Category: Software
Product Number: ADRV9002
Software Version: 2022_R2
I am running a custom board that is having a difficult time tuning the TX channels. 50% of the boots fail to tune either TX1 or TX2, the other 50% pass.
I am running 2022.2. The system does not appear to have any trouble booting if I set the sample rate to 15.36 MSPS (default). However we have included a patch to initialize booting at 61.44 MSPS. NOTE: If we don't include this patch the system successfully boots at 15.36 MSPS, but later fails tuning when we use IIO Oscilloscope to set a new higher sample rate profile.
Here is a log (Some custom messages included) for the system working:
zynq_pm_remap_ocm: OCM pool is not available zynq_pm_suspend_init: Unable to map OCM. Registering SWP/SWPB emulation handler of-fpga-region fpga-full: FPGA Region probed random: fast init done random: crng init done SAMPL CLK: 61440000 tuning: RX1 0:1:2:3:4:5:6:7 0:o o o o o o o o 1:# o o o o o o o 2:# # o o o o o o 3:o # # o o o o o 4:o o # # o o o o 5:o o o # # o o o 6:o o o o # # o o 7:o o o o # # # o adrv9002 spi1.0: sel: 6 off: 0x2000 SAMPL CLK: 61440000 tuning: TX1 0:1:2:3:4:5:6:7 0:o # o o o o o o 1:o o # o o o o o 2:o o o # o o o o 3:o o o o # o o o 4:o o o o o # o o 5:o o o o o o # # 6:o o o o o o o # 7:# o o o o o o o SAMPL CLK: 61440000 tuning: RX2 0:1:2:3:4:5:6:7 0:o o o o o o o o 1:# o o o o o o o 2:# # o o o o o o 3:# # # o o o o o 4:o # # # o o o o 5:o o # # # o o o 6:o o o # # # o o 7:o o o o # # # o adrv9002 spi1.0: sel: 6 off: 0x4000 SAMPL CLK: 61440000 tuning: TX2 0:1:2:3:4:5:6:7 0:o # o o o o o o 1:o o # o o o o o 2:o o o # o o o o 3:o o o o # o o o 4:o o o o o # o o 5:o o o o o o # o 6:o o o o o o o # 7:# o o o o o o o adrv9002 spi1.0: adrv9002-phy Rev 12.0, Firmware 0.22.27, Stream 0.7.10.0, API version: 68.10.1 successfully initialized cf_axi_adc 44a00000.axi-adrv9002-rx-lpc: ADI AIM (10.03.) at 0x44A00000 mapped to 0x60161b7a probed ADC ADRV9002 as MASTER cf_axi_tdd 44a0c800.axi-adrv9002-core-tdd1-lpc: Major version mismatch between PCORE and driver. Driver expected 1.00.a, PCORE reported 173.222. cf_axi_tdd 44a0cc00.axi-adrv9002-core-tdd2-lpc: Major version mismatch between PCORE and driver. Driver expected 1.00.a, PCORE reported 173.222. cf_axi_dds 44a0a000.axi-adrv9002-tx-lpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x44A0A000 mapped to 0x7aa21bde, probed DDS ADRV9002 cf_axi_dds 44a0c000.axi-adrv9002-tx2-lpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x44A0C000 mapped to 0x01e44753, probed DDS ADRV9002 of_cfs_init of_cfs_init: OK clk: Not disabling unused clocks ALSA device list: No soundcards found.
Here is a boot log when the system fails to tune:
zynq_pm_remap_ocm: OCM pool is not available zynq_pm_suspend_init: Unable to map OCM. Registering SWP/SWPB emulation handler of-fpga-region fpga-full: FPGA Region probed random: fast init done random: crng init done SAMPL CLK: 61440000 tuning: RX1 0:1:2:3:4:5:6:7 0:o o o o o o o o 1:# o o o o o o o 2:# # o o o o o o 3:o # # o o o o o 4:o o # # o o o o 5:o o o # # o o o 6:o o o o # # o o 7:o o o o # # # o adrv9002 spi1.0: sel: 6 off: 0x2000 adrv9002 spi1.0: sel: 6 off: 0x2000 SAMPL CLK: 61440000 tuning: TX1 0:1:2:3:4:5:6:7 0:# # # # # # # # 1:# # # # # # # # 2:# # # # # # # # 3:# # # # # # # # 4:# # # # # # # # 5:# # # # # # # # 6:# # # # # # # # 7:# # # # # # # # adrv9002 spi1.0: Interface tuning failed: -5 cf_axi_adc: probe of 44a00000.axi-adrv9002-rx-lpc failed with error -5 of_cfs_init of_cfs_init: OK clk: Not disabling unused clocks ALSA device list: No soundcards found.
Here are my FPGA Selections for the system:
Here is the patch file we are using to set the sample rate:
diff --git a/firmware/Navassa_LVDS_profile.json b/firmware/Navassa_LVDS_profile.json
old mode 100755
new mode 100644
index a5a761107e34..6ff48bafccb2
--- a/firmware/Navassa_LVDS_profile.json
+++ b/firmware/Navassa_LVDS_profile.json
@@ -37,9 +37,9 @@
"rxInitChannelMask": 195,
"rxChannelCfg": [ {
"profile": {
- "primarySigBandwidth_Hz": 9000000,
- "rxOutputRate_Hz": 15360000,
- "rxInterfaceSampleRate_Hz": 15360000,
+ "primarySigBandwidth_Hz": 38000000,
+ "rxOutputRate_Hz": 61440000,
+ "rxInterfaceSampleRate_Hz": 61440000,
"rxOffsetLo_kHz": 0,
"rxNcoEnable": false,
"outputSignaling": 0,
@@ -73,8 +73,8 @@
"decBy2Blk25En": 0,
"decBy2Blk27En": 0,
"decBy2Blk29En": 0,
- "decBy2Blk31En": 1,
- "decBy2Blk33En": 1,
+ "decBy2Blk31En": 0,
+ "decBy2Blk33En": 0,
"wbLpfBlk33p1En": 0
},
"rxDecTop": {
@@ -102,7 +102,7 @@
"rxNbNcoEn": 1,
"rxNbNcoConfig": {
"freq": 0,
- "sampleFreq": 15360000,
+ "sampleFreq": 61440000,
"phase": 0,
"realOut": 0
}
@@ -155,9 +155,9 @@
}
}, {
"profile": {
- "primarySigBandwidth_Hz": 9000000,
- "rxOutputRate_Hz": 15360000,
- "rxInterfaceSampleRate_Hz": 15360000,
+ "primarySigBandwidth_Hz": 38000000,
+ "rxOutputRate_Hz": 61440000,
+ "rxInterfaceSampleRate_Hz": 61440000,
"rxOffsetLo_kHz": 0,
"rxNcoEnable": false,
"outputSignaling": 0,
@@ -191,8 +191,8 @@
"decBy2Blk25En": 0,
"decBy2Blk27En": 0,
"decBy2Blk29En": 0,
- "decBy2Blk31En": 1,
- "decBy2Blk33En": 1,
+ "decBy2Blk31En": 0,
+ "decBy2Blk33En": 0,
"wbLpfBlk33p1En": 0
},
"rxDecTop": {
@@ -220,7 +220,7 @@
"rxNbNcoEn": 1,
"rxNbNcoConfig": {
"freq": 0,
- "sampleFreq": 15360000,
+ "sampleFreq": 61440000,
"phase": 0,
"realOut": 0
}
@@ -509,9 +509,9 @@
}
}, {
"profile": {
- "primarySigBandwidth_Hz": 9000000,
- "rxOutputRate_Hz": 15360000,
- "rxInterfaceSampleRate_Hz": 15360000,
+ "primarySigBandwidth_Hz": 38000000,
+ "rxOutputRate_Hz": 61440000,
+ "rxInterfaceSampleRate_Hz": 61440000,
"rxOffsetLo_kHz": 0,
"rxNcoEnable": false,
"outputSignaling": 0,
@@ -545,8 +545,8 @@
"decBy2Blk25En": 0,
"decBy2Blk27En": 0,
"decBy2Blk29En": 0,
- "decBy2Blk31En": 1,
- "decBy2Blk33En": 1,
+ "decBy2Blk31En": 0,
+ "decBy2Blk33En": 0,
"wbLpfBlk33p1En": 0
},
"rxDecTop": {
@@ -627,9 +627,9 @@
}
}, {
"profile": {
- "primarySigBandwidth_Hz": 9000000,
- "rxOutputRate_Hz": 15360000,
- "rxInterfaceSampleRate_Hz": 15360000,
+ "primarySigBandwidth_Hz": 38000000,
+ "rxOutputRate_Hz": 61440000,
+ "rxInterfaceSampleRate_Hz": 61440000,
"rxOffsetLo_kHz": 0,
"rxNcoEnable": false,
"outputSignaling": 0,
@@ -663,8 +663,8 @@
"decBy2Blk25En": 0,
"decBy2Blk27En": 0,
"decBy2Blk29En": 0,
- "decBy2Blk31En": 1,
- "decBy2Blk33En": 1,
+ "decBy2Blk31En": 0,
+ "decBy2Blk33En": 0,
"wbLpfBlk33p1En": 0
},
"rxDecTop": {
@@ -984,9 +984,9 @@
"tx": {
"txInitChannelMask": 12,
"txProfile": [ {
- "primarySigBandwidth_Hz": 9000000,
- "txInputRate_Hz": 15360000,
- "txInterfaceSampleRate_Hz": 15360000,
+ "primarySigBandwidth_Hz": 38000000,
+ "txInputRate_Hz": 61440000,
+ "txInterfaceSampleRate_Hz": 61440000,
"txOffsetLo_kHz": 0,
"validDataDelay": 0,
"txBbf3dBCorner_kHz": 50000,
@@ -1015,8 +1015,8 @@
"txInterpBy2Blk30En": 0,
"txInterpBy2Blk28En": 0,
"txInterpBy2Blk26En": 0,
- "txInterpBy2Blk24En": 1,
- "txInterpBy2Blk22En": 1,
+ "txInterpBy2Blk24En": 0,
+ "txInterpBy2Blk22En": 0,
"txWbLpfBlk22p1En": 0
},
"txNbIntTop": {
@@ -1079,9 +1079,9 @@
"rxMaskStrobeEn": false
}
}, {
- "primarySigBandwidth_Hz": 9000000,
- "txInputRate_Hz": 15360000,
- "txInterfaceSampleRate_Hz": 15360000,
+ "primarySigBandwidth_Hz": 38000000,
+ "txInputRate_Hz": 61440000,
+ "txInterfaceSampleRate_Hz": 61440000,
"txOffsetLo_kHz": 0,
"validDataDelay": 0,
"txBbf3dBCorner_kHz": 50000,
@@ -1110,8 +1110,8 @@
"txInterpBy2Blk30En": 0,
"txInterpBy2Blk28En": 0,
"txInterpBy2Blk26En": 0,
- "txInterpBy2Blk24En": 1,
- "txInterpBy2Blk22En": 1,
+ "txInterpBy2Blk24En": 0,
+ "txInterpBy2Blk22En": 0,
"txWbLpfBlk22p1En": 0
},
"txNbIntTop": {
What is confusing me most is that this issue is not consistent, I'm trying to think of what could be causing every delay value to fail. Do you have any recommendations on things I should be looking into?