TX Tuning failed (-5) on custom board

Jcrash29V

on Apr 2, 2024

Category: Software

Product Number: ADRV9002

Software Version: 2022_R2

I am running a custom board that is having a difficult time tuning the TX channels. 50% of the boots fail to tune either TX1 or TX2, the other 50% pass.

I am running 2022.2. The system does not appear to have any trouble booting if I set the sample rate to 15.36 MSPS (default). However we have included a patch to initialize booting at 61.44 MSPS. NOTE: If we don't include this patch the system successfully boots at 15.36 MSPS, but later fails tuning when we use IIO Oscilloscope to set a new higher sample rate profile.

Here is a log (Some custom messages included) for the system working:

zynq_pm_remap_ocm: OCM pool is not available
zynq_pm_suspend_init: Unable to map OCM.
Registering SWP/SWPB emulation handler
of-fpga-region fpga-full: FPGA Region probed
random: fast init done
random: crng init done
SAMPL CLK: 61440000 tuning: RX1
  0:1:2:3:4:5:6:7
0:o o o o o o o o
1:# o o o o o o o
2:# # o o o o o o
3:o # # o o o o o
4:o o # # o o o o
5:o o o # # o o o
6:o o o o # # o o
7:o o o o # # # o
adrv9002 spi1.0: sel: 6 off: 0x2000
SAMPL CLK: 61440000 tuning: TX1
  0:1:2:3:4:5:6:7
0:o # o o o o o o
1:o o # o o o o o
2:o o o # o o o o
3:o o o o # o o o
4:o o o o o # o o
5:o o o o o o # #
6:o o o o o o o #
7:# o o o o o o o
SAMPL CLK: 61440000 tuning: RX2
  0:1:2:3:4:5:6:7
0:o o o o o o o o
1:# o o o o o o o
2:# # o o o o o o
3:# # # o o o o o
4:o # # # o o o o
5:o o # # # o o o
6:o o o # # # o o
7:o o o o # # # o
adrv9002 spi1.0: sel: 6 off: 0x4000
SAMPL CLK: 61440000 tuning: TX2
  0:1:2:3:4:5:6:7
0:o # o o o o o o
1:o o # o o o o o
2:o o o # o o o o
3:o o o o # o o o
4:o o o o o # o o
5:o o o o o o # o
6:o o o o o o o #
7:# o o o o o o o
adrv9002 spi1.0: adrv9002-phy Rev 12.0, Firmware 0.22.27,  Stream 0.7.10.0,  API version: 68.10.1 successfully initialized
cf_axi_adc 44a00000.axi-adrv9002-rx-lpc: ADI AIM (10.03.) at 0x44A00000 mapped to 0x60161b7a probed ADC ADRV9002 as MASTER
cf_axi_tdd 44a0c800.axi-adrv9002-core-tdd1-lpc: Major version mismatch between PCORE and driver. Driver expected 1.00.a, PCORE reported 173.222.
cf_axi_tdd 44a0cc00.axi-adrv9002-core-tdd2-lpc: Major version mismatch between PCORE and driver. Driver expected 1.00.a, PCORE reported 173.222.
cf_axi_dds 44a0a000.axi-adrv9002-tx-lpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x44A0A000 mapped to 0x7aa21bde, probed DDS ADRV9002
cf_axi_dds 44a0c000.axi-adrv9002-tx2-lpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x44A0C000 mapped to 0x01e44753, probed DDS ADRV9002
of_cfs_init
of_cfs_init: OK
clk: Not disabling unused clocks
ALSA device list:
  No soundcards found.

Here is a boot log when the system fails to tune:

zynq_pm_remap_ocm: OCM pool is not available
zynq_pm_suspend_init: Unable to map OCM.
Registering SWP/SWPB emulation handler
of-fpga-region fpga-full: FPGA Region probed
random: fast init done
random: crng init done
SAMPL CLK: 61440000 tuning: RX1
  0:1:2:3:4:5:6:7
0:o o o o o o o o
1:# o o o o o o o
2:# # o o o o o o
3:o # # o o o o o
4:o o # # o o o o
5:o o o # # o o o
6:o o o o # # o o
7:o o o o # # # o
adrv9002 spi1.0: sel: 6 off: 0x2000
adrv9002 spi1.0: sel: 6 off: 0x2000
SAMPL CLK: 61440000 tuning: TX1
  0:1:2:3:4:5:6:7
0:# # # # # # # #
1:# # # # # # # #
2:# # # # # # # #
3:# # # # # # # #
4:# # # # # # # #
5:# # # # # # # #
6:# # # # # # # #
7:# # # # # # # #
adrv9002 spi1.0: Interface tuning failed: -5
cf_axi_adc: probe of 44a00000.axi-adrv9002-rx-lpc failed with error -5
of_cfs_init
of_cfs_init: OK
clk: Not disabling unused clocks
ALSA device list:
  No soundcards found.

Here are my FPGA Selections for the system:

Here is the patch file we are using to set the sample rate:

diff --git a/firmware/Navassa_LVDS_profile.json b/firmware/Navassa_LVDS_profile.json
old mode 100755
new mode 100644
index a5a761107e34..6ff48bafccb2
--- a/firmware/Navassa_LVDS_profile.json
+++ b/firmware/Navassa_LVDS_profile.json
@@ -37,9 +37,9 @@
     "rxInitChannelMask": 195,
     "rxChannelCfg": [ {
         "profile": {
-          "primarySigBandwidth_Hz": 9000000,
-          "rxOutputRate_Hz": 15360000,
-          "rxInterfaceSampleRate_Hz": 15360000,
+          "primarySigBandwidth_Hz": 38000000,
+          "rxOutputRate_Hz": 61440000,
+          "rxInterfaceSampleRate_Hz": 61440000,
           "rxOffsetLo_kHz": 0,
           "rxNcoEnable": false,
           "outputSignaling": 0,
@@ -73,8 +73,8 @@
               "decBy2Blk25En": 0,
               "decBy2Blk27En": 0,
               "decBy2Blk29En": 0,
-              "decBy2Blk31En": 1,
-              "decBy2Blk33En": 1,
+              "decBy2Blk31En": 0,
+              "decBy2Blk33En": 0,
               "wbLpfBlk33p1En": 0
             },
             "rxDecTop": {
@@ -102,7 +102,7 @@
                 "rxNbNcoEn": 1,
                 "rxNbNcoConfig": {
                   "freq": 0,
-                  "sampleFreq": 15360000,
+                  "sampleFreq": 61440000,
                   "phase": 0,
                   "realOut": 0
                 }
@@ -155,9 +155,9 @@
         }
       }, {
         "profile": {
-          "primarySigBandwidth_Hz": 9000000,
-          "rxOutputRate_Hz": 15360000,
-          "rxInterfaceSampleRate_Hz": 15360000,
+          "primarySigBandwidth_Hz": 38000000,
+          "rxOutputRate_Hz": 61440000,
+          "rxInterfaceSampleRate_Hz": 61440000,
           "rxOffsetLo_kHz": 0,
           "rxNcoEnable": false,
           "outputSignaling": 0,
@@ -191,8 +191,8 @@
               "decBy2Blk25En": 0,
               "decBy2Blk27En": 0,
               "decBy2Blk29En": 0,
-              "decBy2Blk31En": 1,
-              "decBy2Blk33En": 1,
+              "decBy2Blk31En": 0,
+              "decBy2Blk33En": 0,
               "wbLpfBlk33p1En": 0
             },
             "rxDecTop": {
@@ -220,7 +220,7 @@
                 "rxNbNcoEn": 1,
                 "rxNbNcoConfig": {
                   "freq": 0,
-                  "sampleFreq": 15360000,
+                  "sampleFreq": 61440000,
                   "phase": 0,
                   "realOut": 0
                 }
@@ -509,9 +509,9 @@
         }
       }, {
         "profile": {
-          "primarySigBandwidth_Hz": 9000000,
-          "rxOutputRate_Hz": 15360000,
-          "rxInterfaceSampleRate_Hz": 15360000,
+          "primarySigBandwidth_Hz": 38000000,
+          "rxOutputRate_Hz": 61440000,
+          "rxInterfaceSampleRate_Hz": 61440000,
           "rxOffsetLo_kHz": 0,
           "rxNcoEnable": false,
           "outputSignaling": 0,
@@ -545,8 +545,8 @@
               "decBy2Blk25En": 0,
               "decBy2Blk27En": 0,
               "decBy2Blk29En": 0,
-              "decBy2Blk31En": 1,
-              "decBy2Blk33En": 1,
+              "decBy2Blk31En": 0,
+              "decBy2Blk33En": 0,
               "wbLpfBlk33p1En": 0
             },
             "rxDecTop": {
@@ -627,9 +627,9 @@
         }
       }, {
         "profile": {
-          "primarySigBandwidth_Hz": 9000000,
-          "rxOutputRate_Hz": 15360000,
-          "rxInterfaceSampleRate_Hz": 15360000,
+          "primarySigBandwidth_Hz": 38000000,
+          "rxOutputRate_Hz": 61440000,
+          "rxInterfaceSampleRate_Hz": 61440000,
           "rxOffsetLo_kHz": 0,
           "rxNcoEnable": false,
           "outputSignaling": 0,
@@ -663,8 +663,8 @@
               "decBy2Blk25En": 0,
               "decBy2Blk27En": 0,
               "decBy2Blk29En": 0,
-              "decBy2Blk31En": 1,
-              "decBy2Blk33En": 1,
+              "decBy2Blk31En": 0,
+              "decBy2Blk33En": 0,
               "wbLpfBlk33p1En": 0
             },
             "rxDecTop": {
@@ -984,9 +984,9 @@
   "tx": {
     "txInitChannelMask": 12,
     "txProfile": [ {
-        "primarySigBandwidth_Hz": 9000000,
-        "txInputRate_Hz": 15360000,
-        "txInterfaceSampleRate_Hz": 15360000,
+        "primarySigBandwidth_Hz": 38000000,
+        "txInputRate_Hz": 61440000,
+        "txInterfaceSampleRate_Hz": 61440000,
         "txOffsetLo_kHz": 0,
         "validDataDelay": 0,
         "txBbf3dBCorner_kHz": 50000,
@@ -1015,8 +1015,8 @@
             "txInterpBy2Blk30En": 0,
             "txInterpBy2Blk28En": 0,
             "txInterpBy2Blk26En": 0,
-            "txInterpBy2Blk24En": 1,
-            "txInterpBy2Blk22En": 1,
+            "txInterpBy2Blk24En": 0,
+            "txInterpBy2Blk22En": 0,
             "txWbLpfBlk22p1En": 0
           },
           "txNbIntTop": {
@@ -1079,9 +1079,9 @@
           "rxMaskStrobeEn": false
         }
       }, {
-        "primarySigBandwidth_Hz": 9000000,
-        "txInputRate_Hz": 15360000,
-        "txInterfaceSampleRate_Hz": 15360000,
+        "primarySigBandwidth_Hz": 38000000,
+        "txInputRate_Hz": 61440000,
+        "txInterfaceSampleRate_Hz": 61440000,
         "txOffsetLo_kHz": 0,
         "validDataDelay": 0,
         "txBbf3dBCorner_kHz": 50000,
@@ -1110,8 +1110,8 @@
             "txInterpBy2Blk30En": 0,
             "txInterpBy2Blk28En": 0,
             "txInterpBy2Blk26En": 0,
-            "txInterpBy2Blk24En": 1,
-            "txInterpBy2Blk22En": 1,
+            "txInterpBy2Blk24En": 0,
+            "txInterpBy2Blk22En": 0,
             "txWbLpfBlk22p1En": 0
           },
           "txNbIntTop": {

What is confusing me most is that this issue is not consistent, I'm trying to think of what could be causing every delay value to fail. Do you have any recommendations on things I should be looking into?

Tags: software linux kernel driver ADRV9002 tuning 2022_R2 Wideband Transceiver IC rf and microwave RF Integrated Transceivers Show More

Parents

0 Jcrash29V

on Apr 5, 2024 9:50 AM

I realized that adrv9002.c didnt print debug messages even with #define DEBUG. Therefore I modified the code to make them all print:

Key type dns_resolver registered
Registering SWP/SWPB emulation handler
of-fpga-region fpga-full: FPGA Region probed
mmc0: new high speed SDHC card at address 0001
mmcblk0: mmc0:0001 SD16G 14.5 GiB
 mmcblk0: p1
adrv9002 spi1.0: RX1 enabled
adrv9002 spi1.0: TX1 enabled
adrv9002 spi1.0: RX2 enabled
adrv9002 spi1.0: TX2 enabled
adrv9002 spi1.0: pos: 15, Chan1:1BE5F7, Chan2:1BE5F7
random: fast init done
random: crng init done
adrv9002 spi1.0: Set dpgio: 1, signal: 0
adrv9002 spi1.0: Set dpgio: 2, signal: 1
adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 61440000 Hz
adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 61440000 Hz
adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 61440000 Hz
adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 61440000 Hz
adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 61440000 Hz
adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 61440000 Hz
adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 61440000 Hz
adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 61440000 Hz
adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 122880000 Hz
adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 122880000 Hz
adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 122880000 Hz
adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 122880000 Hz
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:0
adrv9002 spi1.0: Set intf delay clk:0, d_i:0, d_q:0, d_s:0, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:0, d_i:1, d_q:1, d_s:1, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:0, d_i:2, d_q:2, d_s:2, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:0, d_i:3, d_q:3, d_s:3, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:0, d_i:4, d_q:4, d_s:4, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:0, d_i:5, d_q:5, d_s:5, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:0, d_i:6, d_q:6, d_s:6, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:0, d_i:7, d_q:7, d_s:7, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:1, d_i:0, d_q:0, d_s:0, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:1, d_i:1, d_q:1, d_s:1, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:1, d_i:2, d_q:2, d_s:2, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:1, d_i:3, d_q:3, d_s:3, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:1, d_i:4, d_q:4, d_s:4, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:1, d_i:5, d_q:5, d_s:5, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:1, d_i:6, d_q:6, d_s:6, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:1, d_i:7, d_q:7, d_s:7, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:2, d_i:0, d_q:0, d_s:0, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:2, d_i:1, d_q:1, d_s:1, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:2, d_i:2, d_q:2, d_s:2, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:2, d_i:3, d_q:3, d_s:3, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:2, d_i:4, d_q:4, d_s:4, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:2, d_i:5, d_q:5, d_s:5, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:2, d_i:6, d_q:6, d_s:6, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:2, d_i:7, d_q:7, d_s:7, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:3, d_i:0, d_q:0, d_s:0, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:3, d_i:1, d_q:1, d_s:1, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:3, d_i:2, d_q:2, d_s:2, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:3, d_i:3, d_q:3, d_s:3, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:3, d_i:4, d_q:4, d_s:4, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:3, d_i:5, d_q:5, d_s:5, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:3, d_i:6, d_q:6, d_s:6, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:3, d_i:7, d_q:7, d_s:7, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:4, d_i:0, d_q:0, d_s:0, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:4, d_i:1, d_q:1, d_s:1, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:4, d_i:2, d_q:2, d_s:2, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:4, d_i:3, d_q:3, d_s:3, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:4, d_i:4, d_q:4, d_s:4, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:4, d_i:5, d_q:5, d_s:5, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:4, d_i:6, d_q:6, d_s:6, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:4, d_i:7, d_q:7, d_s:7, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:5, d_i:0, d_q:0, d_s:0, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:5, d_i:1, d_q:1, d_s:1, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:5, d_i:2, d_q:2, d_s:2, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:5, d_i:3, d_q:3, d_s:3, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:5, d_i:4, d_q:4, d_s:4, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:5, d_i:5, d_q:5, d_s:5, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:5, d_i:6, d_q:6, d_s:6, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:5, d_i:7, d_q:7, d_s:7, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:6, d_i:0, d_q:0, d_s:0, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:6, d_i:1, d_q:1, d_s:1, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:6, d_i:2, d_q:2, d_s:2, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:6, d_i:3, d_q:3, d_s:3, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:6, d_i:4, d_q:4, d_s:4, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:6, d_i:5, d_q:5, d_s:5, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:6, d_i:6, d_q:6, d_s:6, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:6, d_i:7, d_q:7, d_s:7, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:7, d_i:0, d_q:0, d_s:0, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:7, d_i:1, d_q:1, d_s:1, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:7, d_i:2, d_q:2, d_s:2, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:7, d_i:3, d_q:3, d_s:3, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:7, d_i:4, d_q:4, d_s:4, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:7, d_i:5, d_q:5, d_s:5, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:7, d_i:6, d_q:6, d_s:6, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:7, d_i:7, d_q:7, d_s:7, tx:0 c:0
SAMPL CLK: 61440000 tuning: RX1
  0:1:2:3:4:5:6:7
0:o o o o o o o o
1:# o o o o o o o
2:# # o o o o o o
3:o # # o o o o o
4:o o # # o o o o
5:o o o # # o o o
6:o o o o # # o o
7:o o o o o # # o
adrv9002 spi1.0: cfg test stop:1, ssi:2, c:0, tx:0
adrv9002 spi1.0: RX: Got clk: 0, data: 4
adrv9002 spi1.0: Set intf delay clk:0, d_i:0, d_q:0, d_s:0, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:0, d_i:1, d_q:1, d_s:1, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:0, d_i:2, d_q:2, d_s:2, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:0, d_i:3, d_q:3, d_s:3, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:0, d_i:4, d_q:4, d_s:4, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:0, d_i:5, d_q:5, d_s:5, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:0, d_i:6, d_q:6, d_s:6, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:0, d_i:7, d_q:7, d_s:7, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:1, d_i:0, d_q:0, d_s:0, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:1, d_i:1, d_q:1, d_s:1, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:1, d_i:2, d_q:2, d_s:2, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:1, d_i:3, d_q:3, d_s:3, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:1, d_i:4, d_q:4, d_s:4, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:1, d_i:5, d_q:5, d_s:5, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:1, d_i:6, d_q:6, d_s:6, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:1, d_i:7, d_q:7, d_s:7, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:2, d_i:0, d_q:0, d_s:0, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:2, d_i:1, d_q:1, d_s:1, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:2, d_i:2, d_q:2, d_s:2, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:2, d_i:3, d_q:3, d_s:3, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:2, d_i:4, d_q:4, d_s:4, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:2, d_i:5, d_q:5, d_s:5, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:2, d_i:6, d_q:6, d_s:6, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:2, d_i:7, d_q:7, d_s:7, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:3, d_i:0, d_q:0, d_s:0, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:3, d_i:1, d_q:1, d_s:1, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:3, d_i:2, d_q:2, d_s:2, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:3, d_i:3, d_q:3, d_s:3, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:93, f_f:0 f_e:1, s_e:1
adrv9002 spi1.0: Set intf delay clk:3, d_i:4, d_q:4, d_s:4, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:3, d_i:5, d_q:5, d_s:5, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:3, d_i:6, d_q:6, d_s:6, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:3, d_i:7, d_q:7, d_s:7, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:4, d_i:0, d_q:0, d_s:0, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:4, d_i:1, d_q:1, d_s:1, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:4, d_i:2, d_q:2, d_s:2, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:4, d_i:3, d_q:3, d_s:3, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:4, d_i:4, d_q:4, d_s:4, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:4, d_i:5, d_q:5, d_s:5, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:4, d_i:6, d_q:6, d_s:6, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:4, d_i:7, d_q:7, d_s:7, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:5, d_i:0, d_q:0, d_s:0, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:5, d_i:1, d_q:1, d_s:1, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:5, d_i:2, d_q:2, d_s:2, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:5, d_i:3, d_q:3, d_s:3, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:5, d_i:4, d_q:4, d_s:4, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:5, d_i:5, d_q:5, d_s:5, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:5, d_i:6, d_q:6, d_s:6, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:5, d_i:7, d_q:7, d_s:7, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:6, d_i:0, d_q:0, d_s:0, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:6, d_i:1, d_q:1, d_s:1, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:6, d_i:2, d_q:2, d_s:2, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:6, d_i:3, d_q:3, d_s:3, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:6, d_i:4, d_q:4, d_s:4, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:6, d_i:5, d_q:5, d_s:5, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:6, d_i:6, d_q:6, d_s:6, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:6, d_i:7, d_q:7, d_s:7, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:7, d_i:0, d_q:0, d_s:0, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:7, d_i:1, d_q:1, d_s:1, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:7, d_i:2, d_q:2, d_s:2, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:7, d_i:3, d_q:3, d_s:3, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:7, d_i:4, d_q:4, d_s:4, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:7, d_i:5, d_q:5, d_s:5, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:7, d_i:6, d_q:6, d_s:6, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:7, d_i:7, d_q:7, d_s:7, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:0
SAMPL CLK: 61440000 tuning: TX1
  0:1:2:3:4:5:6:7
0:# # # # # # # #
1:# # # # # # # #
2:# # # # # # # #
3:# # # # # # # #
4:# # # # # # # #
5:# # # # # # # #
6:# # # # # # # #
7:# # # # # # # #
adrv9002 spi1.0: cfg test stop:1, ssi:2, c:0, tx:1
adrv9002 spi1.0: Interface tuning failed: -5
cf_axi_adc: probe of 44a00000.axi-adrv9002-rx-lpc failed with error -5

It appears when things go wrong, I am getting a lot of strobe errors. Even when I don't get strobe errors, I am still getting data errors.

adrv9002 spi1.0: Set intf delay clk:7, d_i:7, d_q:7, d_s:7, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:0

adrv9002 spi1.0: Set intf delay clk:6, d_i:7, d_q:7, d_s:7, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:255, f_f:0 f_e:0, s_e:1

Maybe this will help narrow things down?

0 nsa

on Apr 8, 2024 4:16 AM in reply to Jcrash29V
Hi,

Jcrash29V said:
I realized that adrv9002.c didnt print debug messages even with #define DEBUG. Therefore I modified the code to make them all print:

Are you sure you placed the line right before all the "#includes"?

We did saw some issues on a platform we have on TX2 but not failing like this on interface tuning. We did however some improvements that made interface tuning for the 61.44MSPS profile much more stable for TX2. Can you give a test to this branch? I'm applying the same fix (actually a not so pretty workaround) to TX1. If this does not help, I'll have to ask one of our HDL folks to help you ( I can only help you with the driver).

- Nuno Sá
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0 Jcrash29V

on Apr 9, 2024 10:50 AM in reply to nsa

Hi Nuno,

I created a patch based on your staging branch:

Here is the log:

NET: Registered PF_PACKET protocol family
NET: Registered PF_IEEE802154 protocol family
Key type dns_resolver registered
zynq_pm_remap_ocm: OCM pool is not available
zynq_pm_suspend_init: Unable to map OCM.
Registering SWP/SWPB emulation handler
of-fpga-region fpga-full: FPGA Region probed
adrv9002 spi1.0: RX1 enabled
adrv9002 spi1.0: TX1 enabled
adrv9002 spi1.0: RX2 enabled
adrv9002 spi1.0: TX2 enabled
adrv9002 spi1.0: pos: 15, Chan1:1BE5F7, Chan2:1BE5F7
random: fast init done
random: crng init done
adrv9002 spi1.0: Set dpgio: 1, signal: 0
adrv9002 spi1.0: Set dpgio: 2, signal: 1
adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 61440000 Hz
adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 61440000 Hz
adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 61440000 Hz
adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 61440000 Hz
adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 61440000 Hz
adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 61440000 Hz
adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 61440000 Hz
adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 61440000 Hz
adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 122880000 Hz
adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 122880000 Hz
adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 122880000 Hz
adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 122880000 Hz
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:0
adrv9002 spi1.0: Set intf delay clk:0, d:0, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:0, d:1, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:0, d:2, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:0, d:3, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:0, d:4, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:0, d:5, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:0, d:6, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:0, d:7, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:1, d:0, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:1, d:1, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:1, d:2, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:1, d:3, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:1, d:4, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:1, d:5, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:1, d:6, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:1, d:7, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:2, d:0, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:2, d:1, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:2, d:2, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:2, d:3, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:2, d:4, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:2, d:5, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:2, d:6, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:2, d:7, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:3, d:0, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:3, d:1, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:3, d:2, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:3, d:3, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:3, d:4, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:3, d:5, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:3, d:6, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:3, d:7, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:4, d:0, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:4, d:1, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:4, d:2, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:4, d:3, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:4, d:4, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:4, d:5, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:4, d:6, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:4, d:7, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:5, d:0, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:5, d:1, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:5, d:2, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:5, d:3, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:5, d:4, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:5, d:5, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:5, d:6, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:5, d:7, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:6, d:0, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:6, d:1, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:6, d:2, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:6, d:3, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:6, d:4, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:6, d:5, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:6, d:6, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:6, d:7, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:7, d:0, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:7, d:1, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:7, d:2, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:7, d:3, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:7, d:4, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:7, d:5, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:7, d:6, tx:0 c:0
adrv9002 spi1.0: Set intf delay clk:7, d:7, tx:0 c:0
SAMPL CLK: 61440000 tuning: RX1
  0:1:2:3:4:5:6:7
0:o o o o o o o o
1:o o o o o o o o
2:o o o o o o o o
3:o o o o o o o o
4:o o o o o o o o
5:o o o o o o o o
6:o o o o o o o o
7:o o o o o o o o
adrv9002 spi1.0: cfg test stop:1, ssi:2, c:0, tx:0
adrv9002 spi1.0: RX: Got clk: 0, data: 4
adrv9002 spi1.0: Set intf delay clk:0, d:0, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:1 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:0, d:1, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:0, d:2, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:0, d:3, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:1
adrv9002 spi1.0: Set intf delay clk:0, d:4, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:0, d:5, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:1 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:0, d:6, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:0, d:7, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:1, d:0, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:1 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:1, d:1, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:1, d:2, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:1, d:3, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:1, d:4, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:1, d:5, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:1, d:6, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:1, d:7, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:2, d:0, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:2, d:1, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:2, d:2, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:2, d:3, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:2, d:4, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:2, d:5, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:2, d:6, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:2, d:7, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:3, d:0, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:3, d:1, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:3, d:2, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:3, d:3, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:3, d:4, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:3, d:5, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:3, d:6, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:3, d:7, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:4, d:0, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:1 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:4, d:1, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:4, d:2, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:4, d:3, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:4, d:4, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:4, d:5, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:4, d:6, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:4, d:7, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:5, d:0, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:5, d:1, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:5, d:2, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:5, d:3, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:5, d:4, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:5, d:5, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:5, d:6, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:1 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:5, d:7, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:6, d:0, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:6, d:1, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:6, d:2, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:6, d:3, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:6, d:4, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:6, d:5, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:6, d:6, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:6, d:7, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:1 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:7, d:0, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:7, d:1, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:7, d:2, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:7, d:3, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:7, d:4, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:7, d:5, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:7, d:6, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:7, d:7, tx:1 c:0
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:0, s_e:1
SAMPL CLK: 61440000 tuning: TX1
  0:1:2:3:4:5:6:7
0:o o o o o o o o
1:o o o o o o o o
2:o o o o o o o o
3:o o o o o o o o
4:o o o o o o o o
5:o o o o o o o o
6:o o o o o o o o
7:o o o o o o o o
adrv9002 spi1.0: cfg test stop:1, ssi:2, c:0, tx:1
adrv9002 spi1.0: TX: Got clk: 0, data: 4
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:0
adrv9002 spi1.0: Set intf delay clk:0, d:0, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:0, d:1, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:0, d:2, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:0, d:3, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:0, d:4, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:0, d:5, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:0, d:6, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:0, d:7, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:1, d:0, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:1, d:1, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:1, d:2, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:1, d:3, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:1, d:4, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:1, d:5, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:1, d:6, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:1, d:7, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:2, d:0, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:2, d:1, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:2, d:2, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:2, d:3, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:2, d:4, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:2, d:5, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:2, d:6, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:2, d:7, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:3, d:0, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:3, d:1, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:3, d:2, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:3, d:3, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:3, d:4, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:3, d:5, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:3, d:6, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:3, d:7, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:4, d:0, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:4, d:1, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:4, d:2, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:4, d:3, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:4, d:4, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:4, d:5, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:4, d:6, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:4, d:7, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:5, d:0, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:5, d:1, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:5, d:2, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:5, d:3, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:5, d:4, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:5, d:5, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:5, d:6, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:5, d:7, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:6, d:0, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:6, d:1, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:6, d:2, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:6, d:3, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:6, d:4, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:6, d:5, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:6, d:6, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:6, d:7, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:7, d:0, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:7, d:1, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:7, d:2, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:7, d:3, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:7, d:4, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:7, d:5, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:7, d:6, tx:0 c:1
adrv9002 spi1.0: Set intf delay clk:7, d:7, tx:0 c:1
SAMPL CLK: 61440000 tuning: RX2
  0:1:2:3:4:5:6:7
0:o o o o o o o o
1:# o o o o o o o
2:# # o o o o o o
3:o # # o o o o o
4:o o # # o o o o
5:o o o # # o o o
6:o o o o # # o o
7:o o o o # # # o
adrv9002 spi1.0: cfg test stop:1, ssi:2, c:1, tx:0
adrv9002 spi1.0: RX: Got clk: 0, data: 4
adrv9002 spi1.0: Set intf delay clk:0, d:0, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:0, d:1, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:0, d:2, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:0, d:3, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:0, d:4, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:0, d:5, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:0, d:6, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:0, d:7, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:1, d:0, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:1 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:1, d:1, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:1, d:2, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:1, d:3, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:1, d:4, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:1, d:5, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
adrv9002 spi1.0: Set intf delay clk:1, d:6, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:1, d:7, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:2, d:0, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:2, d:1, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:2, d:2, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:2, d:3, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:2, d:4, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:2, d:5, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:2, d:6, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:2, d:7, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:3, d:0, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:3, d:1, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:3, d:2, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:3, d:3, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:3, d:4, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:3, d:5, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:3, d:6, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:3, d:7, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:4, d:0, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:4, d:1, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:4, d:2, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:4, d:3, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:4, d:4, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:1 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:4, d:5, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:4, d:6, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:4, d:7, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:5, d:0, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:5, d:1, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:5, d:2, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:5, d:3, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:5, d:4, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:5, d:5, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:5, d:6, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:5, d:7, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:6, d:0, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:6, d:1, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:6, d:2, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:6, d:3, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:6, d:4, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:6, d:5, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:6, d:6, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:6, d:7, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:0
adrv9002 spi1.0: Set intf delay clk:7, d:0, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:7, d:1, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:7, d:2, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:7, d:3, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:1
adrv9002 spi1.0: Set intf delay clk:7, d:4, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:7, d:5, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:7, d:6, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:0, s_e:1
adrv9002 spi1.0: Set intf delay clk:7, d:7, tx:1 c:1
adrv9002 spi1.0: cfg test stop:0, ssi:2, c:1, tx:1
adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:1
SAMPL CLK: 61440000 tuning: TX2
  0:1:2:3:4:5:6:7
0:o o o o o o o o
1:o o o o o o o o
2:o o o o o o o o
3:o o o o o o o o
4:o o o o o o o o
5:o o o o o o o o
6:o o o o o o o o
7:o o o o o o o o
adrv9002 spi1.0: cfg test stop:1, ssi:2, c:1, tx:1
adrv9002 spi1.0: TX: Got clk: 0, data: 4
adrv9002 spi1.0: [ERROR]: Error number  1 (0x00000001), Recovery action -2.In file drivers/iio/adc/navassa/devices/adrv9001/public/src/adi_adrv9001_arm.c, in function adi_adrv9001_arm_Version, in line  865, variable name device.Error message ARM binary must be loaded before calling ArmVersionGet().
adrv9002 spi1.0: adrv9002_post_init, 4619: failed with "ARM binary must be loaded before calling ArmVersionGet()" (1)
adrv9002 spi1.0: [ERROR]: Error number  1 (0x00000001), Recovery action -2.In file drivers/iio/adc/navassa/devices/adrv9001/public/src/adi_adrv9001_stream.c, in function adi_adrv9001_Stream_Version, in line  299, variable name device.Error message Stream processor binary must be loaded before calling adi_adrv9001_stream_Version().
adrv9002 spi1.0: adrv9002_post_init, 4621: failed with "Stream processor binary must be loaded before calling adi_adrv9001_stream_Version()" (1)
adrv9002 spi1.0: adrv9002-phy Rev 12.0, Firmware 28.67.112,  Stream 1.0.0.0,  API version: 68.10.1 successfully initialized
cf_axi_adc 44a00000.axi-adrv9002-rx-lpc: ADI AIM (10.03.) at 0x44A00000 mapped to 0x0bc512b2 probed ADC ADRV9002 as MASTER
cf_axi_tdd 44a0c800.axi-adrv9002-core-tdd1-lpc: Major version mismatch between PCORE and driver. Driver expected 1.00.a, PCORE reported 173.222.
cf_axi_tdd 44a0cc00.axi-adrv9002-core-tdd2-lpc: Major version mismatch between PCORE and driver. Driver expected 1.00.a, PCORE reported 173.222.
cf_axi_dds 44a0a000.axi-adrv9002-tx-lpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x44A0A000 mapped to 0x570d8851, probed DDS ADRV9002
cf_axi_dds 44a0c000.axi-adrv9002-tx2-lpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x44A0C000 mapped to 0x15b4e533, probed DDS ADRV9002
of_cfs_init
of_cfs_init: OK
clk: Not disabling unused clocks

Some interesting points:

* I appear to still be getting strobe errors "s_e", but the tuning appears to be "valid"?

* The Errors at the end seems to indicate that the ADRV isn't programmed?

* When I run iio-oscilliscope the system errors out with the following error:

adrv9002 spi1.0: [ERROR]: Error number  3 (0x00000003), Recovery action -101.In file drivers/iio/adc/navassa/devices/adrv9001/public/src/adi_adrv9001_arm.c, in function adi_adrv9001_arm_Cmd_Write, in line  828, variable name device.Error message ARM Mailbox Busy. Command not executed in ArmCmdWrite().
adrv9002 spi1.0: [ERROR]: Error number  3 (0x00000003), Recovery action -101.In file drivers/iio/adc/navassa/devices/adrv9001/public/src/adi_adrv9001.c, in function adi_adrv9001_Temperature_Get, in line  552, variable name NULL.Error message ARM Mailbox Busy. Command not executed in ArmCmdWrite().
adrv9002 spi1.0: adrv9002_phy_read_raw_no_rf_chan, 2200: failed with "ARM Mailbox Busy. Command not executed in ArmCmdWrite()" (3)

Any other thoughts? Want me to try a different driver change?

0 nsa

on Apr 15, 2024 4:13 AM in reply to Jcrash29V
Jcrash29V said:
I created a patch based on your staging branch:

What do you mean by this? I would suggest to use the branch as-is and build it.

Jcrash29V said:
* When I run iio-oscilliscope the system errors out with the following error:

Hmm, the logs don't show much... But the system seems to be in a weird state already.

Jcrash29V said:
I appear to still be getting strobe errors "s_e", but the tuning appears to be "valid"?

We only error out on data errors...

Also, I would not expect to see a "clean" map in TX1/TX2 and even more strange on RX1...

- Nuno Sá
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0 nsa

on Apr 15, 2024 4:13 AM in reply to Jcrash29V
Jcrash29V said:
I created a patch based on your staging branch:

What do you mean by this? I would suggest to use the branch as-is and build it.

Jcrash29V said:
* When I run iio-oscilliscope the system errors out with the following error:

Hmm, the logs don't show much... But the system seems to be in a weird state already.

Jcrash29V said:
I appear to still be getting strobe errors "s_e", but the tuning appears to be "valid"?

We only error out on data errors...

Also, I would not expect to see a "clean" map in TX1/TX2 and even more strange on RX1...

- Nuno Sá
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TX Tuning failed (-5) on custom board