Unable to build hdl design on VIVADO 2019.2

On the wiki pages you may want to consider setting the history back to early 2020. Perhaps the guide has changed?

Hello,

I fallows below step:

mkdir adi
cd adi
git clone github.com/.../hdl.git
ls
cd hdl/
ls
git status
git branch
git branch -a
git checkout hdl_2019_r2
git rebase origin/hdl_2019_r2
cd projects
ls
cd ad7768evb/
export PATH=$PATH:"tools/Xilinx/Vivado/2019.2/bin"
export PATH=$PATH:"tools/Xilinx/Vitis/2019.2/bin"
make

On the wiki pages you may want to consider setting the history back to early 2020. Perhaps the guide has changed? exact what are trying to say.

Hello,

I fallows below step:

mkdir adi
cd adi
git clone github.com/.../hdl.git
ls
cd hdl/
ls
git status
git branch
git branch -a
git checkout hdl_2019_r2
git rebase origin/hdl_2019_r2
cd projects
ls
cd ad7768evb/
export PATH=$PATH:"tools/Xilinx/Vivado/2019.2/bin"
export PATH=$PATH:"tools/Xilinx/Vitis/2019.2/bin"
make

On the wiki pages you may want to consider setting the history back to early 2020. Perhaps the guide has changed? exact what are trying to say.

Here is the guide from when they were using a 2019.2 example:

Building HDL [Analog Devices Wiki]

the link you provided they are using a 2021.1 version, its possible that the steps to generate are different. I don't know.