I am using an AD9081-FMCA-EBZ on a ZCU102.
I see all of the example device trees on github. Here is an excerpt from the file "zynqmp-zcu102-rev10-ad9082-204c-txmode22-rxmode23-sc1.dts"
// ad9081_204b_txmode_0_rxmode_1: 204C use case with Subclass 0,
// Med. lane rate, using gearbox and PRGOGDIV
// * 1Txs / 1Rxs per MxFE
// * DAC_CLK = 11.52GSPS
// * ADC_CLK = 3.84GSPS
// * Tx I/Q Rate: 960 MSPS (Interpolation of 12x1)
// * Rx I/Q Rate: 960 MSPS (Decimation of 4x1)
// * DAC JESD204B: Mode 22, L=2, M=2, N=N'=12
// * ADC JESD204B: Mode 23, L=2, M=2, N=N'=12
// * DAC-Side JESD204B Lane Rate: 11.88Gbps
// * ADC-Side JESD204B Lane Rate: 11.88Gbps
// HDL Synthesis Parameters:
// JESD_MODE=64B66B \
// RX_RATE=12 \
// RX_PLL_SEL=2 \
// TX_RATE=12 \
// TX_PLL_SEL=2 \
// REF_CLK_RATE=180 \
// RX_JESD_M=2 \
// RX_JESD_L=2 \
// RX_JESD_S=4 \
// RX_JESD_NP=12 \
// TX_JESD_M=2 \
// TX_JESD_L=2 \
// TX_JESD_S=2 \
// TX_JESD_NP=12
The documenting of the HDL build parameters inside the devicetree file, communicates to me, that the HDL build sets the JESD parameters, and the devicetree should match those. That would indicate that the HDL build sets the JESD parameters. The devicetree simply matches what was used during the HDL build.
Am I reading too much into that comment in the devicetree file?
Is it possible to change the JESD parameters at boot time, using the devicetree?
