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What's the difference between Generic Time-Division Duplexing Controller and TDD core built for AD9361?

Category: Software

Hello,

Greeting!

I found there are two Time Division Duplexing core: one is called Generic Time-Division Duplexing Controller and the other is TDD core built for AD9361. They are very similar. I think their difference is that Generic TDD has more output channels, right? I found there are two figs to instruct their principle:

Generic TDD:


TDD for AD9361:

So, I would like to ask if the TCH0 is equal to TVCO. Similarly, TCH1 is equal to TRF and TCH2 is equal to TDP?
Could you give some guidance?

Thanks,

Dongyu

Top Replies

    •  Analog Employees 
    Mar 8, 2024 +1 verified

    Hi  ,

    = Regarding your first question, yes you are right that the generic TDD controller can have up to 32 independent output channels while the AD9361 has 2 independently controlled Receiver channels…

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  • Hi  ,

    = Regarding your first question, yes you are right that the generic TDD controller can have up to 32 independent output channels while the AD9361 has 2 independently controlled Receiver channels and 2 independently controlled Transmitter channels.

    = To answer your second question, TCH0 & TVCO, TCH1 & TRF, and TCH2 & TDP are not the same with each other.

    As what is also described under the Theory of Operation section in Generic Time-Division Duplexing Controller [Analog Devices Wiki], the diagram shows "how different channels (CH0, CH1, and CH2) can be enabled at different times relative to the beginning of a frame."

    TCH0_ON represents when CH0 was enabled and then disabled at TCH0_OFF at Frame 0. This illustrates the basic and central idea of a Time Division Duplex controller wherein the time period of the receive and transmit bursts of the channels can be controlled.

    On the other hand, the TDD diagram you've provided for AD9361 is explained under the TDD Controller section in HDL support for AD9361 TDD mode [Analog Devices Wiki].

    The figure describes the different control signals generated when the TDD controller is used.

    After defining the frame length, the user can define one or two sets of pointers, which will tell the exact location, when the device will start/stop a receive/transmit burst inside a frame. 

    Start and stop a receive burst consist of the following action points, each point will define a pointer:

    1. Enabling the RX synthesizer (or the Voltage Controlled Oscillator responsible for generating the carrier frequency for transmission and reception) ---> TVCO_ON
    2. Enabling the RX RF path inside the device (ALERT to RX state transition) ---> TRF_ON
    3. Enabling the RX Data path inside the FPGA (the core starts to get valid data from the devices interface) ---> TDP_ON_1/2
    4. Disabling the RX Data path inside the FPGA ---> TDP_OFF_1/2
    5. Disabling the RX RF path inside the device (RX to ALERT state transition) ---> TDRF_OFF
    6. Disabling the RX synthesizer ---> TGVCO_OFF

    Start or stop a transmit burst consist of the following action points, each point will define a pointer:

    1. Enabling the TX synthesizer ---> TVCO_ON
    2. Enabling the TX RF path inside the device (ALERT to TX state transition) ---> TRF_ON
    3. Enabling the TX Data path inside the FPGA (the core starts to push valid data to the devices interface) ---> TDP_ON_1/2
    4. Disabling the TX Data path inside the FPGA ---> TDP_OFF_1/2
    5. Disabling the TX RF path inside the device (TX to ALERT state transition) ---> TDRF_OFF
    6. Disabling the TX synthesizer ---> TGVCO_OFF

    Further details and description about each register, such as VCO_RX_EN, VCO_TX_EN, RF_RX_EN, RF_TX_EN, TX_DP_EN, to mention a few, can be found in this page: Base (common to all cores) [Analog Devices Wiki]Base (common to all cores) [Analog Devices Wiki].


    Thanks and regards,
    Andy

Reply
  • Hi  ,

    = Regarding your first question, yes you are right that the generic TDD controller can have up to 32 independent output channels while the AD9361 has 2 independently controlled Receiver channels and 2 independently controlled Transmitter channels.

    = To answer your second question, TCH0 & TVCO, TCH1 & TRF, and TCH2 & TDP are not the same with each other.

    As what is also described under the Theory of Operation section in Generic Time-Division Duplexing Controller [Analog Devices Wiki], the diagram shows "how different channels (CH0, CH1, and CH2) can be enabled at different times relative to the beginning of a frame."

    TCH0_ON represents when CH0 was enabled and then disabled at TCH0_OFF at Frame 0. This illustrates the basic and central idea of a Time Division Duplex controller wherein the time period of the receive and transmit bursts of the channels can be controlled.

    On the other hand, the TDD diagram you've provided for AD9361 is explained under the TDD Controller section in HDL support for AD9361 TDD mode [Analog Devices Wiki].

    The figure describes the different control signals generated when the TDD controller is used.

    After defining the frame length, the user can define one or two sets of pointers, which will tell the exact location, when the device will start/stop a receive/transmit burst inside a frame. 

    Start and stop a receive burst consist of the following action points, each point will define a pointer:

    1. Enabling the RX synthesizer (or the Voltage Controlled Oscillator responsible for generating the carrier frequency for transmission and reception) ---> TVCO_ON
    2. Enabling the RX RF path inside the device (ALERT to RX state transition) ---> TRF_ON
    3. Enabling the RX Data path inside the FPGA (the core starts to get valid data from the devices interface) ---> TDP_ON_1/2
    4. Disabling the RX Data path inside the FPGA ---> TDP_OFF_1/2
    5. Disabling the RX RF path inside the device (RX to ALERT state transition) ---> TDRF_OFF
    6. Disabling the RX synthesizer ---> TGVCO_OFF

    Start or stop a transmit burst consist of the following action points, each point will define a pointer:

    1. Enabling the TX synthesizer ---> TVCO_ON
    2. Enabling the TX RF path inside the device (ALERT to TX state transition) ---> TRF_ON
    3. Enabling the TX Data path inside the FPGA (the core starts to push valid data to the devices interface) ---> TDP_ON_1/2
    4. Disabling the TX Data path inside the FPGA ---> TDP_OFF_1/2
    5. Disabling the TX RF path inside the device (TX to ALERT state transition) ---> TDRF_OFF
    6. Disabling the TX synthesizer ---> TGVCO_OFF

    Further details and description about each register, such as VCO_RX_EN, VCO_TX_EN, RF_RX_EN, RF_TX_EN, TX_DP_EN, to mention a few, can be found in this page: Base (common to all cores) [Analog Devices Wiki]Base (common to all cores) [Analog Devices Wiki].


    Thanks and regards,
    Andy

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