Hello Team,
we have a setup consisting of ZCU102 and AD9082-FMCA-EBZ. On the provided HDL, I am implementing xilinx roe (https://www.xilinx.com/products/intellectual-property/ef-di-roe-framer.html) and ethernet 10G/25G (https://www.xilinx.com/products/intellectual-property/ef-di-25gemac.html#overview) IP cores. In the repo of ADI kernel, there is a folder of xroeframer and xroetrafficgen (driver required by roe IP core), https://github.com/analogdevicesinc/linux/tree/main/drivers/staging, but I am not sure if it is already included in the kernel. If it is not included, then what should be the option to be checked in the menu so that the above mentioned folders can be included while compiling new kernel from source. On the other hand, if it is already included how can I check the status of the driver for any error in the system? Moreover, the IP core needs si570_mgt clock source which in .dtb is setup at 148.5MHz but we need at 156.25 MHz. I hope this will not create issue with the provided HDL design.
Thanks in advance.
Edit: The S_AXI of the Ethernet and ROE IP core is connected to the M_AXI_HPM0_FPD. The FPD interface is setup as 128 bits. Could that be the reason that the IP cores are not being read by the linux system as, might be, that FPD is not setup in psu_init() proc?
With regards,
Ankur
Edit Notes
Added additional Info regarding the interface connecting PS with ROE and ethernet IP cores.[edited by: FPGA@noob at 7:39 PM (GMT -5) on 27 Feb 2024]
