Category: Software
Product Number: kria
Software Version: 2023.1
I have custom board for the kria k26c som and the ad9364 chip. I used the fmcomms2 design as a reference for my HDL. I have a petalinux build for it that boots fine and I can transmit data. When it comes to the receive side I dont see anything, not even noise. I am using the iio oscilloscope application to capture RX data. I have tried messing around with all configurations, enable signals, using TDD mode or FDD mode, BIST, etc. But RX just wont work.
The following is my device tree.
/dts-v1/;
/ {
compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB", "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26", "xlnx,zynqmp";
#address-cells = <0x2>;
#size-cells = <0x2>;
model = "ZynqMP SM-K26 Rev1/B/A";
cpus {
#address-cells = <0x1>;
#size-cells = <0x0>;
cpu@0 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
operating-points-v2 = <0x1>;
reg = <0x0>;
cpu-idle-states = <0x2>;
next-level-cache = <0x3>;
clocks = <0x4 0xa>;
phandle = <0x6>;
};
cpu@1 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
reg = <0x1>;
operating-points-v2 = <0x1>;
cpu-idle-states = <0x2>;
next-level-cache = <0x3>;
phandle = <0x7>;
};
cpu@2 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
reg = <0x2>;
operating-points-v2 = <0x1>;
cpu-idle-states = <0x2>;
next-level-cache = <0x3>;
phandle = <0x8>;
};
cpu@3 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
reg = <0x3>;
operating-points-v2 = <0x1>;
cpu-idle-states = <0x2>;
next-level-cache = <0x3>;
phandle = <0x9>;
};
l2-cache {
compatible = "cache";
cache-level = <0x2>;
phandle = <0x3>;
};
idle-states {
entry-method = "psci";
cpu-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x40000000>;
local-timer-stop;
entry-latency-us = <0x12c>;
exit-latency-us = <0x258>;
min-residency-us = <0x2710>;
phandle = <0x2>;
};
};
};
opp-table-cpu {
compatible = "operating-points-v2";
opp-shared;
phandle = <0x1>;
opp00 {
opp-hz = <0x0 0x4f790c10>;
opp-microvolt = <0xf4240>;
clock-latency-ns = <0x7a120>;
};
opp01 {
opp-hz = <0x0 0x27bc8608>;
opp-microvolt = <0xf4240>;
clock-latency-ns = <0x7a120>;
};
opp02 {
opp-hz = <0x0 0x1a7daeb0>;
opp-microvolt = <0xf4240>;
clock-latency-ns = <0x7a120>;
};
opp03 {
opp-hz = <0x0 0x13de4304>;
opp-microvolt = <0xf4240>;
clock-latency-ns = <0x7a120>;
};
opp04 {
opp-hz = <0x0 0x4d7c6cf4>;
opp-microvolt = <0xf4240>;
clock-latency-ns = <0x7a120>;
};
};
zynqmp_ipi {
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-ipi-mailbox";
interrupt-parent = <0x5>;
interrupts = <0x0 0x23 0x4>;
xlnx,ipi-id = <0x0>;
#address-cells = <0x2>;
#size-cells = <0x2>;
ranges;
phandle = <0x26>;
mailbox@ff9905c0 {
u-boot,dm-pre-reloc;
reg = <0x0 0xff9905c0 0x0 0x20 0x0 0xff9905e0 0x0 0x20 0x0 0xff990e80 0x0 0x20 0x0 0xff990ea0 0x0 0x20>;
reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region";
#mbox-cells = <0x1>;
xlnx,ipi-id = <0x4>;
phandle = <0xa>;
};
};
dcc {
compatible = "arm,dcc";
status = "disabled";
u-boot,dm-pre-reloc;
phandle = <0x27>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupt-parent = <0x5>;
interrupts = <0x0 0x8f 0x4 0x0 0x90 0x4 0x0 0x91 0x4 0x0 0x92 0x4>;
interrupt-affinity = <0x6 0x7 0x8 0x9>;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
firmware {
zynqmp-firmware {
compatible = "xlnx,zynqmp-firmware";
u-boot,dm-pre-reloc;
method = "smc";
#power-domain-cells = <0x1>;
phandle = <0x11>;
zynqmp-power {
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-power";
interrupt-parent = <0x5>;
interrupts = <0x0 0x23 0x4>;
mboxes = <0xa 0x0 0xa 0x1>;
mbox-names = "tx", "rx";
phandle = <0x28>;
};
nvmem_firmware {
compatible = "xlnx,zynqmp-nvmem-fw";
#address-cells = <0x1>;
#size-cells = <0x1>;
soc_revision@0 {
reg = <0x0 0x4>;
phandle = <0x29>;
};
efuse_dna@c {
reg = <0xc 0xc>;
phandle = <0x2a>;
};
efuse_usr0@20 {
reg = <0x20 0x4>;
phandle = <0x2b>;
};
efuse_usr1@24 {
reg = <0x24 0x4>;
phandle = <0x2c>;
};
efuse_usr2@28 {
reg = <0x28 0x4>;
phandle = <0x2d>;
};
efuse_usr3@2c {
reg = <0x2c 0x4>;
phandle = <0x2e>;
};
efuse_usr4@30 {
reg = <0x30 0x4>;
phandle = <0x2f>;
};
efuse_usr5@34 {
reg = <0x34 0x4>;
phandle = <0x30>;
};
efuse_usr6@38 {
reg = <0x38 0x4>;
phandle = <0x31>;
};
efuse_usr7@3c {
reg = <0x3c 0x4>;
phandle = <0x32>;
};
efuse_miscusr@40 {
reg = <0x40 0x4>;
phandle = <0x33>;
};
efuse_chash@50 {
reg = <0x50 0x4>;
phandle = <0x34>;
};
efuse_pufmisc@54 {
reg = <0x54 0x4>;
phandle = <0x35>;
};
efuse_sec@58 {
reg = <0x58 0x4>;
phandle = <0x36>;
};
efuse_spkid@5c {
reg = <0x5c 0x4>;
phandle = <0x37>;
};
efuse_ppk0hash@a0 {
reg = <0xa0 0x30>;
phandle = <0x38>;
};
efuse_ppk1hash@d0 {
reg = <0xd0 0x30>;
phandle = <0x39>;
};
};
pcap {
compatible = "xlnx,zynqmp-pcap-fpga";
clock-names = "ref_clk";
clocks = <0x4 0x29>;
phandle = <0x10>;
};
reset-controller {
compatible = "xlnx,zynqmp-reset";
#reset-cells = <0x1>;
phandle = <0x13>;
};
pinctrl {
compatible = "xlnx,zynqmp-pinctrl";
status = "okay";
phandle = <0x3a>;
sdhci0-default {
phandle = <0x18>;
conf {
groups = "sdio0_0_grp";
slew-rate = <0x1>;
power-source = <0x1>;
bias-disable;
};
mux {
groups = "sdio0_0_grp";
function = "sdio0";
};
};
};
gpio {
compatible = "xlnx,zynqmp-gpio-modepin";
gpio-controller;
#gpio-cells = <0x2>;
label = "modepin";
phandle = <0x1a>;
};
clock-controller {
u-boot,dm-pre-reloc;
#clock-cells = <0x1>;
compatible = "xlnx,zynqmp-clk";
clocks = <0xb 0xc 0xd 0xe 0xf>;
clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk";
phandle = <0x4>;
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <0x5>;
interrupts = <0x1 0xd 0xf08 0x1 0xe 0xf08 0x1 0xb 0xf08 0x1 0xa 0xf08>;
};
edac {
compatible = "arm,cortex-a53-edac";
};
fpga-full {
compatible = "fpga-region";
fpga-mgr = <0x10>;
#address-cells = <0x2>;
#size-cells = <0x2>;
ranges;
phandle = <0x3b>;
};
axi {
compatible = "simple-bus";
u-boot,dm-pre-reloc;
#address-cells = <0x2>;
#size-cells = <0x2>;
ranges;
phandle = <0x3c>;
can@ff060000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clock-names = "can_clk", "pclk";
reg = <0x0 0xff060000 0x0 0x1000>;
interrupts = <0x0 0x17 0x4>;
interrupt-parent = <0x5>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
power-domains = <0x11 0x2f>;
clocks = <0x4 0x3f 0x4 0x1f>;
phandle = <0x3d>;
};
can@ff070000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clock-names = "can_clk", "pclk";
reg = <0x0 0xff070000 0x0 0x1000>;
interrupts = <0x0 0x18 0x4>;
interrupt-parent = <0x5>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
power-domains = <0x11 0x30>;
clocks = <0x4 0x40 0x4 0x1f>;
phandle = <0x3e>;
};
cci@fd6e0000 {
compatible = "arm,cci-400";
status = "okay";
reg = <0x0 0xfd6e0000 0x0 0x9000>;
ranges = <0x0 0x0 0xfd6e0000 0x10000>;
#address-cells = <0x1>;
#size-cells = <0x1>;
phandle = <0x3f>;
pmu@9000 {
compatible = "arm,cci-400-pmu,r1";
reg = <0x9000 0x5000>;
interrupt-parent = <0x5>;
interrupts = <0x0 0x7b 0x4 0x0 0x7b 0x4 0x0 0x7b 0x4 0x0 0x7b 0x4 0x0 0x7b 0x4>;
};
};
dma-controller@fd500000 {
status = "okay";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd500000 0x0 0x1000>;
interrupt-parent = <0x5>;
interrupts = <0x0 0x7c 0x4>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <0x1>;
xlnx,bus-width = <0x80>;
iommus = <0x12 0x14e8>;
power-domains = <0x11 0x2a>;
clocks = <0x4 0x13 0x4 0x1f>;
phandle = <0x40>;
};
dma-controller@fd510000 {
status = "okay";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd510000 0x0 0x1000>;
interrupt-parent = <0x5>;
interrupts = <0x0 0x7d 0x4>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <0x1>;
xlnx,bus-width = <0x80>;
iommus = <0x12 0x14e9>;
power-domains = <0x11 0x2a>;
clocks = <0x4 0x13 0x4 0x1f>;
phandle = <0x41>;
};
dma-controller@fd520000 {
status = "okay";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd520000 0x0 0x1000>;
interrupt-parent = <0x5>;
interrupts = <0x0 0x7e 0x4>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <0x1>;
xlnx,bus-width = <0x80>;
iommus = <0x12 0x14ea>;
power-domains = <0x11 0x2a>;
clocks = <0x4 0x13 0x4 0x1f>;
phandle = <0x42>;
};
dma-controller@fd530000 {
status = "okay";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd530000 0x0 0x1000>;
interrupt-parent = <0x5>;
interrupts = <0x0 0x7f 0x4>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <0x1>;
xlnx,bus-width = <0x80>;
iommus = <0x12 0x14eb>;
power-domains = <0x11 0x2a>;
clocks = <0x4 0x13 0x4 0x1f>;
phandle = <0x43>;
};
dma-controller@fd540000 {
status = "okay";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd540000 0x0 0x1000>;
interrupt-parent = <0x5>;
interrupts = <0x0 0x80 0x4>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <0x1>;
xlnx,bus-width = <0x80>;
iommus = <0x12 0x14ec>;
power-domains = <0x11 0x2a>;
clocks = <0x4 0x13 0x4 0x1f>;
phandle = <0x44>;
};
dma-controller@fd550000 {
status = "okay";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd550000 0x0 0x1000>;
interrupt-parent = <0x5>;
interrupts = <0x0 0x81 0x4>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <0x1>;
xlnx,bus-width = <0x80>;
iommus = <0x12 0x14ed>;
power-domains = <0x11 0x2a>;
clocks = <0x4 0x13 0x4 0x1f>;
phandle = <0x45>;
};
dma-controller@fd560000 {
status = "okay";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd560000 0x0 0x1000>;
interrupt-parent = <0x5>;
interrupts = <0x0 0x82 0x4>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <0x1>;
xlnx,bus-width = <0x80>;
iommus = <0x12 0x14ee>;
power-domains = <0x11 0x2a>;
clocks = <0x4 0x13 0x4 0x1f>;
phandle = <0x46>;
};
dma-controller@fd570000 {
status = "okay";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd570000 0x0 0x1000>;
interrupt-parent = <0x5>;
interrupts = <0x0 0x83 0x4>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <0x1>;
xlnx,bus-width = <0x80>;
iommus = <0x12 0x14ef>;
power-domains = <0x11 0x2a>;
clocks = <0x4 0x13 0x4 0x1f>;
phandle = <0x47>;
};
interrupt-controller@f9010000 {
compatible = "arm,gic-400";
#interrupt-cells = <0x3>;
reg = <0x0 0xf9010000 0x0 0x10000 0x0 0xf9020000 0x0 0x20000 0x0 0xf9040000 0x0 0x20000 0x0 0xf9060000 0x0 0x20000>;
interrupt-controller;
interrupt-parent = <0x5>;
interrupts = <0x1 0x9 0xf04>;
num_cpus = <0x2>;
num_interrupts = <0x60>;
phandle = <0x5>;
};
gpu@fd4b0000 {
status = "okay";
compatible = "xlnx,zynqmp-mali", "arm,mali-400";
reg = <0x0 0xfd4b0000 0x0 0x10000>;
interrupt-parent = <0x5>;
interrupts = <0x0 0x84 0x4 0x0 0x84 0x4 0x0 0x84 0x4 0x0 0x84 0x4 0x0 0x84 0x4 0x0 0x84 0x4>;
interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1";
clock-names = "bus", "core";
power-domains = <0x11 0x3a>;
clocks = <0x4 0x18 0x4 0x19>;
xlnx,tz-nonsecure = <0x1>;
phandle = <0x48>;
};
dma-controller@ffa80000 {
status = "okay";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffa80000 0x0 0x1000>;
interrupt-parent = <0x5>;
interrupts = <0x0 0x4d 0x4>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <0x1>;
xlnx,bus-width = <0x40>;
power-domains = <0x11 0x2b>;
clocks = <0x4 0x44 0x4 0x1f>;
phandle = <0x49>;
};
dma-controller@ffa90000 {
status = "okay";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffa90000 0x0 0x1000>;
interrupt-parent = <0x5>;
interrupts = <0x0 0x4e 0x4>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <0x1>;
xlnx,bus-width = <0x40>;
power-domains = <0x11 0x2b>;
clocks = <0x4 0x44 0x4 0x1f>;
phandle = <0x4a>;
};
dma-controller@ffaa0000 {
status = "okay";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffaa0000 0x0 0x1000>;
interrupt-parent = <0x5>;
interrupts = <0x0 0x4f 0x4>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <0x1>;
xlnx,bus-width = <0x40>;
power-domains = <0x11 0x2b>;
clocks = <0x4 0x44 0x4 0x1f>;
phandle = <0x4b>;
};
dma-controller@ffab0000 {
status = "okay";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffab0000 0x0 0x1000>;
interrupt-parent = <0x5>;
interrupts = <0x0 0x50 0x4>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <0x1>;
xlnx,bus-width = <0x40>;
power-domains = <0x11 0x2b>;
clocks = <0x4 0x44 0x4 0x1f>;
phandle = <0x4c>;
};
dma-controller@ffac0000 {
status = "okay";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffac0000 0x0 0x1000>;
interrupt-parent = <0x5>;
interrupts = <0x0 0x51 0x4>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <0x1>;
xlnx,bus-width = <0x40>;
power-domains = <0x11 0x2b>;
clocks = <0x4 0x44 0x4 0x1f>;
phandle = <0x4d>;
};
dma-controller@ffad0000 {
status = "okay";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffad0000 0x0 0x1000>;
interrupt-parent = <0x5>;
interrupts = <0x0 0x52 0x4>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <0x1>;
xlnx,bus-width = <0x40>;
power-domains = <0x11 0x2b>;
clocks = <0x4 0x44 0x4 0x1f>;
phandle = <0x4e>;
};
dma-controller@ffae0000 {
status = "okay";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffae0000 0x0 0x1000>;
interrupt-parent = <0x5>;
interrupts = <0x0 0x53 0x4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <0x40>;
power-domains = <0x11 0x2b>;
clocks = <0x4 0x44 0x4 0x1f>;
phandle = <0x4f>;
};
dma-controller@ffaf0000 {
status = "okay";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffaf0000 0x0 0x1000>;
interrupt-parent = <0x5>;
interrupts = <0x0 0x54 0x4>;
clock-names = "clk_main", "clk_apb";
#dma-cells = <0x1>;
xlnx,bus-width = <0x40>;
power-domains = <0x11 0x2b>;
clocks = <0x4 0x44 0x4 0x1f>;
phandle = <0x50>;
};
memory-controller@fd070000 {
compatible = "xlnx,zynqmp-ddrc-2.40a";
reg = <0x0 0xfd070000 0x0 0x30000>;
interrupt-parent = <0x5>;
interrupts = <0x0 0x70 0x4>;
phandle = <0x51>;
};
nand-controller@ff100000 {
compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10";
status = "disabled";
reg = <0x0 0xff100000 0x0 0x1000>;
clock-names = "controller", "bus";
interrupt-parent = <0x5>;
interrupts = <0x0 0xe 0x4>;
#address-cells = <0x1>;
#size-cells = <0x0>;
iommus = <0x12 0x872>;
power-domains = <0x11 0x2c>;
clocks = <0x4 0x3c 0x4 0x1f>;
phandle = <0x52>;
};
ethernet@ff0b0000 {
compatible = "xlnx,zynqmp-gem", "cdns,gem";
status = "disabled";
interrupt-parent = <0x5>;
interrupts = <0x0 0x39 0x4 0x0 0x39 0x4>;
reg = <0x0 0xff0b0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
iommus = <0x12 0x874>;
power-domains = <0x11 0x1d>;
resets = <0x13 0x1d>;
reset-names = "gem0_rst";
clocks = <0x4 0x1f 0x4 0x68 0x4 0x2d 0x4 0x31 0x4 0x2c>;
phandle = <0x53>;
};
ethernet@ff0c0000 {
compatible = "xlnx,zynqmp-gem", "cdns,gem";
status = "disabled";
interrupt-parent = <0x5>;
interrupts = <0x0 0x3b 0x4 0x0 0x3b 0x4>;
reg = <0x0 0xff0c0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
iommus = <0x12 0x875>;
power-domains = <0x11 0x1e>;
resets = <0x13 0x1e>;
reset-names = "gem1_rst";
clocks = <0x4 0x1f 0x4 0x69 0x4 0x2e 0x4 0x32 0x4 0x2c>;
phandle = <0x54>;
};
ethernet@ff0d0000 {
compatible = "xlnx,zynqmp-gem", "cdns,gem";
status = "disabled";
interrupt-parent = <0x5>;
interrupts = <0x0 0x3d 0x4 0x0 0x3d 0x4>;
reg = <0x0 0xff0d0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
iommus = <0x12 0x876>;
power-domains = <0x11 0x1f>;
resets = <0x13 0x1f>;
reset-names = "gem2_rst";
clocks = <0x4 0x1f 0x4 0x6a 0x4 0x2f 0x4 0x33 0x4 0x2c>;
phandle = <0x55>;
};
ethernet@ff0e0000 {
compatible = "xlnx,zynqmp-gem", "cdns,gem";
status = "okay";
interrupt-parent = <0x5>;
interrupts = <0x0 0x3f 0x4 0x0 0x3f 0x4>;
reg = <0x0 0xff0e0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
iommus = <0x12 0x877>;
power-domains = <0x11 0x20>;
resets = <0x13 0x20>;
reset-names = "gem3_rst";
clocks = <0x4 0x1f 0x4 0x6b 0x4 0x30 0x4 0x34 0x4 0x2c>;
phy-mode = "rgmii-id";
xlnx,ptp-enet-clock = <0x0>;
phy-handle = <0x14>;
phandle = <0x56>;
mdio {
#address-cells = <0x1>;
#size-cells = <0x0>;
ethernet-phy@1 {
#phy-cells = <0x1>;
compatible = "ethernet-phy-id2000.a231";
device_type = "ethernet-phy";
reg = <0x0>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk;
phandle = <0x14>;
};
};
};
gpio@ff0a0000 {
compatible = "xlnx,zynqmp-gpio-1.0";
status = "okay";
#gpio-cells = <0x2>;
gpio-controller;
interrupt-parent = <0x5>;
interrupts = <0x0 0x10 0x4>;
interrupt-controller;
#interrupt-cells = <0x2>;
reg = <0x0 0xff0a0000 0x0 0x1000>;
power-domains = <0x11 0x2e>;
clocks = <0x4 0x1f>;
gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", "I2C1_SDA", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "";
emio-gpio-width = <0x20>;
gpio-mask-high = <0x0>;
gpio-mask-low = <0x5600>;
phandle = <0x15>;
};
i2c@ff020000 {
compatible = "cdns,i2c-r1p14";
status = "disabled";
interrupt-parent = <0x5>;
interrupts = <0x0 0x11 0x4>;
reg = <0x0 0xff020000 0x0 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
power-domains = <0x11 0x25>;
clocks = <0x4 0x3d>;
phandle = <0x57>;
};
i2c@ff030000 {
compatible = "cdns,i2c-r1p14";
status = "okay";
interrupt-parent = <0x5>;
interrupts = <0x0 0x12 0x4>;
reg = <0x0 0xff030000 0x0 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
power-domains = <0x11 0x26>;
clocks = <0x4 0x3e>;
u-boot,dm-pre-reloc;
clock-frequency = <0x61a80>;
scl-gpios = <0x15 0x18 0x0>;
sda-gpios = <0x15 0x19 0x0>;
phandle = <0x58>;
eeprom@50 {
u-boot,dm-pre-reloc;
compatible = "st,24c64", "atmel,24c64";
reg = <0x50>;
phandle = <0x59>;
};
eeprom@51 {
u-boot,dm-pre-reloc;
compatible = "st,24c64", "atmel,24c64";
reg = <0x51>;
phandle = <0x5a>;
};
pmic@33 {
compatible = "dlg,da9131";
reg = <0x33>;
phandle = <0x5b>;
regulators {
buck1 {
regulator-name = "da9131_buck1";
regulator-boot-on;
regulator-always-on;
phandle = <0x5c>;
};
buck2 {
regulator-name = "da9131_buck2";
regulator-boot-on;
regulator-always-on;
phandle = <0x5d>;
};
};
};
pmic@32 {
compatible = "dlg,da9130";
reg = <0x32>;
phandle = <0x5e>;
regulators {
buck1 {
regulator-name = "da9130_buck1";
regulator-boot-on;
regulator-always-on;
phandle = <0x5f>;
};
};
};
};
memory-controller@ff960000 {
compatible = "xlnx,zynqmp-ocmc-1.0";
reg = <0x0 0xff960000 0x0 0x1000>;
interrupt-parent = <0x5>;
interrupts = <0x0 0xa 0x4>;
phandle = <0x60>;
};
perf-monitor@ffa00000 {
compatible = "xlnx,axi-perf-monitor";
reg = <0x0 0xffa00000 0x0 0x10000>;
interrupts = <0x0 0x19 0x4>;
interrupt-parent = <0x5>;
xlnx,enable-profile = <0x0>;
xlnx,enable-trace = <0x0>;
xlnx,num-monitor-slots = <0x1>;
xlnx,enable-event-count = <0x1>;
xlnx,enable-event-log = <0x1>;
xlnx,have-sampled-metric-cnt = <0x1>;
xlnx,num-of-counters = <0x8>;
xlnx,metric-count-width = <0x20>;
xlnx,metrics-sample-count-width = <0x20>;
xlnx,global-count-width = <0x20>;
xlnx,metric-count-scale = <0x1>;
clocks = <0x4 0x1f>;
phandle = <0x61>;
};
perf-monitor@fd0b0000 {
compatible = "xlnx,axi-perf-monitor";
reg = <0x0 0xfd0b0000 0x0 0x10000>;
interrupts = <0x0 0x7b 0x4>;
interrupt-parent = <0x5>;
xlnx,enable-profile = <0x0>;
xlnx,enable-trace = <0x0>;
xlnx,num-monitor-slots = <0x6>;
xlnx,enable-event-count = <0x1>;
xlnx,enable-event-log = <0x0>;
xlnx,have-sampled-metric-cnt = <0x1>;
xlnx,num-of-counters = <0xa>;
xlnx,metric-count-width = <0x20>;
xlnx,metrics-sample-count-width = <0x20>;
xlnx,global-count-width = <0x20>;
xlnx,metric-count-scale = <0x1>;
clocks = <0x4 0x1c>;
phandle = <0x62>;
};
perf-monitor@fd490000 {
compatible = "xlnx,axi-perf-monitor";
reg = <0x0 0xfd490000 0x0 0x10000>;
interrupts = <0x0 0x7b 0x4>;
interrupt-parent = <0x5>;
xlnx,enable-profile = <0x0>;
xlnx,enable-trace = <0x0>;
xlnx,num-monitor-slots = <0x1>;
xlnx,enable-event-count = <0x1>;
xlnx,enable-event-log = <0x0>;
xlnx,have-sampled-metric-cnt = <0x1>;
xlnx,num-of-counters = <0x8>;
xlnx,metric-count-width = <0x20>;
xlnx,metrics-sample-count-width = <0x20>;
xlnx,global-count-width = <0x20>;
xlnx,metric-count-scale = <0x1>;
clocks = <0x4 0x1c>;
phandle = <0x63>;
};
perf-monitor@ffa10000 {
compatible = "xlnx,axi-perf-monitor";
reg = <0x0 0xffa10000 0x0 0x10000>;
interrupts = <0x0 0x19 0x4>;
interrupt-parent = <0x5>;
xlnx,enable-profile = <0x0>;
xlnx,enable-trace = <0x0>;
xlnx,num-monitor-slots = <0x1>;
xlnx,enable-event-count = <0x1>;
xlnx,enable-event-log = <0x1>;
xlnx,have-sampled-metric-cnt = <0x1>;
xlnx,num-of-counters = <0x8>;
xlnx,metric-count-width = <0x20>;
xlnx,metrics-sample-count-width = <0x20>;
xlnx,global-count-width = <0x20>;
xlnx,metric-count-scale = <0x1>;
clocks = <0x4 0x1f>;
phandle = <0x64>;
};
pcie@fd0e0000 {
compatible = "xlnx,nwl-pcie-2.11";
status = "disabled";
#address-cells = <0x3>;
#size-cells = <0x2>;
#interrupt-cells = <0x1>;
msi-controller;
device_type = "pci";
interrupt-parent = <0x5>;
interrupts = <0x0 0x76 0x4 0x0 0x75 0x4 0x0 0x74 0x4 0x0 0x73 0x4 0x0 0x72 0x4>;
interrupt-names = "misc", "dummy", "intx", "msi1", "msi0";
msi-parent = <0x16>;
reg = <0x0 0xfd0e0000 0x0 0x1000 0x0 0xfd480000 0x0 0x1000 0x80 0x0 0x0 0x1000000>;
reg-names = "breg", "pcireg", "cfg";
ranges = <0x2000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000 0x43000000 0x6 0x0 0x6 0x0 0x2 0x0>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
bus-range = <0x0 0xff>;
interrupt-map = <0x0 0x0 0x0 0x1 0x17 0x1 0x0 0x0 0x0 0x2 0x17 0x2 0x0 0x0 0x0 0x3 0x17 0x3 0x0 0x0 0x0 0x4 0x17 0x4>;
iommus = <0x12 0x4d0>;
power-domains = <0x11 0x3b>;
clocks = <0x4 0x17>;
phandle = <0x16>;
legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0x0>;
#interrupt-cells = <0x1>;
phandle = <0x17>;
};
};
spi@ff0f0000 {
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-qspi-1.0";
status = "okay";
clock-names = "ref_clk", "pclk";
interrupts = <0x0 0xf 0x4>;
interrupt-parent = <0x5>;
num-cs = <0x1>;
reg = <0x0 0xff0f0000 0x0 0x1000 0x0 0xc0000000 0x0 0x8000000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
iommus = <0x12 0x873>;
power-domains = <0x11 0x2d>;
clocks = <0x4 0x35 0x4 0x1f>;
is-dual = <0x0>;
spi-rx-bus-width = <0x4>;
spi-tx-bus-width = <0x4>;
phandle = <0x65>;
flash@0 {
compatible = "mt25qu512a", "jedec,spi-nor";
#address-cells = <0x1>;
#size-cells = <0x1>;
reg = <0x0>;
spi-tx-bus-width = <0x4>;
spi-rx-bus-width = <0x4>;
spi-max-frequency = <0x2625a00>;
phandle = <0x66>;
partitions {
compatible = "fixed-partitions";
#address-cells = <0x1>;
#size-cells = <0x1>;
partition@0 {
label = "Image Selector";
reg = <0x0 0x80000>;
read-only;
lock;
};
partition@80000 {
label = "Image Selector Golden";
reg = <0x80000 0x80000>;
read-only;
lock;
};
partition@100000 {
label = "Persistent Register";
reg = <0x100000 0x20000>;
};
partition@120000 {
label = "Persistent Register Backup";
reg = <0x120000 0x20000>;
};
partition@140000 {
label = "Open_1";
reg = <0x140000 0xc0000>;
};
partition@200000 {
label = "Image A (FSBL, PMU, ATF, U-Boot)";
reg = <0x200000 0xd00000>;
};
partition@f00000 {
label = "ImgSel Image A Catch";
reg = <0xf00000 0x80000>;
read-only;
lock;
};
partition@f80000 {
label = "Image B (FSBL, PMU, ATF, U-Boot)";
reg = <0xf80000 0xd00000>;
};
partition@1c80000 {
label = "ImgSel Image B Catch";
reg = <0x1c80000 0x80000>;
read-only;
lock;
};
partition@1d00000 {
label = "Open_2";
reg = <0x1d00000 0x100000>;
};
partition@1e00000 {
label = "Recovery Image";
reg = <0x1e00000 0x200000>;
read-only;
lock;
};
partition@2000000 {
label = "Recovery Image Backup";
reg = <0x2000000 0x200000>;
read-only;
lock;
};
partition@2200000 {
label = "U-Boot storage variables";
reg = <0x2200000 0x20000>;
};
partition@2220000 {
label = "U-Boot storage variables backup";
reg = <0x2220000 0x20000>;
};
partition@2240000 {
label = "SHA256";
reg = <0x2240000 0x40000>;
read-only;
lock;
};
partition@2280000 {
label = "Secure OS Storage";
reg = <0x2280000 0x20000>;
};
partition@22A0000 {
label = "User";
reg = <0x22a0000 0x1db0000>;
};
};
};
};
phy@fd400000 {
compatible = "xlnx,zynqmp-psgtr-v1.1";
status = "okay";
reg = <0x0 0xfd400000 0x0 0x40000 0x0 0xfd3d0000 0x0 0x1000>;
reg-names = "serdes", "siou";
#phy-cells = <0x4>;
phandle = <0x67>;
};
rtc@ffa60000 {
compatible = "xlnx,zynqmp-rtc";
status = "okay";
reg = <0x0 0xffa60000 0x0 0x100>;
interrupt-parent = <0x5>;
interrupts = <0x0 0x1a 0x4 0x0 0x1b 0x4>;
interrupt-names = "alarm", "sec";
calibration = <0x7fff>;
phandle = <0x68>;
};
ahci@fd0c0000 {
compatible = "ceva,ahci-1v84";
status = "disabled";
reg = <0x0 0xfd0c0000 0x0 0x2000>;
interrupt-parent = <0x5>;
interrupts = <0x0 0x85 0x4>;
power-domains = <0x11 0x1c>;
resets = <0x13 0x10>;
clocks = <0x4 0x16>;
phandle = <0x69>;
};
mmc@ff160000 {
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "okay";
interrupt-parent = <0x5>;
interrupts = <0x0 0x30 0x4>;
reg = <0x0 0xff160000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
iommus = <0x12 0x870>;
power-domains = <0x11 0x27>;
#clock-cells = <0x1>;
clock-output-names = "clk_out_sd0", "clk_in_sd0";
resets = <0x13 0x26>;
clocks = <0x4 0x36 0x4 0x1f>;
assigned-clocks = <0x4 0x36>;
pinctrl-names = "default";
pinctrl-0 = <0x18>;
non-removable;
disable-wp;
bus-width = <0x8>;
xlnx,mio-bank = <0x0>;
assigned-clock-rates = <0xb2cfe8b>;
clock-frequency = <0xb2cfe8b>;
phandle = <0x6a>;
};
mmc@ff170000 {
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
interrupt-parent = <0x5>;
interrupts = <0x0 0x31 0x4>;
reg = <0x0 0xff170000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
iommus = <0x12 0x871>;
power-domains = <0x11 0x28>;
#clock-cells = <0x1>;
clock-output-names = "clk_out_sd1", "clk_in_sd1";
resets = <0x13 0x27>;
clocks = <0x4 0x37 0x4 0x1f>;
assigned-clocks = <0x4 0x37>;
phandle = <0x6b>;
};
smmu@fd800000 {
compatible = "arm,mmu-500";
reg = <0x0 0xfd800000 0x0 0x20000>;
#iommu-cells = <0x1>;
status = "disabled";
#global-interrupts = <0x1>;
interrupt-parent = <0x5>;
interrupts = <0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4>;
phandle = <0x12>;
};
spi@ff040000 {
compatible = "cdns,spi-r1p6";
status = "okay";
interrupt-parent = <0x5>;
interrupts = <0x0 0x13 0x4>;
reg = <0x0 0xff040000 0x0 0x1000>;
clock-names = "ref_clk", "pclk";
#address-cells = <0x1>;
#size-cells = <0x0>;
power-domains = <0x11 0x23>;
clocks = <0x4 0x3a 0x4 0x1f>;
is-decoded-cs = <0x0>;
num-cs = <0x3>;
phandle = <0x6c>;
ad9361-phy@0 {
compatible = "adi,ad9364";
reg = <0x0>;
spi-cpha;
spi-max-frequency = <0x989680>;
clocks = <0x19 0x0>;
clock-names = "ad9364_ext_refclk";
clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
#clock-cells = <0x1>;
adi,digital-interface-tune-skip-mode = <0x2>;
adi,pp-tx-swap-enable;
adi,pp-rx-swap-enable;
adi,rx-frame-pulse-mode-enable;
adi,lvds-mode-enable;
adi,lvds-bias-mV = <0x96>;
adi,lvds-rx-onchip-termination-enable;
adi,rx-data-delay = <0x4>;
adi,tx-fb-clock-delay = <0x7>;
adi,xo-disable-use-ext-refclk-enable;
adi,frequency-division-duplex-mode-enable;
adi,rx-rf-port-input-select = <0x0>;
adi,tx-rf-port-input-select = <0x0>;
adi,tx-attenuation-mdB = <0x2710>;
adi,tx-lo-powerdown-managed-enable;
adi,rf-rx-bandwidth-hz = <0x112a880>;
adi,rf-tx-bandwidth-hz = <0x112a880>;
adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;
adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;
adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
adi,gc-rx1-mode = <0x2>;
adi,gc-rx2-mode = <0x2>;
adi,gc-adc-ovr-sample-size = <0x4>;
adi,gc-adc-small-overload-thresh = <0x2f>;
adi,gc-adc-large-overload-thresh = <0x3a>;
adi,gc-lmt-overload-high-thresh = <0x320>;
adi,gc-lmt-overload-low-thresh = <0x2c0>;
adi,gc-dec-pow-measurement-duration = <0x2000>;
adi,gc-low-power-thresh = <0x18>;
adi,mgc-inc-gain-step = <0x2>;
adi,mgc-dec-gain-step = <0x2>;
adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;
adi,agc-attack-delay-extra-margin-us = <0x1>;
adi,agc-outer-thresh-high = <0x5>;
adi,agc-outer-thresh-high-dec-steps = <0x2>;
adi,agc-inner-thresh-high = <0xa>;
adi,agc-inner-thresh-high-dec-steps = <0x1>;
adi,agc-inner-thresh-low = <0xc>;
adi,agc-inner-thresh-low-inc-steps = <0x1>;
adi,agc-outer-thresh-low = <0x12>;
adi,agc-outer-thresh-low-inc-steps = <0x2>;
adi,agc-adc-small-overload-exceed-counter = <0xa>;
adi,agc-adc-large-overload-exceed-counter = <0xa>;
adi,agc-adc-large-overload-inc-steps = <0x2>;
adi,agc-lmt-overload-large-exceed-counter = <0xa>;
adi,agc-lmt-overload-small-exceed-counter = <0xa>;
adi,agc-lmt-overload-large-inc-steps = <0x2>;
adi,agc-gain-update-interval-us = <0x3e8>;
adi,fagc-dec-pow-measurement-duration = <0x40>;
adi,fagc-lp-thresh-increment-steps = <0x1>;
adi,fagc-lp-thresh-increment-time = <0x5>;
adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;
adi,fagc-final-overrange-count = <0x3>;
adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;
adi,fagc-lmt-final-settling-steps = <0x1>;
adi,fagc-lock-level = <0xa>;
adi,fagc-lock-level-gain-increase-upper-limit = <0x5>;
adi,fagc-lock-level-lmt-gain-increase-enable;
adi,fagc-lpf-final-settling-steps = <0x1>;
adi,fagc-optimized-gain-offset = <0x5>;
adi,fagc-power-measurement-duration-in-state5 = <0x40>;
adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;
adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable;
adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;
adi,fagc-rst-gla-large-adc-overload-enable;
adi,fagc-rst-gla-large-lmt-overload-enable;
adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;
adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable;
adi,fagc-state-wait-time-ns = <0x104>;
adi,fagc-use-last-lock-level-for-set-gain-enable;
adi,rssi-restart-mode = <0x3>;
adi,rssi-delay = <0x1>;
adi,rssi-wait = <0x1>;
adi,rssi-duration = <0x3e8>;
adi,ctrl-outs-index = <0x0>;
adi,ctrl-outs-enable-mask = <0xff>;
adi,temp-sense-measurement-interval-ms = <0x3e8>;
adi,temp-sense-offset-signed = <0xce>;
adi,temp-sense-periodic-measurement-enable;
adi,aux-dac-manual-mode-enable;
adi,aux-dac1-default-value-mV = <0x0>;
adi,aux-dac1-rx-delay-us = <0x0>;
adi,aux-dac1-tx-delay-us = <0x0>;
adi,aux-dac2-default-value-mV = <0x0>;
adi,aux-dac2-rx-delay-us = <0x0>;
adi,aux-dac2-tx-delay-us = <0x0>;
en_agc-gpios = <0x15 0x7a 0x0>;
sync-gpios = <0x15 0x7b 0x0>;
reset-gpios = <0x15 0x7c 0x0>;
enable-gpios = <0x15 0x7d 0x0>;
txnrx-gpios = <0x15 0x7e 0x0>;
phandle = <0x24>;
};
};
spi@ff050000 {
compatible = "cdns,spi-r1p6";
status = "disabled";
interrupt-parent = <0x5>;
interrupts = <0x0 0x14 0x4>;
reg = <0x0 0xff050000 0x0 0x1000>;
clock-names = "ref_clk", "pclk";
#address-cells = <0x1>;
#size-cells = <0x0>;
power-domains = <0x11 0x24>;
clocks = <0x4 0x3b 0x4 0x1f>;
label = "TPM";
num-cs = <0x1>;
phandle = <0x6d>;
tpm@0 {
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
reg = <0x0>;
spi-max-frequency = <0x11a49a0>;
};
};
timer@ff110000 {
compatible = "cdns,ttc";
status = "okay";
interrupt-parent = <0x5>;
interrupts = <0x0 0x24 0x4 0x0 0x25 0x4 0x0 0x26 0x4>;
reg = <0x0 0xff110000 0x0 0x1000>;
timer-width = <0x20>;
power-domains = <0x11 0x18>;
clocks = <0x4 0x1f>;
#pwm-cells = <0x3>;
phandle = <0x22>;
};
timer@ff120000 {
compatible = "cdns,ttc";
status = "okay";
interrupt-parent = <0x5>;
interrupts = <0x0 0x27 0x4 0x0 0x28 0x4 0x0 0x29 0x4>;
reg = <0x0 0xff120000 0x0 0x1000>;
timer-width = <0x20>;
power-domains = <0x11 0x19>;
clocks = <0x4 0x1f>;
phandle = <0x6e>;
};
timer@ff130000 {
compatible = "cdns,ttc";
status = "okay";
interrupt-parent = <0x5>;
interrupts = <0x0 0x2a 0x4 0x0 0x2b 0x4 0x0 0x2c 0x4>;
reg = <0x0 0xff130000 0x0 0x1000>;
timer-width = <0x20>;
power-domains = <0x11 0x1a>;
clocks = <0x4 0x1f>;
phandle = <0x6f>;
};
timer@ff140000 {
compatible = "cdns,ttc";
status = "okay";
interrupt-parent = <0x5>;
interrupts = <0x0 0x2d 0x4 0x0 0x2e 0x4 0x0 0x2f 0x4>;
reg = <0x0 0xff140000 0x0 0x1000>;
timer-width = <0x20>;
power-domains = <0x11 0x1b>;
clocks = <0x4 0x1f>;
phandle = <0x70>;
};
serial@ff000000 {
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
status = "disabled";
interrupt-parent = <0x5>;
interrupts = <0x0 0x15 0x4>;
reg = <0x0 0xff000000 0x0 0x1000>;
clock-names = "uart_clk", "pclk";
power-domains = <0x11 0x21>;
clocks = <0x4 0x38 0x4 0x1f>;
phandle = <0x71>;
};
serial@ff010000 {
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
status = "okay";
interrupt-parent = <0x5>;
interrupts = <0x0 0x16 0x4>;
reg = <0x0 0xff010000 0x0 0x1000>;
clock-names = "uart_clk", "pclk";
power-domains = <0x11 0x22>;
clocks = <0x4 0x39 0x4 0x1f>;
cts-override;
device_type = "serial";
port-number = <0x0>;
phandle = <0x72>;
};
usb@ff9d0000 {
#address-cells = <0x2>;
#size-cells = <0x2>;
status = "disabled";
compatible = "xlnx,zynqmp-dwc3";
reg = <0x0 0xff9d0000 0x0 0x100>;
clock-names = "bus_clk", "ref_clk";
power-domains = <0x11 0x16>;
resets = <0x13 0x3b 0x13 0x3d 0x13 0x3f>;
reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
reset-gpios = <0x1a 0x1 0x1>;
ranges;
clocks = <0x4 0x20 0x4 0x22>;
assigned-clocks = <0x4 0x20 0x4 0x22>;
phandle = <0x73>;
usb@fe200000 {
compatible = "snps,dwc3";
status = "okay";
reg = <0x0 0xfe200000 0x0 0x40000>;
interrupt-parent = <0x5>;
interrupt-names = "dwc_usb3", "otg", "hiber";
interrupts = <0x0 0x41 0x4 0x0 0x45 0x4 0x0 0x4b 0x4>;
iommus = <0x12 0x860>;
snps,quirk-frame-length-adjustment = <0x20>;
clock-names = "ref";
snps,enable_guctl1_resume_quirk;
snps,enable_guctl1_ipd_quirk;
snps,resume-hs-terminations;
clocks = <0x4 0x22>;
dr_mode = "otg";
phandle = <0x74>;
};
};
usb@ff9e0000 {
#address-cells = <0x2>;
#size-cells = <0x2>;
status = "disabled";
compatible = "xlnx,zynqmp-dwc3";
reg = <0x0 0xff9e0000 0x0 0x100>;
clock-names = "bus_clk", "ref_clk";
power-domains = <0x11 0x17>;
resets = <0x13 0x3c 0x13 0x3e 0x13 0x40>;
reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
ranges;
clocks = <0x4 0x21 0x4 0x22>;
assigned-clocks = <0x4 0x21 0x4 0x22>;
phandle = <0x75>;
usb@fe300000 {
compatible = "snps,dwc3";
status = "disabled";
reg = <0x0 0xfe300000 0x0 0x40000>;
interrupt-parent = <0x5>;
interrupt-names = "dwc_usb3", "otg", "hiber";
interrupts = <0x0 0x46 0x4 0x0 0x4a 0x4 0x0 0x4c 0x4>;
iommus = <0x12 0x861>;
snps,quirk-frame-length-adjustment = <0x20>;
clock-names = "ref";
snps,enable_guctl1_resume_quirk;
snps,enable_guctl1_ipd_quirk;
snps,resume-hs-terminations;
clocks = <0x4 0x22>;
phandle = <0x76>;
};
};
watchdog@fd4d0000 {
compatible = "cdns,wdt-r1p2";
status = "okay";
interrupt-parent = <0x5>;
interrupts = <0x0 0x71 0x1>;
reg = <0x0 0xfd4d0000 0x0 0x1000>;
timeout-sec = <0x3c>;
reset-on-timeout;
clocks = <0x4 0x4b>;
phandle = <0x77>;
};
watchdog@ff150000 {
compatible = "cdns,wdt-r1p2";
status = "okay";
interrupt-parent = <0x5>;
interrupts = <0x0 0x34 0x1>;
reg = <0x0 0xff150000 0x0 0x1000>;
timeout-sec = <0xa>;
clocks = <0x4 0x70>;
phandle = <0x78>;
};
ams@ffa50000 {
compatible = "xlnx,zynqmp-ams";
status = "okay";
interrupt-parent = <0x5>;
interrupts = <0x0 0x38 0x4>;
interrupt-names = "ams-irq";
reg = <0x0 0xffa50000 0x0 0x800>;
reg-names = "ams-base";
#address-cells = <0x1>;
#size-cells = <0x1>;
#io-channel-cells = <0x1>;
ranges = <0x0 0x0 0xffa50800 0x800>;
clocks = <0x4 0x46>;
phandle = <0x21>;
ams_ps@0 {
compatible = "xlnx,zynqmp-ams-ps";
status = "okay";
reg = <0x0 0x400>;
phandle = <0x79>;
};
ams_pl@400 {
compatible = "xlnx,zynqmp-ams-pl";
status = "okay";
reg = <0x400 0x400>;
phandle = <0x7a>;
};
};
dma-controller@fd4c0000 {
compatible = "xlnx,zynqmp-dpdma";
status = "disabled";
reg = <0x0 0xfd4c0000 0x0 0x1000>;
interrupts = <0x0 0x7a 0x4>;
interrupt-parent = <0x5>;
clock-names = "axi_clk";
power-domains = <0x11 0x29>;
dma-channels = <0x6>;
iommus = <0x12 0xce4>;
#dma-cells = <0x1>;
clocks = <0x4 0x14>;
assigned-clocks = <0x4 0x14>;
phandle = <0x1c>;
};
dp_aud@fd4ac000 {
compatible = "xlnx,zynqmp-dpaud-setting", "syscon";
reg = <0x0 0xfd4ac000 0x0 0x1000>;
phandle = <0x1b>;
};
display@fd4a0000 {
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-dpsub-1.7";
status = "disabled";
reg = <0x0 0xfd4a0000 0x0 0x1000 0x0 0xfd4aa000 0x0 0x1000 0x0 0xfd4ab000 0x0 0x1000>;
reg-names = "dp", "blend", "av_buf";
xlnx,dpaud-reg = <0x1b>;
interrupts = <0x0 0x77 0x4>;
interrupt-parent = <0x5>;
iommus = <0x12 0xce3>;
clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in";
power-domains = <0x11 0x29>;
resets = <0x13 0x3>;
dma-names = "vid0", "vid1", "vid2", "gfx0";
dmas = <0x1c 0x0 0x1c 0x1 0x1c 0x2 0x1c 0x3>;
clocks = <0x1d 0x4 0x11 0x4 0x10>;
assigned-clocks = <0x4 0x12 0x4 0x11 0x4 0x10>;
phandle = <0x7b>;
i2c-bus {
};
zynqmp_dp_snd_codec0 {
compatible = "xlnx,dp-snd-codec";
clock-names = "aud_clk";
clocks = <0x4 0x11>;
phandle = <0x20>;
};
zynqmp_dp_snd_pcm0 {
compatible = "xlnx,dp-snd-pcm0";
dmas = <0x1c 0x4>;
dma-names = "tx";
phandle = <0x1e>;
};
zynqmp_dp_snd_pcm1 {
compatible = "xlnx,dp-snd-pcm1";
dmas = <0x1c 0x5>;
dma-names = "tx";
phandle = <0x1f>;
};
zynqmp_dp_snd_card {
compatible = "xlnx,dp-snd-card";
xlnx,dp-snd-pcm = <0x1e 0x1f>;
xlnx,dp-snd-codec = <0x20>;
phandle = <0x7c>;
};
};
};
fclk0 {
status = "okay";
compatible = "xlnx,fclk";
clocks = <0x4 0x47>;
phandle = <0x7d>;
};
fclk1 {
status = "okay";
compatible = "xlnx,fclk";
clocks = <0x4 0x48>;
phandle = <0x7e>;
};
fclk2 {
status = "okay";
compatible = "xlnx,fclk";
clocks = <0x4 0x49>;
phandle = <0x7f>;
};
fclk3 {
status = "okay";
compatible = "xlnx,fclk";
clocks = <0x4 0x4a>;
phandle = <0x80>;
};
pss_ref_clk {
u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0x1fca055>;
phandle = <0xb>;
};
video_clk {
u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0x19bfcc0>;
phandle = <0xc>;
};
pss_alt_ref_clk {
u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0x0>;
phandle = <0xd>;
};
gt_crx_ref_clk {
u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0x66ff300>;
phandle = <0xf>;
};
aux_ref_clk {
u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0x19bfcc0>;
phandle = <0xe>;
};
dp_aclk {
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0x5f5e100>;
clock-accuracy = <0x64>;
phandle = <0x1d>;
};
aliases {
gpio0 = "/axi/gpio@ff0a0000";
i2c0 = "/axi/i2c@ff020000";
i2c1 = "/axi/i2c@ff030000";
mmc0 = "/axi/mmc@ff160000";
mmc1 = "/axi/mmc@ff170000";
nvmem0 = "/axi/i2c@ff030000/eeprom@50";
nvmem1 = "/axi/i2c@ff030000/eeprom@51";
rtc0 = "/axi/rtc@ffa60000";
serial0 = "/axi/serial@ff000000";
serial1 = "/axi/serial@ff010000";
serial2 = "/dcc";
spi0 = "/axi/spi@ff0f0000";
spi1 = "/axi/spi@ff040000";
spi2 = "/axi/spi@ff050000";
usb0 = "/axi/usb@ff9d0000";
usb1 = "/axi/usb@ff9e0000";
};
chosen {
bootargs = "earlycon console=ttyPS1,115200 clk_ignore_unused root=/dev/ram0 rw";
stdout-path = "serial1:115200n8";
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
key-fwuen {
label = "fwuen";
gpios = <0x15 0xc 0x1>;
linux,code = <0x100>;
wakeup-source;
autorepeat;
};
};
leds {
compatible = "gpio-leds";
ds35-led {
label = "heartbeat";
gpios = <0x15 0x7 0x0>;
linux,default-trigger = "heartbeat";
};
ds36-led {
label = "vbus_det";
gpios = <0x15 0x8 0x0>;
default-state = "on";
};
};
ams {
compatible = "iio-hwmon";
io-channels = <0x21 0x0 0x21 0x1 0x21 0x2 0x21 0x3 0x21 0x4 0x21 0x5 0x21 0x6 0x21 0x7 0x21 0x8 0x21 0x9 0x21 0xa 0x21 0xb 0x21 0xc 0x21 0xd 0x21 0xe 0x21 0xf 0x21 0x10 0x21 0x11 0x21 0x12 0x21 0x13 0x21 0x14 0x21 0x15 0x21 0x16 0x21 0x17 0x21 0x18 0x21 0x19 0x21 0x1a 0x21 0x1b 0x21 0x1c 0x21 0x1d>;
};
pwm-fan {
compatible = "pwm-fan";
pwms = <0x22 0x2 0x9c40 0x0>;
};
amba_pl@0 {
#address-cells = <0x2>;
#size-cells = <0x2>;
compatible = "simple-bus";
ranges;
phandle = <0x81>;
axi_quad_spi@a0000000 {
bits-per-word = <0x8>;
clock-names = "ext_spi_clk", "s_axi_aclk";
clocks = <0x4 0x47 0x4 0x47>;
compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a";
fifo-size = <0x10>;
interrupt-names = "ip2intc_irpt";
interrupt-parent = <0x5>;
interrupts = <0x0 0x59 0x1>;
num-cs = <0x3>;
reg = <0x0 0xa0000000 0x0 0x10000>;
xlnx,num-ss-bits = <0x3>;
xlnx,spi-mode = <0x0>;
phandle = <0x82>;
};
axi_quad_spi@a0010000 {
bits-per-word = <0x8>;
clock-names = "ext_spi_clk", "s_axi_aclk";
clocks = <0x4 0x47 0x4 0x47>;
compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a";
fifo-size = <0x10>;
interrupt-names = "ip2intc_irpt";
interrupt-parent = <0x5>;
interrupts = <0x0 0x5d 0x1>;
num-cs = <0x1>;
reg = <0x0 0xa0010000 0x0 0x10000>;
xlnx,num-ss-bits = <0x1>;
xlnx,spi-mode = <0x2>;
phandle = <0x83>;
};
axi_quad_spi@a0020000 {
bits-per-word = <0x8>;
clock-names = "ext_spi_clk", "s_axi_aclk";
clocks = <0x4 0x47 0x4 0x47>;
compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a";
fifo-size = <0x10>;
interrupt-names = "ip2intc_irpt";
interrupt-parent = <0x5>;
interrupts = <0x0 0x5c 0x1>;
num-cs = <0x1>;
reg = <0x0 0xa0020000 0x0 0x10000>;
xlnx,num-ss-bits = <0x1>;
xlnx,spi-mode = <0x2>;
phandle = <0x84>;
};
axi_quad_spi@a0030000 {
bits-per-word = <0x8>;
clock-names = "ext_spi_clk", "s_axi_aclk";
clocks = <0x4 0x47 0x4 0x47>;
compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a";
fifo-size = <0x10>;
interrupt-names = "ip2intc_irpt";
interrupt-parent = <0x5>;
interrupts = <0x0 0x5b 0x1>;
num-cs = <0x1>;
reg = <0x0 0xa0030000 0x0 0x10000>;
xlnx,num-ss-bits = <0x1>;
xlnx,spi-mode = <0x2>;
phandle = <0x85>;
};
axi_quad_spi@a0040000 {
bits-per-word = <0x8>;
clock-names = "ext_spi_clk", "s_axi_aclk";
clocks = <0x4 0x47 0x4 0x47>;
compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a";
fifo-size = <0x10>;
interrupt-names = "ip2intc_irpt";
interrupt-parent = <0x5>;
interrupts = <0x0 0x5a 0x1>;
num-cs = <0x1>;
reg = <0x0 0xa0040000 0x0 0x10000>;
xlnx,num-ss-bits = <0x1>;
xlnx,spi-mode = <0x0>;
phandle = <0x86>;
};
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000 0x8 0x0 0x0 0x80000000>;
};
clocks {
clock@0 {
#clock-cells = <0x0>;
compatible = "adjustable-clock";
clock-frequency = <0x2625a00>;
clock-accuracy = <0x30d40>;
clock-output-names = "ad9364_ext_refclk";
phandle = <0x19>;
};
};
fpga-axi@0 {
interrupt-parent = <0x5>;
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges = <0x0 0x0 0x0 0xffffffff>;
phandle = <0x87>;
axi_dmac@9c400000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x9c400000 0x1000>;
#dma-cells = <0x1>;
#clock-cells = <0x0>;
interrupts = <0x0 0x6d 0x4>;
clocks = <0x4 0x47>;
phandle = <0x23>;
adi,channels {
#size-cells = <0x0>;
#address-cells = <0x1>;
dma-channel@0 {
reg = <0x0>;
adi,source-bus-width = <0x40>;
adi,source-bus-type = <0x2>;
adi,destination-bus-width = <0x40>;
adi,destination-bus-type = <0x0>;
};
};
};
axi_dmac1@9c420000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x9c420000 0x1000>;
#dma-cells = <0x1>;
#clock-cells = <0x0>;
interrupts = <0x0 0x6c 0x4>;
clocks = <0x4 0x47>;
phandle = <0x25>;
adi,channels {
#size-cells = <0x0>;
#address-cells = <0x1>;
dma-channel@0 {
reg = <0x0>;
adi,source-bus-width = <0x40>;
adi,source-bus-type = <0x0>;
adi,destination-bus-width = <0x40>;
adi,destination-bus-type = <0x2>;
};
};
};
cf-ad9361-lpc@99020000 {
compatible = "adi,axi-ad9361-6.00.a";
reg = <0x99020000 0x6000>;
dmas = <0x23 0x0>;
dma-names = "rx";
spibus-connected = <0x24>;
phandle = <0x88>;
};
cf-ad9361-dds-core-lpc@99024000 {
compatible = "adi,axi-ad9364-dds-6.00.a";
reg = <0x99024000 0x1000>;
clocks = <0x24 0xd>;
clock-names = "sampl_clk";
dmas = <0x25 0x0>;
dma-names = "tx";
phandle = <0x89>;
};
axi_sysid-0@85000000 {
compatible = "adi,axi-sysid-1.00.a";
reg = <0x85000000 0x10000>;
phandle = <0x8a>;
};
};
__symbols__ {
cpu0 = "/cpus/cpu@0";
cpu1 = "/cpus/cpu@1";
cpu2 = "/cpus/cpu@2";
cpu3 = "/cpus/cpu@3";
L2 = "/cpus/l2-cache";
CPU_SLEEP_0 = "/cpus/idle-states/cpu-sleep-0";
cpu_opp_table = "/opp-table-cpu";
zynqmp_ipi = "/zynqmp_ipi";
ipi_mailbox_pmu1 = "/zynqmp_ipi/mailbox@ff9905c0";
dcc = "/dcc";
zynqmp_firmware = "/firmware/zynqmp-firmware";
zynqmp_power = "/firmware/zynqmp-firmware/zynqmp-power";
soc_revision = "/firmware/zynqmp-firmware/nvmem_firmware/soc_revision@0";
efuse_dna = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_dna@c";
efuse_usr0 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr0@20";
efuse_usr1 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr1@24";
efuse_usr2 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr2@28";
efuse_usr3 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr3@2c";
efuse_usr4 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr4@30";
efuse_usr5 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr5@34";
efuse_usr6 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr6@38";
efuse_usr7 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr7@3c";
efuse_miscusr = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_miscusr@40";
efuse_chash = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_chash@50";
efuse_pufmisc = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_pufmisc@54";
efuse_sec = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_sec@58";
efuse_spkid = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_spkid@5c";
efuse_ppk0hash = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_ppk0hash@a0";
efuse_ppk1hash = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_ppk1hash@d0";
zynqmp_pcap = "/firmware/zynqmp-firmware/pcap";
zynqmp_reset = "/firmware/zynqmp-firmware/reset-controller";
pinctrl0 = "/firmware/zynqmp-firmware/pinctrl";
pinctrl_sdhci0_default = "/firmware/zynqmp-firmware/pinctrl/sdhci0-default";
modepin_gpio = "/firmware/zynqmp-firmware/gpio";
zynqmp_clk = "/firmware/zynqmp-firmware/clock-controller";
fpga_full = "/fpga-full";
amba = "/axi";
can0 = "/axi/can@ff060000";
can1 = "/axi/can@ff070000";
cci = "/axi/cci@fd6e0000";
fpd_dma_chan1 = "/axi/dma-controller@fd500000";
fpd_dma_chan2 = "/axi/dma-controller@fd510000";
fpd_dma_chan3 = "/axi/dma-controller@fd520000";
fpd_dma_chan4 = "/axi/dma-controller@fd530000";
fpd_dma_chan5 = "/axi/dma-controller@fd540000";
fpd_dma_chan6 = "/axi/dma-controller@fd550000";
fpd_dma_chan7 = "/axi/dma-controller@fd560000";
fpd_dma_chan8 = "/axi/dma-controller@fd570000";
gic = "/axi/interrupt-controller@f9010000";
gpu = "/axi/gpu@fd4b0000";
lpd_dma_chan1 = "/axi/dma-controller@ffa80000";
lpd_dma_chan2 = "/axi/dma-controller@ffa90000";
lpd_dma_chan3 = "/axi/dma-controller@ffaa0000";
lpd_dma_chan4 = "/axi/dma-controller@ffab0000";
lpd_dma_chan5 = "/axi/dma-controller@ffac0000";
lpd_dma_chan6 = "/axi/dma-controller@ffad0000";
lpd_dma_chan7 = "/axi/dma-controller@ffae0000";
lpd_dma_chan8 = "/axi/dma-controller@ffaf0000";
mc = "/axi/memory-controller@fd070000";
nand0 = "/axi/nand-controller@ff100000";
gem0 = "/axi/ethernet@ff0b0000";
gem1 = "/axi/ethernet@ff0c0000";
gem2 = "/axi/ethernet@ff0d0000";
gem3 = "/axi/ethernet@ff0e0000";
phy0 = "/axi/ethernet@ff0e0000/mdio/ethernet-phy@1";
gpio = "/axi/gpio@ff0a0000";
i2c0 = "/axi/i2c@ff020000";
i2c1 = "/axi/i2c@ff030000";
eeprom = "/axi/i2c@ff030000/eeprom@50";
eeprom_cc = "/axi/i2c@ff030000/eeprom@51";
da9131 = "/axi/i2c@ff030000/pmic@33";
da9131_buck1 = "/axi/i2c@ff030000/pmic@33/regulators/buck1";
da9131_buck2 = "/axi/i2c@ff030000/pmic@33/regulators/buck2";
da9130 = "/axi/i2c@ff030000/pmic@32";
da9130_buck1 = "/axi/i2c@ff030000/pmic@32/regulators/buck1";
ocm = "/axi/memory-controller@ff960000";
perf_monitor_ocm = "/axi/perf-monitor@ffa00000";
perf_monitor_ddr = "/axi/perf-monitor@fd0b0000";
perf_monitor_cci = "/axi/perf-monitor@fd490000";
perf_monitor_lpd = "/axi/perf-monitor@ffa10000";
pcie = "/axi/pcie@fd0e0000";
pcie_intc = "/axi/pcie@fd0e0000/legacy-interrupt-controller";
qspi = "/axi/spi@ff0f0000";
spi_flash = "/axi/spi@ff0f0000/flash@0";
psgtr = "/axi/phy@fd400000";
rtc = "/axi/rtc@ffa60000";
sata = "/axi/ahci@fd0c0000";
sdhci0 = "/axi/mmc@ff160000";
sdhci1 = "/axi/mmc@ff170000";
smmu = "/axi/smmu@fd800000";
spi0 = "/axi/spi@ff040000";
adc0_ad9361 = "/axi/spi@ff040000/ad9361-phy@0";
spi1 = "/axi/spi@ff050000";
ttc0 = "/axi/timer@ff110000";
ttc1 = "/axi/timer@ff120000";
ttc2 = "/axi/timer@ff130000";
ttc3 = "/axi/timer@ff140000";
uart0 = "/axi/serial@ff000000";
uart1 = "/axi/serial@ff010000";
usb0 = "/axi/usb@ff9d0000";
dwc3_0 = "/axi/usb@ff9d0000/usb@fe200000";
usb1 = "/axi/usb@ff9e0000";
dwc3_1 = "/axi/usb@ff9e0000/usb@fe300000";
watchdog0 = "/axi/watchdog@fd4d0000";
lpd_watchdog = "/axi/watchdog@ff150000";
xilinx_ams = "/axi/ams@ffa50000";
ams_ps = "/axi/ams@ffa50000/ams_ps@0";
ams_pl = "/axi/ams@ffa50000/ams_pl@400";
zynqmp_dpdma = "/axi/dma-controller@fd4c0000";
zynqmp_dpaud_setting = "/axi/dp_aud@fd4ac000";
zynqmp_dpsub = "/axi/display@fd4a0000";
zynqmp_dp_snd_codec0 = "/axi/display@fd4a0000/zynqmp_dp_snd_codec0";
zynqmp_dp_snd_pcm0 = "/axi/display@fd4a0000/zynqmp_dp_snd_pcm0";
zynqmp_dp_snd_pcm1 = "/axi/display@fd4a0000/zynqmp_dp_snd_pcm1";
zynqmp_dp_snd_card0 = "/axi/display@fd4a0000/zynqmp_dp_snd_card";
fclk0 = "/fclk0";
fclk1 = "/fclk1";
fclk2 = "/fclk2";
fclk3 = "/fclk3";
pss_ref_clk = "/pss_ref_clk";
video_clk = "/video_clk";
pss_alt_ref_clk = "/pss_alt_ref_clk";
gt_crx_ref_clk = "/gt_crx_ref_clk";
aux_ref_clk = "/aux_ref_clk";
dp_aclk = "/dp_aclk";
amba_pl = "/amba_pl@0";
Memory_devices_FRAM_SPI = "/amba_pl@0/axi_quad_spi@a0000000";
Memory_devices_NOR_Flash_NOR0_QSPI = "/amba_pl@0/axi_quad_spi@a0010000";
Memory_devices_NOR_Flash_NOR1_QSPI = "/amba_pl@0/axi_quad_spi@a0020000";
Memory_devices_NOR_Flash_NOR2_QSPI = "/amba_pl@0/axi_quad_spi@a0030000";
Memory_devices_TLM_SPI = "/amba_pl@0/axi_quad_spi@a0040000";
ad9364_clkin = "/clocks/clock@0";
fpga_axi = "/fpga-axi@0";
rx_dma = "/fpga-axi@0/axi_dmac@9c400000";
tx_dma = "/fpga-axi@0/axi_dmac1@9c420000";
cf_ad9361_adc_core_0 = "/fpga-axi@0/cf-ad9361-lpc@99020000";
cf_ad9361_dac_core_0 = "/fpga-axi@0/cf-ad9361-dds-core-lpc@99024000";
axi_sysid_0 = "/fpga-axi@0/axi_sysid-0@85000000";
};
};
Also I skip tuning for both RX and TX because when I dont TX tuning fails, maybe thats part of the issue? When i skip tuning and run tuning verification as shown here.
https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/interface_timing_validation
I get the following with two different Sample Rates. I have a 40 Mhz external clock. If any more info is needed let me know. 
