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Questions about AD9082-FMCA-EBZ board

Category: Software
Product Number: AD9082-FMCA-EBZ, AD9082

Hello,

One of our customers has the following questions:  

A few months ago, my company bought an AD9082-FMCA-EBZ board. We are going to use the “AD9082-FMCA-EBZ board” with an “Mercury XU8 SoC and ST1 board” from the Enclustra company (basically the Mercury XU8 SoC is a Xilinx Zynq

UltraScale+ MPSoC Module).



Based on the hdl (https://urldefense.com/v3/__https://github.com/analogdevicesinc/hdl__;!!A3Ni8CS0y2Y!6A7y31gGLhzNc9kx_WB1UwuZNVYRXikd5CN-CFvonnW0aOwVgcC_xGFP36XHpeYtiD_7dqe0qL2uLUzR9t73Zg$ ) for a ZCU102, I have made the modifications to adapt the hdl for Mercury XU8/ST1. The modified design considers the same clock for transmission and reception (due to available pins on the FMC connector of Mercury XU8/ST1, we use clkin10_n/p while clkin6_n/p are not used).



To build the embedded Linux I configured the tools and I was able to build the Linux using Petalinux for the ZCU102 case. I have tried to replicate the same steps for the Mercury XU8/ST1 and found the following

limitations:



---------------------------------------

Case 1: usign meta-adi git repository



* There is no coincidence between the versions of Enclustra and ADI to build embedded Linux. Enclusta provides the BSP files (https://urldefense.com/v3/__https://github.com/enclustra/Mercury_XU8_ST1_Reference_Design/releases__;!!A3Ni8CS0y2Y!6A7y31gGLhzNc9kx_WB1UwuZNVYRXikd5CN-CFvonnW0aOwVgcC_xGFP36XHpeYtiD_7dqe0qL2uLUzNNn0m0Q$ ) for Petalinux versions 2020.1 / 2020.2 / 2022.1. While ADI provides the meta-adi (https://urldefense.com/v3/__https://github.com/analogdevicesinc/meta-adi__;!!A3Ni8CS0y2Y!6A7y31gGLhzNc9kx_WB1UwuZNVYRXikd5CN-CFvonnW0aOwVgcC_xGFP36XHpeYtiD_7dqe0qL2uLUxzUhDNIQ$ ) for Petalinux versions 2018_R2 / 2019_R1 / 2019_R2 / 2021_R1 / 2021_R2 / 2022_R2 / 2023.1.



* I have not found a document that explains the proper way to create ‘device tree’ files (for example zynqmp-zcu102-rev10-ad9082-m4-l8.dts).

To build embedded Linux I need the  device tree files adapted to the Mercury XU8/ST1.



---------------------------------------

Case 2: using pbeltram git repository



* In the ADI EngineerZone, I found the following post:

https://ez.analog.com/fpga/f/q-a/573360/enclustra-st1-xu8-and-ad-fmcomms3-ebz/504460

The publication says that it worked with AD-FMCOMMS3-EBZ and the Mercury XU8/ST1, and access is also given to the git repository. I have followed the steps to build embedded Linux but like the previous case I do not have the device tree files.



* I manage to generate some device tree files by following the steps provided in https://urldefense.com/v3/__https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842279/Build*Device*Tree*Blob__;Kysr!!A3Ni8CS0y2Y!6A7y31gGLhzNc9kx_WB1UwuZNVYRXikd5CN-CFvonnW0aOwVgcC_xGFP36XHpeYtiD_7dqe0qL2uLUwNxCdeFw$ , in the generated files I do not find any reference to adi (axi_ad9081_adxcvr_rx, axi_ad9081_core_tx, adi,jesd-links, ad9081_adc0, ad9081_dac0, etc).

---------------------------------------



I have the following questions:



1). Could you generate the device tree files for the case of AD9082-FMCA-EBZ and Mercury XU8/ST1, or provide me with a guide on how to write these files?



2). For building embedded Linux, what steps and strategies can you recommend (case 1, case 2, or another more generic case that you know of)?



3). For another application we are going to use the AD9082-FMCA-EBZ but with another Zynq UltraScale+ model, do you know a generic method or flow for building embedded Linux?



I attach the system_top.xsa file generated with the hdl repository (adapted for AD9082-FMCA-EBZ and Mercury XU8/ST1) and the vivado 2020.2 version.

Please contact me directly so I can share the xsa file mentioned above.

Thanks

Alex Moreira

Thread Notes

Parents
  • 1). Could you generate the device tree files for the case of AD9082-FMCA-EBZ and Mercury XU8/ST1, or provide me with a guide on how to write these files?

    Unfortunately we can't do that for you.

    Please take a look here:

    1. https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9081-default.dtsi
    2. https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9082-m4-l8.dts

    This will be very similar to yours.

    The first one has the device nodes for the PL side.

    While the second one has the nodes for the SPI devices in the PL.

    2). For building embedded Linux, what steps and strategies can you recommend (case 1, case 2, or another more generic case that you know of)?

    I would use meta-adi

    Please follow the instructions on the README.md here: (Adding a new Devicetree)

    https://github.com/analogdevicesinc/meta-adi/tree/main/meta-adi-xilinx

    3). For another application we are going to use the AD9082-FMCA-EBZ but with another Zynq UltraScale+ model, do you know a generic method or flow for building embedded Linux?

    You can also follow this guide here:

    https://wiki.analog.com/resources/tools-software/linux-build/generic/zynqmp

    That's what most people do. 

    -Michael

  • Hello,

    Please see below response from customer:

    As suggested, in the devicetree file adi,axi-pl-fifo-enable has been added as follows:

     

    &axi_ad9081_core_tx {

    adi,axi-pl-fifo-enable;

    };

     

    &axi_ad9081_core_rx {

    adi,axi-pl-fifo-enable;

    };

     

    Unfortunately the results have not changed much, the problem still persists.

    I attach a new figure from IIO Oscilloscope.

     

    By executing the iio_attr -D hmc7044 status command we have:

    ST1ME-XU8-4CG-1E-D11E:~# iio_attr -D hmc7044 status

    --- PLL1 ---

    Status: Locked

    Using: CLKIN0 @ 100000000 Hz

    PFD: 1000 kHz

    --- PLL2 ---

    Status: Locked (Synchronized)

    Frequency: 3000000000 Hz (Autocal cap bank value: 13)

    SYSREF Status: Valid & Locked

    SYNC Status: Synchronized

    Lock Status: PLL1 & PLL2 Locked

    ST1ME-XU8-4CG-1E-D11E:~#

     

    Is this a correct result?

    The other suggestions to isolate the error are not yet done. I will send you the results as soon as possible.

     

    -------------------------------------------

    Regarding the questions asked:

     

    Can they confirm that their Vivado design successfully passes timing ?

    Our design successfully passes timing.

     

    One thing that confuses me a bit, is that the jesd_status_RX doesn’t seem to show lane related data. I need to check if it’s the case for our 2022 release. It would be interesting to know if there are reported errors on the lanes.

    The jesd_status does not show lane related data (as a note, when the AD9082-FMCA-EBZ board was tested on a zcu102, jesd_status also did not show the data related to the lane).

    The attached file called “jesd204-rx lane_info mexu8st1.txt” contains the information obtained by executing:

    grep "" /sys/bus/platform/drivers/axi-jesd204*/*/status /sys/bus/platform/drivers/axi-jesd204*/*/lane* /sys/bus/platform/drivers/axi-jesd204*/*/encoder

    ST1ME-XU8-4CG-1E-D11E:~# grep "" /sys/bus/platform/drivers/axi-jesd204*/*/status /sys/bus/platform/drivers/axi-jesd204*/*/lane* /sys/bus/platform/drivers/axi-jesd204*/*/encoder
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/status:Link is enabled
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/status:Measured Link Clock: 249.998 MHz
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/status:Reported Link Clock: 250.000 MHz
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/status:Measured Device Clock: 250.000 MHz
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/status:Reported Device Clock: 250.000 MHz
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/status:Desired Device Clock: 250.000 MHz
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/status:Lane rate: 10000.000 MHz
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/status:Lane rate / 40: 250.000 MHz
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/status:LMFC rate: 31.250 MHz
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/status:Link status: DATA
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/status:SYSREF captured: Yes
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/status:SYSREF alignment error: No
    /sys/bus/platform/drivers/axi-jesd204-tx/84b90000.axi-jesd204-tx/status:Link is enabled
    /sys/bus/platform/drivers/axi-jesd204-tx/84b90000.axi-jesd204-tx/status:Measured Link Clock: 250.000 MHz
    /sys/bus/platform/drivers/axi-jesd204-tx/84b90000.axi-jesd204-tx/status:Reported Link Clock: 250.000 MHz
    /sys/bus/platform/drivers/axi-jesd204-tx/84b90000.axi-jesd204-tx/status:Measured Device Clock: 250.000 MHz
    /sys/bus/platform/drivers/axi-jesd204-tx/84b90000.axi-jesd204-tx/status:Reported Device Clock: 250.000 MHz
    /sys/bus/platform/drivers/axi-jesd204-tx/84b90000.axi-jesd204-tx/status:Desired Device Clock: 250.000 MHz
    /sys/bus/platform/drivers/axi-jesd204-tx/84b90000.axi-jesd204-tx/status:Lane rate: 10000.000 MHz
    /sys/bus/platform/drivers/axi-jesd204-tx/84b90000.axi-jesd204-tx/status:Lane rate / 40: 250.000 MHz
    /sys/bus/platform/drivers/axi-jesd204-tx/84b90000.axi-jesd204-tx/status:LMFC rate: 31.250 MHz
    /sys/bus/platform/drivers/axi-jesd204-tx/84b90000.axi-jesd204-tx/status:SYNC~: deasserted
    /sys/bus/platform/drivers/axi-jesd204-tx/84b90000.axi-jesd204-tx/status:Link status: DATA
    /sys/bus/platform/drivers/axi-jesd204-tx/84b90000.axi-jesd204-tx/status:SYSREF captured: Yes
    /sys/bus/platform/drivers/axi-jesd204-tx/84b90000.axi-jesd204-tx/status:SYSREF alignment error: No
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane0_info:Errors: 0
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane0_info:CGS state: DATA
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane0_info:Initial Frame Synchronization: Yes
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane0_info:Lane Latency: 3 Multi-frames and 7 Octets
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane0_info:Initial Lane Alignment Sequence: Yes
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane0_info:DID: 0, BID: 0, LID: 2, L: 8, SCR: 1, F: 1
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane0_info:K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 1
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane0_info:FCHK: 0x89, CF: 0
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane0_info:ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane0_info:FC: 10000000
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane1_info:Errors: 0
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane1_info:CGS state: DATA
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane1_info:Initial Frame Synchronization: Yes
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane1_info:Lane Latency: 3 Multi-frames and 6 Octets
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane1_info:Initial Lane Alignment Sequence: Yes
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane1_info:DID: 0, BID: 0, LID: 0, L: 8, SCR: 1, F: 1
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane1_info:K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 1
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane1_info:FCHK: 0x87, CF: 0
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane1_info:ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane1_info:FC: 10000000
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane2_info:Errors: 0
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane2_info:CGS state: DATA
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane2_info:Initial Frame Synchronization: Yes
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane2_info:Lane Latency: 3 Multi-frames and 6 Octets
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane2_info:Initial Lane Alignment Sequence: Yes
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane2_info:DID: 0, BID: 0, LID: 7, L: 8, SCR: 1, F: 1
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane2_info:K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 1
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane2_info:FCHK: 0x8E, CF: 0
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane2_info:ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane2_info:FC: 10000000
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane3_info:Errors: 0
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane3_info:CGS state: DATA
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane3_info:Initial Frame Synchronization: Yes
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane3_info:Lane Latency: 3 Multi-frames and 6 Octets
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane3_info:Initial Lane Alignment Sequence: Yes
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane3_info:DID: 0, BID: 0, LID: 6, L: 8, SCR: 1, F: 1
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane3_info:K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 1
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane3_info:FCHK: 0x8D, CF: 0
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane3_info:ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane3_info:FC: 10000000
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane4_info:Errors: 0
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane4_info:CGS state: DATA
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane4_info:Initial Frame Synchronization: Yes
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane4_info:Lane Latency: 3 Multi-frames and 3 Octets
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane4_info:Initial Lane Alignment Sequence: Yes
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane4_info:DID: 0, BID: 0, LID: 5, L: 8, SCR: 1, F: 1
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane4_info:K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 1
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane4_info:FCHK: 0x8C, CF: 0
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane4_info:ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane4_info:FC: 10000000
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane5_info:Errors: 0
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane5_info:CGS state: DATA
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane5_info:Initial Frame Synchronization: Yes
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane5_info:Lane Latency: 3 Multi-frames and 8 Octets
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane5_info:Initial Lane Alignment Sequence: Yes
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane5_info:DID: 0, BID: 0, LID: 4, L: 8, SCR: 1, F: 1
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane5_info:K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 1
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane5_info:FCHK: 0x8B, CF: 0
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane5_info:ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane5_info:FC: 10000000
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane6_info:Errors: 0
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane6_info:CGS state: DATA
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane6_info:Initial Frame Synchronization: Yes
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane6_info:Lane Latency: 3 Multi-frames and 6 Octets
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane6_info:Initial Lane Alignment Sequence: Yes
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane6_info:DID: 0, BID: 0, LID: 3, L: 8, SCR: 1, F: 1
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane6_info:K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 1
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane6_info:FCHK: 0x8A, CF: 0
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane6_info:ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane6_info:FC: 10000000
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane7_info:Errors: 0
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane7_info:CGS state: DATA
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane7_info:Initial Frame Synchronization: Yes
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane7_info:Lane Latency: 3 Multi-frames and 6 Octets
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane7_info:Initial Lane Alignment Sequence: Yes
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane7_info:DID: 0, BID: 0, LID: 1, L: 8, SCR: 1, F: 1
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane7_info:K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 1
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane7_info:FCHK: 0x88, CF: 0
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane7_info:ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/lane7_info:FC: 10000000
    /sys/bus/platform/drivers/axi-jesd204-rx/84a90000.axi-jesd204-rx/encoder:8b10b
    /sys/bus/platform/drivers/axi-jesd204-tx/84b90000.axi-jesd204-tx/encoder:8b10b
    ST1ME-XU8-4CG-1E-D11E:~#
    

    Additional information Feb 07th >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>

    I attach the figures that show the results using test mode RAMP.

     

    To use the Eye Scan tool, in the links provided it is not clear how the installation is carried out, and I have not found a document that explains it.

    Is there a document that clarifies the installation mode and configuration?

     

    On the other hand, the Mercury XU8/ST1 has 2GB DDR4 memory in the PS part. Reviewing the address map of the HDL architecture (see the figure called “address map - mexu8st1”), apparently the Mercury XU8/ST1 would require more than 2GB, is this correct?

       

      

  • Hi,

    As suggested, in the devicetree file adi,axi-pl-fifo-enable has been added as follows:

    This looks good, but it would be good to see the entire devicetree.

    The jesd_status does not show lane related data (as a note, when the AD9082-FMCA-EBZ board was tested on a zcu102, jesd_status also did not show the data related to the lane).

    I guess the problem is different. Either the lane data is truncated or there are missing permissions. The exclude both - use resize and execute as root

    #sudo su

    #resize 

    #jesd_status -s

    The attached file called “jesd204-rx lane_info mexu8st1.txt” contains the information obtained by executing:

    This looks good.

    To use the Eye Scan tool, in the links provided it is not clear how the installation is carried out, and I have not found a document that explains it.

    Is there a document that clarifies the installation mode and configuration?

    https://wiki.analog.com/resources/tools-software/linux-software/jesd_eye_scan

    Is include in our Kuiper default image. Just start it.

    In case you board is not video enabled. Use X11 forwarding.

    -Michael

Reply
  • Hi,

    As suggested, in the devicetree file adi,axi-pl-fifo-enable has been added as follows:

    This looks good, but it would be good to see the entire devicetree.

    The jesd_status does not show lane related data (as a note, when the AD9082-FMCA-EBZ board was tested on a zcu102, jesd_status also did not show the data related to the lane).

    I guess the problem is different. Either the lane data is truncated or there are missing permissions. The exclude both - use resize and execute as root

    #sudo su

    #resize 

    #jesd_status -s

    The attached file called “jesd204-rx lane_info mexu8st1.txt” contains the information obtained by executing:

    This looks good.

    To use the Eye Scan tool, in the links provided it is not clear how the installation is carried out, and I have not found a document that explains it.

    Is there a document that clarifies the installation mode and configuration?

    https://wiki.analog.com/resources/tools-software/linux-software/jesd_eye_scan

    Is include in our Kuiper default image. Just start it.

    In case you board is not video enabled. Use X11 forwarding.

    -Michael

Children
  • Regarding the HDL design:

    - How big is the data storage on RX and TX side ?

    - Are you working on the main hdl branch, or one of the releases?

  • Hi Adrian and Michael,

    See below the response from customer for both HW and SW issues:

    I send you the HDL architecture files for the HW team. I only send the created and modified files, for some reason I cannot send all the project files. (Alex comments: I have not received the HDL architecture files yet, as his attachment is being blocked, I am sorting this out with IT, will share the file with you as soon as I get it)

    I also sent you the devicetree files for the SW team and a question. (Alex comments: I will send the files to you via email)

     

    ---------------------------------------------------

    HW architecture

    I am attaching the modified/created files of the HDL architecture (hdl_2022_r2.zip). To generate the project copy/replace the attached files in the cloned HDL (version HDL_2022_R2) folder.

    Below is a list of files created and modified:

    - In folder <path-to-hdl>/library/common/, you can find the “ad_mem_asym.v” file.

    - In folder <path-to-hdl>/library/util_do_ram/, to use my_ad_mem_asym.v, we modify the Makefile, util_do_ram_ip.tcl, and util_do_ram.v

    - In folder <path-to-hdl>/projects/ad9081_fmca_ebz/, you can find the “viqthor_xu8” folder.

    - In folder <path-to-hdl>/projects/ad9082_fmca_ebz/, you can find the “viqthor_xu8” folder.

    - In folder <path-to-hdl>/projects/common/, you can find the “viqthor_xu8” folder.

    - In folder <path-to-hdl>/projects/scripts/, we add the features of the Mercury XU8/ST1 in the “adi_project_xilinx.tcl” and “gtwizard_generator.tcl” files.

    - In file <path-to-hdl>/scripts/adi_env.tcl, we put the vivado version to 2022.1.

    - To obtain the system_top.xsa file, we open a terminal in the folder <path-to-hdl>/projects/ad9082_fmca_ebz/viqthor_xu8/ and write: make RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1 RX_LANE_RATE=10 TX_LANE_RATE=10

    ---------------------------------------------------

    SW - Embedded Linux

    This looks good, but it would be good to see the entire devicetree.

    I attach all devicetree files (mexu8_linux.zip, custom-devicetree.dts, pl-delete-nodes-custom-devicetree.dtsi).

    - “custom-devicetree.dts” and “pl-delete-nodes-custom-devicetree.dtsi” are created in folder <path-to-meta-adi>/meta-adi-xilinx/recipes-bsp/device-tree/files/

    - mexu8_linux.zip also has the “components/plnx_workspace/device-tree/device-tree/” folder that has the files generated when building the embedded Linux.

    - mexu8_linux.zip has the “project-spec/meta-user/recipes-bsp/device-tree/” folder that has the specific files for the Mercury XU8/ST1 and AD9082-FMCA-EBZ, these files are the ones used to generate the embedded Linux.

     

    I guess the problem is different. Either the lane data is truncated or there are missing permissions. The exclude both - use resize and execute as root

    #sudo su

    #resize

    #jesd_status -s

    The jesd_status -s command cannot be executed as root.

    I get the following message (using an ssh connection):

    sh: jesd_status: command not found

     

    How could I solve this problem?

    Please see below additional questions from customer:

    ___________________________________________________________________________________

    On the other hand, I would like to validate the behavior of the component called storage_unit (util_do_ram.v). This component is present in mxfe_rx_data_offload and mxfe_tx_data_offload and in our case it is where the ultra RAM memories are instantiated.

    1) Could you share a testbench with me to validate the behavior?

    2) Could you share the waveform of the I/O signals to read and write in the util_do_ram component?

    Below are the I/O signals involved in reading and writing.

    module util_do_ram #(
      parameter SRC_DATA_WIDTH = 512,
      parameter DST_DATA_WIDTH = 128,

      parameter LENGTH_WIDTH = 16
    ) (
      input                                    wr_request_enable,
      input                                    wr_request_valid,
      output  reg                              wr_request_ready = 1'b0,
      input   [LENGTH_WIDTH-1:0]               wr_request_length,
      output  reg [LENGTH_WIDTH-1:0]           wr_response_measured_length = 'h0,
      output  reg                              wr_response_eot = 1'b0,

      input                                    rd_request_enable,
      input                                    rd_request_valid,
      output                                   rd_request_ready,
      input   [LENGTH_WIDTH-1:0]               rd_request_length,
      output                                   rd_response_eot,

      // slave streaming AXI interface
      input                                    s_axis_aclk,
      input                                    s_axis_aresetn,
      output reg                               s_axis_ready = 1'b0,
      input                                    s_axis_valid,
      input  [SRC_DATA_WIDTH-1:0]              s_axis_data,
      input  [SRC_DATA_WIDTH/8-1:0]            s_axis_strb,
      input  [SRC_DATA_WIDTH/8-1:0]            s_axis_keep,
      input  [0:0]                             s_axis_user,
      input                                    s_axis_last,

      // master streaming AXI interface
      input                                    m_axis_aclk,
      input                                    m_axis_aresetn,
      input                                    m_axis_ready,
      output                                   m_axis_valid,
      output [DST_DATA_WIDTH-1:0]              m_axis_data,
      output [DST_DATA_WIDTH/8-1:0]            m_axis_strb,
      output [DST_DATA_WIDTH/8-1:0]            m_axis_keep,
      output [0:0]                             m_axis_user,
      output                                   m_axis_last
    );

  • The jesd_status -s command cannot be executed as root.

    I get the following message (using an ssh connection):

    sh: jesd_status: command not found

    Try to give the full path.

    #/usr/local/bin/jesd_status -s

    I would also try to run eye_scan

    And do some PRBS PHY tests:

    Please see here:

    -Michael

  • We are using analogdevicesinc/testbenches: Testbenches for HDL projects (github.com) for testbenches. We're currently verifying how up to date they are, as we're not continuously maintaining them at the moment.

    We also try to rebuild the project with your modifications running on ZCU102 to see if the same issue happens there.

    Could you try using the regular Data offload, without modifications for one of the tests? This may highlight if that's the problem on your side, even if the size of the buffer will be lower for this test.

    Regards,

    Adrian

  • Thank Adrian and Michael,

    Please see following observations and questions with the engineers.

     

    I have reduced the buffer size from 64*1024 to 16*1024 obtaining the following results.

    - Regular Data offload: using BRAMs with two clocks (clka and clkb), we observe that the sine signal is not distorted.

    - Modified Data offload: using BRAM with a single clock (clka or clkb): we observe that the sine signal is distorted. Since Ultra RAMs use a single clock, the signal is also distorted.

    - Modified Data offload: considering the ZCU102 and the full buffer size (64*1024), the modifications to the BRAMs were made to use a single clock (clka) and no alteration to the sine signal was observed.

    The results suggest that for the Mercury XU8/ST1 it is necessary to use BRAMs with both clocks (clka, clkb), possibly both clocks are not synchronized. In the case of the ZCU102, a single clock can be used for Modified Data offload, this leads me to ask the following questions:

    1) To use Ultra RAM memories, is it possible to synchronize the clka and clkb?

    2) Is the result obtained for ZCU102 a particular case?

    On the other hand:

    3) Can the AD9082-FMCA-EBZ board be used with the buffer size of 16*1024?

    4) What is the impact of reducing the buffer and memory size?

  • 1,2. We need to do more research into this, as we haven't used Ultra RAM yet in our designs, but without going into deep research, I cannot answer. We do have it on our roadmap, but don't plan to support it in the near future.

    3. Sure, you'll just be able to send a smaller continuous waveform The buffer size will give you the maximum number of samples that you can send continuously. The number of samples can be split between less channels, so you could send a longer waveform if you're not using all channels for that specific transmission. Depending on the sampling rate, you could potentially bypass the memory and send directly to the HP port (limitation is 128bits at 330Mhz per HP port). Also, depending on the application, you may chose a different split for the two memories ( TX and RX).

    I think your carrier has a PL DDR which may be used to store date for one of the directions. The ZCU102's PL memory is only 16 bits wide so it doesn't have enough bandwidth to be used in this configuration, that's why we don't use it in our designs. On ZC706 design we do use the DDR as an offload memory.

    Regards,

    Adrian

  • Hi Adrian and Michael,

    Please see the following observations and questions from customer:

    For our case, the Mercury XU8 has a PL DDR memory with the following characteristics:

    - The DDR bus width is 32-bit.

    - The DDR4 controller supports speeds up to 2400 Mbit/s (1200 MHz),

    - The maximum PL memory bandwidth on the Mercury+ XU8 module is:
    2400 Mbit/sec × 32 bit = 9600 MB/sec

     

    While the carriers supported by Analog Devices:

    - ZC706: 64 bits of data width.

    - VCU118: 80 bits of data width.

     

    1) Does the PL DDR of the Mercury XU8 with the mentioned characteristics have enough bandwidth?

    2) With respect to PL DDR memory, what are the minimum characteristics that PL DDR must have?

    In order to see how PL DDR memory is used, I have an additional question:

    What are the parameters used in the HDL code to generate an architecture that uses PL DRR memory considering the ZC706?

     

    Using the following command did not take DDR memory into account.

    make RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1 RX_LANE_RATE=10 TX_LANE_RATE=10 DAC_DO_MEM_TYPE=1

     

    In projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl I set "set dac_do_mem_type 1" and got the following errors:

    ERROR: [IP_Flow 19-3452] Invalid long/float value '' specified for parameter 'HBM sections per master(HBM_SEGMENTS_PER_MASTER)' for BD Cell 'storage_unit'.
    ERROR: [IP_Flow 19-3461] Value '24' is out of the range for parameter 'Storage size(LENGTH_WIDTH)' for BD Cell 'storage_unit' . Valid values are - 28, 29, 30, 31, 32, 33, 34
    CRITICAL WARNING: [IP_Flow 19-5622] Failed to create IP instance 'system_storage_unit_1'. Failed to customize IP instance 'system_storage_unit_1'. Failed to load customization data
    ERROR: [BD 41-1712] Create IP failed with errors
    ERROR: [BD 5-7] Error: running create_bd_cell  -vlnv analog.com:user:util_hbm:1.0 -type ip -name storage_unit .
    ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

    Thanks

  • Hi,

    I can comment only regarding this error:

    ERROR: [IP_Flow 19-3452] Invalid long/float value '' specified for parameter 'HBM sections per master(HBM_SEGMENTS_PER_MASTER)' for BD Cell 'storage_unit'.

    It was solved in this commit, but on the main branch. This didn't get the chance to be merged into hdl_2022_r2, and it won't be. https://github.com/analogdevicesinc/hdl/commit/608044d1245bb6d3ac05512a8e1132523c695994. You can cherry-pick it though. This error was discovered only when porting to Vivado 2023 versions, as before it wasn't reported somehow...

    Regards,
    Iulia

  • On ultrascale devices, theoretically we could go up to about 16.3 Gbps and our default design is 15Gbps for AD9082. If we take 8 lanes and 8B10B encoding, we have a bandwidth of 12GB/sec, so the PL DDR cannot keep up with that. Another thing to look at efficiencies of the DDR transfers, they may be 40-75% in a real system.  A use case with 10GBps lane rate will give 8 GB/sec requirements, which is kind of at the limit.

    However, depending on the application, this may be enough.

    Regards,

    Adrian

  • Hi Adrian, Iulia and Michael,

    Our customer has further observations and questions:

    I will share the four attachments via email.

    -----------------------------------------------------------------

    We have stopped using Ultra RAMs, now we only use BRAMs in the HDL design. Everything works normally when using the ADI IIO-Oscilloscope. When performing a python example test using pyadi-iio, we get the following message in the UART terminal:

    ad9081 spi1.0: channel ftw is not updated

     

    -----------------------------------------------------------------

    On the other hand, in our application we want to work only with real data (Total DCM = 1 and Total Interpolation = 1). Considering Tx Lane rate = Rx Lane rate = 10Gsps, Tx core clock = Rx core clock = Lane rate / 40 = 250 MHz, ADC rate = 2 Gsps, and DAC rate = 2 Gsps, we find the following parameters in the document called “AD9081/AD9082 System Development User Guide”:

    - RX, Page 115, Table 70: L= 8, M = 2, F = 1, S = 2, K = 32, N = 16, NP = 16, HD = 1, Total DCM = 1, JTX Async = False, JTX_MODE = 19.

    - TX, Page 164, Table 92: L= 8, M = 2, F = 1, S = 2, K = 32, N = 16, NP = 16, Dual Link = No, Interpolation Mode = 1x1, JESD204B Mode = 63.

    We adapt the device-tree file with the parameters presented and the jesd_status shows that the Tx and Rx configuration has no errors.

    When using ADI IIO-Oscilloscope, we cannot change the test mode, for example the ramp test mode is not executed. The tone produced by the DDS is always displayed. We also observe that the sinusoidal signal is always distorted. When using a python application we also observe the messages:

    ad9081 spi1.0: channel ftw is not updated

    ad9081 spi1.0: main ftw is not updated

     

    I attach the device-tree files, the python file, and figures for the following questions:

    1) Is the choice of parameters appropriate for the case of a Zynq UltraScale+?

    2) Is the configuration of the device-tree files correct?

    3) Are the messages obtained when running a python application normal?

    4) How could I solve the problem I encounter when using the ADI IIO-Oscilloscope?

    5) Would the distorted signal (see m2-l8-s2distorted waveform.png) be a consequence of using ADC rate = DAC rate = 2 Gsps?

     

    When disabling DDS in the ADI IIO-Oscilloscope, we can see the appearance of random pulses (see m2-l8-s2-random pulses.png). This seems to be unusual behavior.