Terasic de10nano with cn0540:make new u-boot to support ltc2308 data read

Hi, Sorry to bother you, I have some questions about modifying the qaurtus hdl file to add GPIOs, Could you please, by any chance, give me some information？
1. To generate soc_system.dts, there are three files needed: system_bd.sopcinfo, soc_system_board_info.xml and hps_common_board_info.xml,  the two .xml file that I used come from DE10-Nano_v.1.3.8_HWrevC_SystemCD\Demonstrations\SoC_FPGA\DE10_NANO_SoC_GHRD, Am I right? Or where the .xml files you used come from？
2. I use the command below to generate soc_system.dts

sopc2dts -i soc_system.sopcinfo/
  -o soc_system.dts/
  -t dts/
  --board soc_system_board_info.xml/
  --board hps_common_board_info.xml/
  --clocks/
  --sopc-parameters all/
  --bridge-removal all

It generated soc_system.dts,  but it also outputs information below:

    Unsupported interface kind: axi4stream_slave
    Unsupported interface kind: axi4stream_slave
    Unsupported interface kind: axi4stream_master
    Unsupported interface kind: axi4stream_master
    .....
    Component axi_dmac_0 of class axi_dmac is unknown
    Component axi_hdmi_tx_0 of class axi_hdmi_tx is unknown
    Component axi_spi_engine_0 of class axi_spi_engine is unknown
    Component axi_sysid_0 of class axi_sysid is unknown
    ....
    DTAppend: Unable to find parent, null, for next-level-cache. Adding to root
    DTAppend: Unable to find parent, null, for next-level-cache. Adding to root
    DTAppend: Unable to find parent, null, for cache-unified. Adding to root
    DTAppend: Unable to find parent, null, for arm,tag-latency. Adding to root
    ....

When I use soc_system.dts to generate the .dtb file, it outputs information below:

    ERROR (phandle_references): Reference to non-existent node or label "hps_0_L2"
    ERROR (phandle_references): Reference to non-existent node or label "hps_0_rstmgr"
    ERROR (phandle_references): Reference to non-existent node or label "hps_0_sysmgr"
    ....
    ERROR: Input tree has errors, aborting (use -f to force output)

Have you ever been in a similar situation?

Hi fireire233 ,

Thank you for your patience. We just got back from our holidays. I will contact the product owner and will get back to you asap.

Thanks and regards,
Jo

I boot the system successfully with the help of this web Altera SOC Quick Start Guide [Analog Devices Wiki].

I think adi dts file is not created automatically. I meet similar situation and i modify the dts file manually.

Thank you for your reply, I don't know how to modify the dts file manually yet, Maybe I should learn FPGA again from scratch.

Hi fireire233 ,

We are glad that your concern has been resolved. And thank you for sharing the solution, so that queries with similar concern could use this thread as their reference.

Regards,
Jo