Category: Software
Hi,
I'm using a Xilinx ZCU102 FPGA board to drive an AD9082-FMCA-EBZ. I have the HDL reference version 2021_r1 and Petalinux version 2021_r1..
So far, I managed to manipulate the HDL and the Petalinux device tree to achieve different sampling frequencies and interpolation/decimation rates. I employ the ADs MxFE JESD selection tool as the starting point.
For some reason, I cannot achieve the decimation/interpolation of 16/32, while the DAC/ADC sampling rate is 12G/6G Hz! Here are the JESD modes suggested by the tool:
- TX JESD: Mode Number 15 txBW 300.0 Total Int 32 Coarse Int 8 Fine Int 4 Dual Link False JESD Deframer JESD204B L 8 M 8 F 2 S 1 K 32 N 16 NP 16 LaneRate 7.5
- RX JESD: Mode Number 11.00 rxBW 305.25 Total Dec 16 Coarse Dec 4 Fine Dec 4 Dual Link False JESD Framer JESD204B Async False L 4 M 4 F 2 S 1 K 32 NP 16 LaneRate 7.5
To make the HLD reference I used the following command:
make JESD_MODE=8B10B\
RX_LANE_RATE=7.5\
TX_LANE_RATE=7.5\
RX_JESD_M=4 \
RX_JESD_L=4 \
RX_JESD_S=1 \
RX_JESD_F=2 \
RX_JESD_NP=16 \
TX_JESD_M=8 \
TX_JESD_L=8 \
TX_JESD_S=1 \
TX_JESD_F=2 \
TX_JESD_NP=16
Then I adjusted the device tree to get the following clocks. I calculated the clocked according the the datasheet. Note that there are two samples per clock at Tx and Rx. You can find the used device tree in the attachment.
Rx Qppl = XCVR_REFCLK_DIV2
Tx Qppl = XCVR_REFCLK_DIV2
DEV_REFCLK = 375 MHz
FPGA_SYSREF = DEV_SYSREF = 1953125
CORE_CLK_TX = CORE_CLK_RX_ALT = 375MHz/2 = 187.5 MHz
FPGA_REFCLK1= 375MHz
FPGA_REFCLK2 = 375 MHz
I get QPLL buffer underflow error for both TX and Rx! Below you see the JESD status.
When I see the register map, apparently the petalinux doesn't set the register 0X0CA for the Rx JESD correctly. According to the datasheet, this register should be 8, while when I read it, it's set to 3! I'm not sure if it has caused the issue. I verified the other registers (Table 64 datasheet) and they look fine.
Could you please help me with this issue?
Best,
Ali
* Analog Devices AD9082-FMC-EBZ
* https://wiki.analog.com/resources/eval/user-guides/quadmxfe/quick-start
* https://wiki.analog.com/resources/tools-software/linux-drivers/iio-mxfe/ad9081
*
* hdl_project: <ad9082_fmca_ebz/zcu102>
* board_revision: <>
*
* Copyright (C) 2019-2021 Analog Devices Inc.
*/
#include "zynqmp-zcu102-rev10-ad9081.dts"
&axi_ad9081_adxcvr_rx {
/* Switch to QPLL */
adi,sys-clk-select = <XCVR_QPLL>;
adi,out-clk-select = <XCVR_REFCLK_DIV2>;
//adi,out-clk-select = <XCVR_REFCLK>;
};
&axi_ad9081_adxcvr_tx {
/* Switch to QPLL */
adi,sys-clk-select = <XCVR_QPLL>;
adi,out-clk-select = <XCVR_REFCLK_DIV2>;
//adi,out-clk-select = <XCVR_REFCLK>;
};
&spi1 {
status = "okay";
hmc7044: hmc7044@0 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
compatible = "adi,hmc7044";
reg = <0>;
spi-max-frequency = <1000000>;
jesd204-device;
#jesd204-cells = <2>;
jesd204-sysref-provider;
adi,jesd204-max-sysref-frequency-hz = <2000000>; /* 2 MHz */
/*
* There are different versions of the AD9081-FMCA-EBZ & AD9082-FMCA-EBZ
* VCXO = 122.880 MHz, XO = 122.880MHz (AD9081-FMC-EBZ & AD9082-FMC-EBZ)
* VCXO = 100.000 MHz, XO = 100.000MHz (AD9081-FMC-EBZ-A2 & AD9082-FMC-EBZ-A2)
* To determine which board is which, read the freqency printed on the VCXO
* or use the fru-dump utility:
* #fru-dump -b /sys/bus/i2c/devices/15-0050/eeprom
*/
//adi,pll1-clkin-frequencies = <122880000 30720000 0 0>;
//adi,vcxo-frequency = <122880000>;
adi,pll1-clkin-frequencies = <100000000 100000000 0 0>;
adi,vcxo-frequency = <100000000>;
adi,pll1-loop-bandwidth-hz = <200>;
adi,pll2-output-frequency = <3000000000>;
adi,sysref-timer-divider = <1024>;
adi,pulse-generator-mode = <0>;
adi,clkin0-buffer-mode = <0x07>;
adi,clkin1-buffer-mode = <0x07>;
adi,oscin-buffer-mode = <0x15>;
adi,gpi-controls = <0x00 0x00 0x00 0x00>;
adi,gpo-controls = <0x37 0x33 0x00 0x00>;
clock-output-names =
"hmc7044_out0", "hmc7044_out1", "hmc7044_out2",
"hmc7044_out3", "hmc7044_out4", "hmc7044_out5",
"hmc7044_out6", "hmc7044_out7", "hmc7044_out8",
"hmc7044_out9", "hmc7044_out10", "hmc7044_out11",
"hmc7044_out12", "hmc7044_out13";
hmc7044_c0: channel@0 {
reg = <0>;
adi,extended-name = "CORE_CLK_RX";
adi,divider = <20>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
};
hmc7044_c2: channel@2 {
reg = <2>;
adi,extended-name = "DEV_REFCLK";
adi,divider = <8>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
};
hmc7044_c3: channel@3 {
reg = <3>;
adi,extended-name = "DEV_SYSREF";
adi,divider = <1536>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
adi,jesd204-sysref-chan;
};
hmc7044_c6: channel@6 {
reg = <6>;
adi,extended-name = "CORE_CLK_TX";
adi,divider = <16>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
};
hmc7044_c8: channel@8 {
reg = <8>;
adi,extended-name = "FPGA_REFCLK1";
adi,divider = <8>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
};
hmc7044_c10: channel@10 {
reg = <10>;
adi,extended-name = "CORE_CLK_RX_ALT";
adi,divider = <16>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
};
hmc7044_c12: channel@12 {
reg = <12>;
adi,extended-name = "FPGA_REFCLK2";
adi,divider = <8>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
};
hmc7044_c13: channel@13 {
reg = <13>;
adi,extended-name = "FPGA_SYSREF";
adi,divider = <1536>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
adi,jesd204-sysref-chan;
};
};
};
&fmc_spi {
trx0_ad9081: ad9081@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi,ad9082";
reg = <0>;
spi-max-frequency = <5000000>;
/* Clocks */
clocks = <&hmc7044 2>;
clock-names = "dev_clk";
clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
#clock-cells = <1>;
jesd204-device;
#jesd204-cells = <2>;
jesd204-top-device = <0>; /* This is the TOP device */
jesd204-link-ids = <FRAMER_LINK0_RX DEFRAMER_LINK0_TX>;
jesd204-inputs =
<&axi_ad9081_core_rx 0 FRAMER_LINK0_RX>,
<&axi_ad9081_core_tx 0 DEFRAMER_LINK0_TX>;
adi,tx-dacs {
#size-cells = <0>;
#address-cells = <1>;
adi,dac-frequency-hz = /bits/ 64 <12000000000>;
adi,main-data-paths {
#address-cells = <1>;
#size-cells = <0>;
adi,interpolation = <4>;
ad9081_dac0: dac@0 {
reg = <0>;
adi,crossbar-select = <&ad9081_tx_fddc_chan0>;
adi,nco-frequency-shift-hz = /bits/ 64 <2000000000>; /* 1000 MHz */
};
ad9081_dac1: dac@1 {
reg = <1>;
adi,crossbar-select = <&ad9081_tx_fddc_chan1>;
adi,nco-frequency-shift-hz = /bits/ 64 <2000000000>; /* 1100 MHz */
};
ad9081_dac2: dac@2 {
reg = <2>;
adi,crossbar-select = <&ad9081_tx_fddc_chan2>;
adi,nco-frequency-shift-hz = /bits/ 64 <2000000000>; /* 1000 MHz */
};
ad9081_dac3: dac@3 {
reg = <3>;
adi,crossbar-select = <&ad9081_tx_fddc_chan3>;
adi,nco-frequency-shift-hz = /bits/ 64 <2000000000>; /* 1100 MHz */
};
};
adi,channelizer-paths {
#address-cells = <1>;
#size-cells = <0>;
adi,interpolation = <8>;
ad9081_tx_fddc_chan0: channel@0 {
reg = <0>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_tx_fddc_chan1: channel@1 {
reg = <1>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_tx_fddc_chan2: channel@2 {
reg = <2>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_tx_fddc_chan3: channel@3 {
reg = <3>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
};
adi,jesd-links {
#size-cells = <0>;
#address-cells = <1>;
ad9081_tx_jesd_l0: link@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
adi,logical-lane-mapping = /bits/ 8 <0 2 7 6 1 5 4 3>;
adi,link-mode = <15>; /* JESD Quick Configuration Mode */
adi,subclass = <1>; /* JESD SUBCLASS 0,1,2 */
adi,version = <1>; /* JESD VERSION 0=204A,1=204B,2=204C */
adi,dual-link = <0>; /* JESD Dual Link Mode */
adi,converters-per-device = <8>; /* JESD M */
adi,octets-per-frame = <2>; /* JESD F */
adi,frames-per-multiframe = <32>; /* JESD K */
adi,converter-resolution = <16>; /* JESD N */
adi,bits-per-sample = <16>; /* JESD NP' */
adi,control-bits-per-sample = <0>; /* JESD CS */
adi,lanes-per-device = <8>; /* JESD L */
adi,samples-per-converter-per-frame = <1>; /* JESD S */
adi,high-density = <1>; /* JESD HD */
adi,tpl-phase-adjust = <0>;
};
};
};
adi,rx-adcs {
#size-cells = <0>;
#address-cells = <1>;
adi,adc-frequency-hz = /bits/ 64 <6000000000>;
adi,main-data-paths {
#address-cells = <1>;
#size-cells = <0>;
ad9081_adc0: adc@0 {
reg = <0>;
adi,decimation = <4>;
adi,nco-frequency-shift-hz = /bits/ 64 <2000000000>;
adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
//adi,crossbar-select = <&ad9081_rx_fddc_chan0>, <&ad9081_rx_fddc_chan2>; /* Static for now */
};
ad9081_adc1: adc@1 {
reg = <1>;
adi,decimation = <4>;
adi,nco-frequency-shift-hz = /bits/ 64 <(2000000000)>;
adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
//adi,crossbar-select = <&ad9081_rx_fddc_chan1>, <&ad9081_rx_fddc_chan3>; /* Static for now */
};
};
adi,channelizer-paths {
#address-cells = <1>;
#size-cells = <0>;
ad9081_rx_fddc_chan0: channel@0 {
reg = <0>;
adi,decimation = <4>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_rx_fddc_chan1: channel@1 {
reg = <1>;
adi,decimation = <4>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
};
adi,jesd-links {
#size-cells = <0>;
#address-cells = <1>;
ad9081_rx_jesd_l0: link@0 {
reg = <0>;
adi,converter-select =
<&ad9081_rx_fddc_chan0 FDDC_I>, <&ad9081_rx_fddc_chan0 FDDC_Q>,
<&ad9081_rx_fddc_chan1 FDDC_I>, <&ad9081_rx_fddc_chan1 FDDC_Q>;
adi,logical-lane-mapping = /bits/ 8 <2 0 7 6 5 4 3 1>;
adi,link-mode = <11>; /* JESD Quick Configuration Mode */
adi,subclass = <1>; /* JESD SUBCLASS 0,1,2 */
adi,version = <1>; /* JESD VERSION 0=204A,1=204B,2=204C */
adi,dual-link = <0>; /* JESD Dual Link Mode */
adi,converters-per-device = <4>; /* JESD M */
adi,octets-per-frame = <2>; /* JESD F */
adi,frames-per-multiframe = <32>; /* JESD K */
adi,converter-resolution = <16>; /* JESD N */
adi,bits-per-sample = <16>; /* JESD NP' */
adi,control-bits-per-sample = <0>; /* JESD CS */
adi,lanes-per-device = <4>; /* JESD L */
adi,samples-per-converter-per-frame = <1>; /* JESD S */
adi,high-density = <1>; /* JESD HD */
};
};
};
};
};
