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AD9986 + ZCU102 Abnomal Work

Product Number: AD9986
Software Version: IIO-Oscilloscope - v0.16

Hi

   I have a one AD9986 EVAL Board and one ZCU102 Board. Refer to description of this website-https://wiki.analog.com/resources/eval/user-guides/ad9081_fmca_ebz/quickstart/zynqmp. I used the SD Card you provided to make ZCU102 boot. Boot mode choose from SD Card. When ZCU102 was fully started, I used the serial command to find the device, but I didn't find the device AD9986.  When I use IIO software, the list of devices is only HMC7044 and there is no AD9986. There is a print log.3288.ZCU102_print log.log

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  • I don't think we have such a use case drafted with a devicetree example.

    For AD9082 I'm pretty sure you could run ADC at 6G and then use decimate by 2 in the coarse DDC.

    That would give you 3G rate which should have 2.4G channel BW.

    And you can tune the main NCO to 1.5G.

    -Michael 

  • Can i get the mode that i want by modifying the device tree and boot file?

    If so, what should i do? 

  • You first need the user guide UG-1578.

    And select the JESD modes - you said you want to have 2 complex channels.

    So M=4, now you need to select a mode either from 204B or 204C and you also need to know how much lanes (L) you have/require. Number of bits (NP), etc.

    Also check that the required interpolation/decimation mode is available for a given mode.

    If you know all this, you can edit the devicetree.

    Set ADC/DAC frequency, enter the decimation/interpolation values and set the JESD mode.

    Please see here:

    https://wiki.analog.com/resources/tools-software/linux-drivers/iio-mxfe/ad9081#device_tree_customization

    -Michael

  • Hmm - with M=4 I think you need all 8 lanes and 204C encoding. Then your lane rate will be 24.750 Gbps.

  • Thanks, i will try it according to your method.If have any question, i will ask you again.

  • Hi

    I try to modify the system.dtb. Then open the software and find that it has no waveform. The Operation mode of the AD9986 what i need. As follow:

    ADC sample frequency is 6GHz.

    just one input channnel (channel ADC0).

    only enable CDDC1 and decimation=2, complex output, bypass FDDC, output data rate =3GSPS (I/Q).

    So it can achieve 2.44GHz Bandwidth analysis. 

    I just modeify the ADC part, and DAC part do not modify. Should I also modify DAC part?

    Part of the device tree information I modify is as below.  Thanks

                    adi,rx-adcs {
    					#size-cells = <0x00>;
    					#address-cells = <0x01>;
    					adi,adc-frequency-hz = <0x01 0x65a0bc00>;     
    
    					adi,main-data-paths {
    						#address-cells = <0x01>;
    						#size-cells = <0x00>;
    
    						adc@0 {
    							reg = <0x00>;
    							adi,decimation = <0x02>; (Modify Mark)
    							adi,nco-frequency-shift-hz = <0x00 0x3b9aca00>;
    							adi,nco-mode = <0x00>;
    						};
    
    						adc@1 {
    							reg = <0x01>;
    							adi,decimation = <0x02>;(Modify Mark)
    							adi,nco-frequency-shift-hz = <0x00 0x3b9aca00>;
    							adi,nco-mode = <0x00>;
    						};
    					};
    
    					adi,channelizer-paths {
    						#address-cells = <0x01>;
    						#size-cells = <0x00>;
    
    						channel@0 {
    							reg = <0x00>;
    							adi,decimation = <0x01>;
    							adi,gain = <0x800>;
    							adi,nco-frequency-shift-hz = <0x00 0x00>;
    							phandle = <0x22>;
    						};
    
    						channel@1 {
    							reg = <0x01>;
    							adi,decimation = <0x01>;
    							adi,gain = <0x800>;
    							adi,nco-frequency-shift-hz = <0x00 0x00>;
    							phandle = <0x23>;
    						};
    					};
    
    					adi,jesd-links {
    						#size-cells = <0x00>;
    						#address-cells = <0x01>;
    
    						link@0 {
    							reg = <0x00>;
    							adi,converter-select = <0x22 0x00 0x22 0x01 0x23 0x00 0x23 0x01>;
    							adi,logical-lane-mapping = <0x2000706 0x5040301>;
    							adi,link-mode = <0x12>;
    							adi,subclass = <0x01>;
    							adi,version = <0x01>;
    							adi,dual-link = <0x00>;
    							adi,converters-per-device = <0x02>;(Modify Mark)
    							adi,octets-per-frame = <0x01>;
    							adi,frames-per-multiframe = <0x20>;
    							adi,converter-resolution = <0x10>;
    							adi,bits-per-sample = <0x10>;
    							adi,control-bits-per-sample = <0x00>;
    							adi,lanes-per-device = <0x08>;
    							adi,samples-per-converter-per-frame = <0x02>;(Modify Mark)
    							adi,high-density = <0x01>;
    						};
    					};
    				};
    
    
            spi@ff050000 {
    			compatible = "cdns,spi-r1p6";
    			status = "okay";
    			interrupt-parent = <0x04>;
    			interrupts = <0x00 0x14 0x04>;
    			reg = <0x00 0xff050000 0x00 0x1000>;
    			clock-names = "ref_clk\0pclk";
    			#address-cells = <0x01>;
    			#size-cells = <0x00>;
    			power-domains = <0x0c 0x24>;
    			clocks = <0x03 0x3b 0x03 0x1f>;
    
    			hmc7044@0 {
    				#address-cells = <0x01>;
    				#size-cells = <0x00>;
    				#clock-cells = <0x01>;
    				compatible = "adi,hmc7044";
    				reg = <0x00>;
    				spi-max-frequency = <0xf4240>;
    				jesd204-device;
    				#jesd204-cells = <0x02>;
    				jesd204-sysref-provider;
    				adi,jesd204-max-sysref-frequency-hz = <0x1e8480>;
    				adi,pll1-clkin-frequencies = <0x7530000 0x1d4c000 0x00 0x00>;
    				adi,vcxo-frequency = <0x7530000>;
    				adi,pll1-loop-bandwidth-hz = <0xc8>;
    				adi,pll2-output-frequency = <0xb2d05e00>;
    				adi,sysref-timer-divider = <0x400>;
    				adi,pulse-generator-mode = <0x00>;
    				adi,clkin0-buffer-mode = <0x07>;
    				adi,clkin1-buffer-mode = <0x07>;
    				adi,oscin-buffer-mode = <0x15>;
    				adi,gpi-controls = <0x00 0x00 0x00 0x00>;
    				adi,gpo-controls = <0x37 0x33 0x00 0x00>;
    				clock-output-names = "hmc7044_out0\0hmc7044_out1\0hmc7044_out2\0hmc7044_out3\0hmc7044_out4\0hmc7044_out5\0hmc7044_out6\0hmc7044_out7\0hmc7044_out8\0hmc7044_out9\0hmc7044_out10\0hmc7044_out11\0hmc7044_out12\0hmc7044_out13";
    				phandle = <0x1d>;
    
    				channel@0 {
    					reg = <0x00>;
    					adi,extended-name = "CORE_CLK_RX";
    					adi,divider = <0x0c>;
    					adi,driver-mode = <0x02>;
    				};
    
    				channel@2 {
    					reg = <0x02>;
    					adi,extended-name = "DEV_REFCLK";
    					adi,divider = <0x0c>;
    					adi,driver-mode = <0x02>;
    				};
    
    				channel@3 {
    					reg = <0x03>;
    					adi,extended-name = "DEV_SYSREF";
    					adi,divider = <0x600>;
    					adi,driver-mode = <0x02>;
    					adi,jesd204-sysref-chan;
    				};
    
    				channel@6 {
    					reg = <0x06>;
    					adi,extended-name = "CORE_CLK_TX";
    					adi,divider = <0x0c>;
    					adi,driver-mode = <0x02>;
    				};
    
    				channel@8 {
    					reg = <0x08>;
    					adi,extended-name = "FPGA_REFCLK1";
    					adi,divider = <0x06>;
    					adi,driver-mode = <0x02>;
    				};
    
    				channel@10 {
    					reg = <0x0a>;
    					adi,extended-name = "CORE_CLK_RX_ALT";
    					adi,divider = <0x0c>;
    					adi,driver-mode = <0x02>;
    				};
    
    				channel@12 {
    					reg = <0x0c>;
    					adi,extended-name = "FPGA_REFCLK2";
    					adi,divider = <0x06>;
    					adi,driver-mode = <0x02>;
    				};
    
    				channel@13 {
    					reg = <0x0d>;
    					adi,extended-name = "FPGA_SYSREF";
    					adi,divider = <0x600>;
    					adi,driver-mode = <0x02>;
    					adi,jesd204-sysref-chan;
    				};
    			};
    		};