ad9375 + zcu102

jacobha

on Sep 13, 2023

i use adrv-dpd1(ad9375) with zcu102, everything is ok pll is locked but i have problem in jesd tx path (i cann't transmit anything) :

# dmesg -C

# cat profile_TxBW50_ORxBW50_RxBW50.txt > /sys/bus/iio/devices/iio:device2/profile_config

# dmesg

ad9371 spi1.1: deframerStatus (0x21)

WARNING: 136: Mismatch detected in MYKONOS_jesd204bIlasCheck()

ad9371 spi1.1: ILAS mismatch: c7f8

ad9371 spi1.1: ILAS lanes per converter did not match

ad9371 spi1.1: ILAS scrambling did not match

ad9371 spi1.1: ILAS octets per frame did not match

ad9371 spi1.1: ILAS frames per multiframe did not match

ad9371 spi1.1: ILAS number of converters did not match

ad9371 spi1.1: ILAS sample resolution did not match

ad9371 spi1.1: ILAS control bits per sample did not match

ad9371 spi1.1: ILAS bits per sample did not match

ad9371 spi1.1: ILAS checksum did not match

ad9371 spi1.1: obsFramerStatus (0x20)

i use petalinux 2021_R2

jacobha
[edited by: jacobha at 12:00 PM (GMT -4) on 13 Sep 2023]

Tags: ad9371 ad9528 ad9375 Wideband Transceiver IC rf and microwave RF Integrated Transceivers Show More

0 travisfcollins

on Sep 13, 2023 12:52 PM
Can you post your profile? You are likely using a profile that requires a device clock which cannot be generated. See here for more details: Changing the VCXO frequency and updating the default RF Transceiver Profile [Analog Devices Wiki]

-Travis
Cancel
Up 0 Down

Reply

Verify Answer

Cancel
0 jacobha
on Sep 15, 2023 2:15 AM in reply to travisfcollins
profiles I use are in https://github.com/analogdevicesinc/iio-oscilloscope/tree/master/filters/ad9371_5/ for ex: https://github.com/analogdevicesinc/iio-oscilloscope/blob/master/filters/ad9371_5/profile_TxBW50_ORxBW50_RxBW50.txt also default RF transceiver profile has same issue (when system boot up dmesg has same logs)
Cancel
Up 0 Down

Reply

Verify Answer

Cancel
0 travisfcollins

on Sep 15, 2023 7:05 PM in reply to jacobha
Does the board boot with all JESD Links functioning? After a fresh boot run the jesd_status command.

-Travis
Cancel
Up 0 Down

Reply

Verify Answer

Cancel
0 jacobha
on Sep 16, 2023 1:18 AM in reply to travisfcollins
after a fresh boot also I have same boot logs and tx path doesn't work , result of jesd_status after fresh boot:
Cancel
Up 0 Down

Reply

Verify Answer

Cancel
0 travisfcollins

on Sep 18, 2023 12:48 PM in reply to jacobha
Internal software team is checking the design now.

-Travis
Cancel
Up 0 Down

Reply

Verify Answer

Cancel
0 jacobha
on Sep 19, 2023 1:21 AM in reply to travisfcollins
thank you and I'm waiting
Cancel
Up 0 Down

Reply

Verify Answer

Cancel

0 mhennerich

on Sep 19, 2023 4:31 AM in reply to jacobha

Hi,

Can you please make sure you provide a 30.72MHz reference clock for the AD9528.

PLL1 should be locked. I have 2 ADRV9371s and 1 ADRV9375.

One of these boards show identical behavior in case the AD9528 PLL1 is not locked.

While works 100% when PLL1 is locked.

Please also make sure you use the devicetrees with the jesd204-fsm.dts suffix.

Kernel messages and jesd_status output below.

I also these the 50MHz BW profile and it works as well.

root@analog:~# iio_attr -d ad9528-1
dev 'ad9528-1', attr 'pll1_feedback_clk_present', value :'1'
dev 'ad9528-1', attr 'pll1_locked', value :'1'
dev 'ad9528-1', attr 'pll1_reference_clk_a_present', value :'1'
dev 'ad9528-1', attr 'pll1_reference_clk_ab_missing', value :'0'
dev 'ad9528-1', attr 'pll1_reference_clk_b_present', value :'0'
dev 'ad9528-1', attr 'pll2_feedback_clk_present', value :'1'
dev 'ad9528-1', attr 'pll2_locked', value :'1'
dev 'ad9528-1', attr 'sync_dividers', value :ERROR: Permission denied (13)
dev 'ad9528-1', attr 'vcxo_clk_present', value :'1'
root@analog:~#


[    5.821585] axi-jesd204-rx 84aa0000.axi-jesd204-rx: AXI-JESD204-RX (1.07.a) at 0x84AA0000. Encoder 8b10b, width 4/4, lanes 2, jesd204-fsm.
[    5.834463] axi-jesd204-rx 84ab0000.axi-jesd204-rx-os: AXI-JESD204-RX (1.07.a) at 0x84AB0000. Encoder 8b10b, width 4/4, lanes 2, jesd204-fsm.
[    5.847512] axi-jesd204-tx 84a90000.axi-jesd204-tx: AXI-JESD204-TX (1.06.a) at 0x84A90000. Encoder 8b10b, width 4/4, lanes 4, jesd204-fsm.
[    5.860364] ad9371 spi1.1: ad9371_probe : enter
[    5.893371] cf_axi_adc 84a00000.axi-ad9371-rx-hpc: ADI AIM (10.02.b) at 0x84A00000 mapped to 0x(____ptrval____) probed ADC AD9371 as MASTER
[    5.926080] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition initialized -> probed
[    5.937134] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition initialized -> probed
[    5.948184] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition initialized -> probed
[    5.959236] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition probed -> idle
[    5.969670] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition probed -> idle
[    5.980111] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition probed -> idle
[    5.990551] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition idle -> device_init
[    6.001422] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition idle -> device_init
[    6.012297] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition idle -> device_init
[    6.023172] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition device_init -> link_init
[    6.034476] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition device_init -> link_init
[    6.045796] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition device_init -> link_init
[    6.057120] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_init -> link_supported
[    6.068683] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_init -> link_supported
[    6.080245] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_init -> link_supported
[    6.092016] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_supported -> link_pre_setup
[    6.104021] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_supported -> link_pre_setup
[    6.116024] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_supported -> link_pre_setup
[    6.133549] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_pre_setup -> clk_sync_stage1
[    6.150878] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_pre_setup -> clk_sync_stage1
[    6.162969] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_pre_setup -> clk_sync_stage1
[    6.175062] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage1 -> clk_sync_stage2
[    6.187238] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clk_sync_stage1 -> clk_sync_stage2
[    6.199413] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clk_sync_stage1 -> clk_sync_stage2
[    6.211595] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage3
[    6.223769] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clk_sync_stage2 -> clk_sync_stage3
[    6.235946] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage3
[    6.250145] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage3 -> link_setup
[    6.261887] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clk_sync_stage3 -> link_setup
[    6.273627] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clk_sync_stage3 -> link_setup
[    7.003293] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_setup -> opt_setup_stage1
[    7.015130] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_setup -> opt_setup_stage1
[    7.026955] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_setup -> opt_setup_stage1
[   12.825505] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage1 -> opt_setup_stage2
[   12.837860] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage1 -> opt_setup_stage2
[   12.850215] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage1 -> opt_setup_stage2
[   12.862567] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage2 -> opt_setup_stage3
[   12.874915] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage2 -> opt_setup_stage3
[   12.887266] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage2 -> opt_setup_stage3
[   12.899622] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage3 -> opt_setup_stage4
[   12.911968] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage3 -> opt_setup_stage4
[   12.924312] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage3 -> opt_setup_stage4
[   12.936668] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage4 -> opt_setup_stage5
[   12.949015] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage4 -> opt_setup_stage5
[   12.961370] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage4 -> opt_setup_stage5
[   12.973978] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage5 -> clocks_enable
[   12.986072] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage5 -> clocks_enable
[   12.998161] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage5 -> clocks_enable
[   13.016442] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clocks_enable -> link_enable
[   13.028101] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clocks_enable -> link_enable
[   13.039756] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clocks_enable -> link_enable
[   13.086906] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_enable -> link_running
[   13.098478] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_enable -> link_running
[   13.110045] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_enable -> link_running
[   13.194239] ad9371 spi1.1: AD9375 Rev 4, Firmware 5.2.2 API version: 1.5.2.3566 successfully initialized via jesd204-fsm
[   13.205114] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_running -> opt_post_running_stage
[   13.217635] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_running -> opt_post_running_stage
[   13.230161] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_running -> opt_post_running_stage
[   13.242692] cf_axi_dds 84a04000.axi-ad9371-tx-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x84A04000 mapped to 0x(____ptrval____), probed DDS AD9371

  (DEVICES) Found 3 JESD204 Link Layer peripherals

  (0): axi-jesd204-rx/84ab0000.axi-jesd204-rx-os  [*]
  (1): axi-jesd204-rx/84aa0000.axi-jesd204-rx
  (2): axi-jesd204-tx/84a90000.axi-jesd204-tx

  (STATUS)
  Link is                      enabled
  Link Status                  DATA
  Measured Link Clock (MHz)    122.893
  Reported Link Clock (MHz)    122.880
  Measured Device Clock (MHz)  122.893
  Reported Device Clock (MHz)  122.880
  Desired Device Clock (MHz)   122.880
  Lane rate (MHz)              4915.200
  Lane rate / 40 (MHz)         122.880
  LMFC rate (MHz)              7.680
  SYSREF captured              Yes
  SYSREF alignment error       No
  SYNC~

  (LANE STATUS)
  Lane#                             0      1
  Errors                            0      0
  Latency (Multiframes/Octets)      1/62   2/0
  CGS State                         DATA   DATA
  Initial Frame Sync                Yes    Yes
  Initial Lane Alignment Sequence   Yes    Yes

  (DEVICES) Found 3 JESD204 Link Layer peripherals

  (0): axi-jesd204-rx/84ab0000.axi-jesd204-rx-os  [*]
  (1): axi-jesd204-rx/84aa0000.axi-jesd204-rx
  (2): axi-jesd204-tx/84a90000.axi-jesd204-tx

  (STATUS)
  Link is                      enabled
  Link Status                  DATA
  Measured Link Clock (MHz)    122.893
  Reported Link Clock (MHz)    122.880
  Measured Device Clock (MHz)  122.893
  Reported Device Clock (MHz)  122.880
  Desired Device Clock (MHz)   122.880
  Lane rate (MHz)              4915.200
  Lane rate / 40 (MHz)         122.880
  LMFC rate (MHz)              7.680
  SYSREF captured              Yes
  SYSREF alignment error       No
  SYNC~

  (LANE STATUS)
  Lane#                             0      1
  Errors                            0      0
  Latency (Multiframes/Octets)      1/62   2/0
  CGS State                         DATA   DATA
  Initial Frame Sync                Yes    Yes
  Initial Lane Alignment Sequence   Yes    Yes

  (DEVICES) Found 3 JESD204 Link Layer peripherals

  (0): axi-jesd204-rx/84ab0000.axi-jesd204-rx-os
  (1): axi-jesd204-rx/84aa0000.axi-jesd204-rx
  (2): axi-jesd204-tx/84a90000.axi-jesd204-tx  [*]

  (STATUS)
  Link is                      enabled
  Link Status                  DATA
  Measured Link Clock (MHz)    122.893
  Reported Link Clock (MHz)    122.880
  Measured Device Clock (MHz)  122.893
  Reported Device Clock (MHz)  122.880
  Desired Device Clock (MHz)   122.880
  Lane rate (MHz)              4915.200
  Lane rate / 40 (MHz)         122.880
  LMFC rate (MHz)              7.680
  SYSREF captured              Yes
  SYSREF alignment error       No
  SYNC~                        deasserted

Regards,

Michael

0 jacobha
on Sep 19, 2023 6:10 AM in reply to mhennerich
Hi, thanks for the reply. I use zynqmp-zcu102-rev10-adrv9371-jesd204-fsm devicetree and only changed spi-max-frequency = <0xbebc20>; property of ad9371 node ( from 0x17d7840 to 0xbebc20).
I use adrv-dpd1 board, in ADRV-DPD1-PCBZ-UG-1238.pdf document on page 8: "Lit LEDs indicate that the correct reference clock is provided and the phase locked loops (PLLs) in the AD9528 are locked. The Status 0 LED (PLL1 lock) ..." for this reason I said pll locked in previous answer but you're correct my iio_info is:

I connect 30.72MHz reference clock (+5 dbm) to board. (The only thing that I don't know if it is important or not is that VADJ_FMC led in zcu102 is turned off but J94 test point in zcu102 has correct voltage level)
Cancel
Up 0 Down

Reply

Verify Answer

Cancel
0 mhennerich

on Sep 19, 2023 7:40 AM in reply to jacobha
To be honest I'm not familiar with the adrv-dpd1 HW nor did I know that this HW is compatible with the ADRV9375/PCBZ FMC card project.

The iio info shows clearly that the reference clock is missing and the PLL1 is unlocked.

In general the FMC_VADJ led should be lit. If it isn't - that means that there is no proper FRU eeprom on the adrv-dpd1 or that the vadj voltage specified in there exceeds 1.8V.

The ZCU102 system controller reads this eeprom and then programs/enabled vadj accordingly.

It this HW works without vadj supplied by the ZCU102, this concerns me...

Also did you actually check schematics, etc. for electrical compatibility?

-Michael
Cancel
Up 0 Down

Reply

Verify Answer

Cancel
0 jacobha
on Sep 19, 2023 8:01 AM in reply to mhennerich
frudump output for eeprom in adrv-dpd1:

and J94 testpoint in zcu102 has 1.8v. I checked schematic, adrv-ddp1 has an additional encoder, which I have added right hdl code to hdl project for driving it ( ADRV-DPD1-PCBZ-UG-1238.pdf on page 19: Table 4. SPI Encoding Codes) and there is some minor differences like ad9371_gpio_08 to ad9371_gpio_18 must be removed from hdl design, I have done it. "G36 G37" FMC pin is reserved for another things and i use G6 , G7 for sysref_p and sysref_n pin. I attached system_top.v and system_constr.xdc files.2678.files.zip
Cancel
Up 0 Down

Reply

Verify Answer

Cancel

Electronic Design Services - PartnerZone

Products Mentioned

ad9375 + zcu102