ADRV9371 + ZCU102 reference design port to custom board: RX, TX and RXObs Clocks not working

Question

Hello, we are currently porting the ADRV9371 reference design for ZCU102 to a custom board (Trenz TEBF0808 +TE0808 w/ Zynq MPSoC) and we're having some issues booting the adrv9371 drivers on PetaLinux correctly - the RX, TX and RXObs Clock generators are not generating any clock and thus the JESD link creation procedure running at kernel initialization gets stuck on the "Link enable" phase. We started by adapting the hardware reference design (generated my through the HDL scripts https://github.com/analogdevicesinc/hdl for ZCU102) to the trenz board which basicly equated to changing the system constraints and pin mapping - all the address space and PL remained the same. Afterwards we used the produced .xsa file as hardware platform for a Baremetal test - we used the no-OS Vitis application https://github.com/analogdevicesinc/no-OS/tree/master/projects/ad9371 with no alterations aside from using a modified FSBL to configure some board clocks and worked flawlessly. The next step was the Petalinux project creation (v2021_R1), which involved adapting the device tree: We first followed the instructions laid out on the meta-adi github https://github.com/analogdevicesinc/meta-adi/blob/master/meta-adi-xilinx/README.md ; On the echo " KERNEL_DTB= \" ${dts_to_use} \" " >> project-spec/meta-user/conf/petalinuxbsp.conf step we used zynqmp-zcu102-rev10-adrv9371-jesd204-fsm and to make sure no ZCU102 specific dependencies were included we modified the meta-adi-xilinx/recipe-bsp/device-tree/device-tree.bbappend file in order to rearranje the includes present on system-top.dts, making sure for example the #include "zynqmp-zcu102-rev1.0.dts" include was not present but zynqMP ones that were called within it were (while respecting the final node order). In other words all the required ADRV9371 and zynqMP nodes are present on the final .dts file leaving out the zcu102 specifc ones, such as i2c mux ones. Also no Trenz specifc nodes were added. We used the same FSBL file as we did in the baremetal test. This is the produced .dtb decompiled to .dts file: /dts-v1/; / { compatible = "xlnx,zynqmp"; #address-cells = <0x02>; #size-cells = <0x02>; amba_pl@0 { #address-cells = <0x02>; #size-cells = <0x02>; compatible = "simple-bus"; ranges; phandle = <0x28>; misc_clk_0 { #clock-cells = <0x00>; clock-frequency = <0x5f5e100>; compatible = "fixed-clock"; phandle = <0x29>; }; }; cpus { #address-cells = <0x01>; #size-cells = <0x00>; cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <0x01>; reg = <0x00>; cpu-idle-states = <0x02>; clocks = <0x03 0x0a>; phandle = <0x2a>; }; cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x01>; operating-points-v2 = <0x01>; cpu-idle-states = <0x02>; phandle = <0x2b>; }; cpu@2 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x02>; operating-points-v2 = <0x01>; cpu-idle-states = <0x02>; phandle = <0x2c>; }; cpu@3 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x03>; operating-points-v2 = <0x01>; cpu-idle-states = <0x02>; phandle = <0x2d>; }; idle-states { entry-method = "psci"; cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <0x12c>; exit-latency-us = <0x258>; min-residency-us = <0x2710>; phandle = <0x02>; }; }; }; cpu-opp-table { compatible = "operating-points-v2"; opp-shared; phandle = <0x01>; opp00 { opp-hz = <0x00 0x47868bf4>; opp-microvolt = <0xf4240>; clock-latency-ns = <0x7a120>; }; opp01 { opp-hz = <0x00 0x23c345fa>; opp-microvolt = <0xf4240>; clock-latency-ns = <0x7a120>; }; opp02 { opp-hz = <0x00 0x17d783fc>; opp-microvolt = <0xf4240>; clock-latency-ns = <0x7a120>; }; opp03 { opp-hz = <0x00 0x11e1a2fd>; opp-microvolt = <0xf4240>; clock-latency-ns = <0x7a120>; }; }; zynqmp_ipi { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <0x04>; interrupts = <0x00 0x23 0x04>; xlnx,ipi-id = <0x00>; #address-cells = <0x02>; #size-cells = <0x02>; ranges; phandle = <0x2e>; mailbox@ff990400 { u-boot,dm-pre-reloc; reg = <0x00 0xff9905c0 0x00 0x20 0x00 0xff9905e0 0x00 0x20 0x00 0xff990e80 0x00 0x20 0x00 0xff990ea0 0x00 0x20>; reg-names = "local_request_region\0local_response_region\0remote_request_region\0remote_response_region"; #mbox-cells = <0x01>; xlnx,ipi-id = <0x04>; phandle = <0x05>; }; }; dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; phandle = <0x2f>; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <0x04>; interrupts = <0x00 0x8f 0x04 0x00 0x90 0x04 0x00 0x91 0x04 0x00 0x92 0x04>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; firmware { zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <0x01>; phandle = <0x0c>; zynqmp-power { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-power"; interrupt-parent = <0x04>; interrupts = <0x00 0x23 0x04>; mboxes = <0x05 0x00 0x05 0x01>; mbox-names = "tx\0rx"; phandle = <0x30>; }; nvmem_firmware { compatible = "xlnx,zynqmp-nvmem-fw"; #address-cells = <0x01>; #size-cells = <0x01>; soc_revision@0 { reg = <0x00 0x04>; phandle = <0x11>; }; efuse_dna@c { reg = <0x0c 0x0c>; phandle = <0x31>; }; efuse_usr0@20 { reg = <0x20 0x04>; phandle = <0x32>; }; efuse_usr1@24 { reg = <0x24 0x04>; phandle = <0x33>; }; efuse_usr2@28 { reg = <0x28 0x04>; phandle = <0x34>; }; efuse_usr3@2c { reg = <0x2c 0x04>; phandle = <0x35>; }; efuse_usr4@30 { reg = <0x30 0x04>; phandle = <0x36>; }; efuse_usr5@34 { reg = <0x34 0x04>; phandle = <0x37>; }; efuse_usr6@38 { reg = <0x38 0x04>; phandle = <0x38>; }; efuse_usr7@3c { reg = <0x3c 0x04>; phandle = <0x39>; }; efuse_miscusr@40 { reg = <0x40 0x04>; phandle = <0x3a>; }; efuse_chash@50 { reg = <0x50 0x04>; phandle = <0x3b>; }; efuse_pufmisc@54 { reg = <0x54 0x04>; phandle = <0x3c>; }; efuse_sec@58 { reg = <0x58 0x04>; phandle = <0x3d>; }; efuse_spkid@5c { reg = <0x5c 0x04>; phandle = <0x3e>; }; efuse_ppk0hash@a0 { reg = <0xa0 0x30>; phandle = <0x3f>; }; efuse_ppk1hash@d0 { reg = <0xd0 0x30>; phandle = <0x40>; }; }; pcap { compatible = "xlnx,zynqmp-pcap-fpga"; clock-names = "ref_clk"; clocks = <0x03 0x29>; phandle = <0x0b>; }; zynqmp-aes { compatible = "xlnx,zynqmp-aes"; phandle = <0x41>; }; reset-controller { compatible = "xlnx,zynqmp-reset"; #reset-cells = <0x01>; phandle = <0x10>; }; pinctrl { compatible = "xlnx,zynqmp-pinctrl"; status = "disabled"; phandle = <0x42>; }; sha384 { compatible = "xlnx,zynqmp-keccak-384"; phandle = <0x43>; }; zynqmp-rsa { compatible = "xlnx,zynqmp-rsa"; phandle = <0x44>; }; gpio { compatible = "xlnx,zynqmp-gpio-modepin"; gpio-controller; #gpio-cells = <0x02>; phandle = <0x18>; }; clock-controller { u-boot,dm-pre-reloc; #clock-cells = <0x01>; compatible = "xlnx,zynqmp-clk"; clocks = <0x06 0x07 0x08 0x09 0x0a>; clock-names = "pss_ref_clk\0video_clk\0pss_alt_ref_clk\0aux_ref_clk\0gt_crx_ref_clk"; phandle = <0x03>; }; }; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <0x04>; interrupts = <0x01 0x0d 0xf08 0x01 0x0e 0xf08 0x01 0x0b 0xf08 0x01 0x0a 0xf08>; }; edac { compatible = "arm,cortex-a53-edac"; }; fpga-full { compatible = "fpga-region"; fpga-mgr = <0x0b>; #address-cells = <0x02>; #size-cells = <0x02>; ranges; phandle = <0x45>; }; smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x00 0xfd800000 0x00 0x20000>; #iommu-cells = <0x01>; status = "disabled"; #global-interrupts = <0x01>; interrupt-parent = <0x04>; interrupts = <0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04>; phandle = <0x0d>; }; axi { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <0x02>; #size-cells = <0x02>; ranges; phandle = <0x46>; can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk\0pclk"; reg = <0x00 0xff060000 0x00 0x1000>; interrupts = <0x00 0x17 0x04>; interrupt-parent = <0x04>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <0x0c 0x2f>; clocks = <0x03 0x3f 0x03 0x1f>; phandle = <0x47>; }; can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk\0pclk"; reg = <0x00 0xff070000 0x00 0x1000>; interrupts = <0x00 0x18 0x04>; interrupt-parent = <0x04>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <0x0c 0x30>; clocks = <0x03 0x40 0x03 0x1f>; phandle = <0x48>; }; cci@fd6e0000 { compatible = "arm,cci-400"; status = "disabled"; reg = <0x00 0xfd6e0000 0x00 0x9000>; ranges = <0x00 0x00 0xfd6e0000 0x10000>; #address-cells = <0x01>; #size-cells = <0x01>; phandle = <0x49>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <0x04>; interrupts = <0x00 0x7b 0x04 0x00 0x7b 0x04 0x00 0x7b 0x04 0x00 0x7b 0x04 0x00 0x7b 0x04>; }; }; dma@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x00 0xfd500000 0x00 0x1000>; interrupt-parent = <0x04>; interrupts = <0x00 0x7c 0x04>; clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x80>; #stream-id-cells = <0x01>; iommus = <0x0d 0x14e8>; power-domains = <0x0c 0x2a>; clocks = <0x03 0x13 0x03 0x1f>; phandle = <0x4a>; }; dma@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x00 0xfd510000 0x00 0x1000>; interrupt-parent = <0x04>; interrupts = <0x00 0x7d 0x04>; clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x80>; #stream-id-cells = <0x01>; iommus = <0x0d 0x14e9>; power-domains = <0x0c 0x2a>; clocks = <0x03 0x13 0x03 0x1f>; phandle = <0x4b>; }; dma@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x00 0xfd520000 0x00 0x1000>; interrupt-parent = <0x04>; interrupts = <0x00 0x7e 0x04>; clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x80>; #stream-id-cells = <0x01>; iommus = <0x0d 0x14ea>; power-domains = <0x0c 0x2a>; clocks = <0x03 0x13 0x03 0x1f>; phandle = <0x4c>; }; dma@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x00 0xfd530000 0x00 0x1000>; interrupt-parent = <0x04>; interrupts = <0x00 0x7f 0x04>; clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x80>; #stream-id-cells = <0x01>; iommus = <0x0d 0x14eb>; power-domains = <0x0c 0x2a>; clocks = <0x03 0x13 0x03 0x1f>; phandle = <0x4d>; }; dma@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x00 0xfd540000 0x00 0x1000>; interrupt-parent = <0x04>; interrupts = <0x00 0x80 0x04>; clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x80>; #stream-id-cells = <0x01>; iommus = <0x0d 0x14ec>; power-domains = <0x0c 0x2a>; clocks = <0x03 0x13 0x03 0x1f>; phandle = <0x4e>; }; dma@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x00 0xfd550000 0x00 0x1000>; interrupt-parent = <0x04>; interrupts = <0x00 0x81 0x04>; clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x80>; #stream-id-cells = <0x01>; iommus = <0x0d 0x14ed>; power-domains = <0x0c 0x2a>; clocks = <0x03 0x13 0x03 0x1f>; phandle = <0x4f>; }; dma@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x00 0xfd560000 0x00 0x1000>; interrupt-parent = <0x04>; interrupts = <0x00 0x82 0x04>; clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x80>; #stream-id-cells = <0x01>; iommus = <0x0d 0x14ee>; power-domains = <0x0c 0x2a>; clocks = <0x03 0x13 0x03 0x1f>; phandle = <0x50>; }; dma@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x00 0xfd570000 0x00 0x1000>; interrupt-parent = <0x04>; interrupts = <0x00 0x83 0x04>; clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x80>; #stream-id-cells = <0x01>; iommus = <0x0d 0x14ef>; power-domains = <0x0c 0x2a>; clocks = <0x03 0x13 0x03 0x1f>; phandle = <0x51>; }; interrupt-controller@f9010000 { compatible = "arm,gic-400"; #interrupt-cells = <0x03>; reg = <0x00 0xf9010000 0x00 0x10000 0x00 0xf9020000 0x00 0x20000 0x00 0xf9040000 0x00 0x20000 0x00 0xf9060000 0x00 0x20000>; interrupt-controller; interrupt-parent = <0x04>; interrupts = <0x01 0x09 0xf04>; phandle = <0x04>; }; gpu@fd4b0000 { status = "disabled"; compatible = "arm,mali-400\0arm,mali-utgard"; reg = <0x00 0xfd4b0000 0x00 0x10000>; interrupt-parent = <0x04>; interrupts = <0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04>; interrupt-names = "IRQGP\0IRQGPMMU\0IRQPP0\0IRQPPMMU0\0IRQPP1\0IRQPPMMU1"; clock-names = "gpu\0gpu_pp0\0gpu_pp1"; power-domains = <0x0c 0x3a>; clocks = <0x03 0x18 0x03 0x19 0x03 0x1a>; phandle = <0x52>; }; dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x00 0xffa80000 0x00 0x1000>; interrupt-parent = <0x04>; interrupts = <0x00 0x4d 0x04>; clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x40>; #stream-id-cells = <0x01>; power-domains = <0x0c 0x2b>; clocks = <0x03 0x44 0x03 0x1f>; phandle = <0x53>; }; dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x00 0xffa90000 0x00 0x1000>; interrupt-parent = <0x04>; interrupts = <0x00 0x4e 0x04>; clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x40>; #stream-id-cells = <0x01>; power-domains = <0x0c 0x2b>; clocks = <0x03 0x44 0x03 0x1f>; phandle = <0x54>; }; dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x00 0xffaa0000 0x00 0x1000>; interrupt-parent = <0x04>; interrupts = <0x00 0x4f 0x04>; clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x40>; #stream-id-cells = <0x01>; power-domains = <0x0c 0x2b>; clocks = <0x03 0x44 0x03 0x1f>; phandle = <0x55>; }; dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x00 0xffab0000 0x00 0x1000>; interrupt-parent = <0x04>; interrupts = <0x00 0x50 0x04>; clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x40>; #stream-id-cells = <0x01>; power-domains = <0x0c 0x2b>; clocks = <0x03 0x44 0x03 0x1f>; phandle = <0x56>; }; dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x00 0xffac0000 0x00 0x1000>; interrupt-parent = <0x04>; interrupts = <0x00 0x51 0x04>; clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x40>; #stream-id-cells = <0x01>; power-domains = <0x0c 0x2b>; clocks = <0x03 0x44 0x03 0x1f>; phandle = <0x57>; }; dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x00 0xffad0000 0x00 0x1000>; interrupt-parent = <0x04>; interrupts = <0x00 0x52 0x04>; clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x40>; #stream-id-cells = <0x01>; power-domains = <0x0c 0x2b>; clocks = <0x03 0x44 0x03 0x1f>; phandle = <0x58>; }; dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x00 0xffae0000 0x00 0x1000>; interrupt-parent = <0x04>; interrupts = <0x00 0x53 0x04>; clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x40>; #stream-id-cells = <0x01>; power-domains = <0x0c 0x2b>; clocks = <0x03 0x44 0x03 0x1f>; phandle = <0x59>; }; dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x00 0xffaf0000 0x00 0x1000>; interrupt-parent = <0x04>; interrupts = <0x00 0x54 0x04>; clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x40>; #stream-id-cells = <0x01>; power-domains = <0x0c 0x2b>; clocks = <0x03 0x44 0x03 0x1f>; phandle = <0x5a>; }; memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x00 0xfd070000 0x00 0x30000>; interrupt-parent = <0x04>; interrupts = <0x00 0x70 0x04>; phandle = <0x5b>; }; nand-controller@ff100000 { compatible = "xlnx,zynqmp-nand-controller\0arasan,nfc-v3p10"; status = "disabled"; reg = <0x00 0xff100000 0x00 0x1000>; clock-names = "controller\0bus"; interrupt-parent = <0x04>; interrupts = <0x00 0x0e 0x04>; #address-cells = <0x01>; #size-cells = <0x00>; #stream-id-cells = <0x01>; iommus = <0x0d 0x872>; power-domains = <0x0c 0x2c>; clocks = <0x03 0x3c 0x03 0x1f>; phandle = <0x5c>; }; ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem\0cdns,gem"; status = "disabled"; interrupt-parent = <0x04>; interrupts = <0x00 0x39 0x04 0x00 0x39 0x04>; reg = <0x00 0xff0b0000 0x00 0x1000>; clock-names = "pclk\0hclk\0tx_clk\0rx_clk\0tsu_clk"; #address-cells = <0x01>; #size-cells = <0x00>; #stream-id-cells = <0x01>; iommus = <0x0d 0x874>; power-domains = <0x0c 0x1d>; clocks = <0x03 0x1f 0x03 0x68 0x03 0x2d 0x03 0x31 0x03 0x2c>; phandle = <0x5d>; }; ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem\0cdns,gem"; status = "disabled"; interrupt-parent = <0x04>; interrupts = <0x00 0x3b 0x04 0x00 0x3b 0x04>; reg = <0x00 0xff0c0000 0x00 0x1000>; clock-names = "pclk\0hclk\0tx_clk\0rx_clk\0tsu_clk"; #address-cells = <0x01>; #size-cells = <0x00>; #stream-id-cells = <0x01>; iommus = <0x0d 0x875>; power-domains = <0x0c 0x1e>; clocks = <0x03 0x1f 0x03 0x69 0x03 0x2e 0x03 0x32 0x03 0x2c>; phandle = <0x5e>; }; ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem\0cdns,gem"; status = "disabled"; interrupt-parent = <0x04>; interrupts = <0x00 0x3d 0x04 0x00 0x3d 0x04>; reg = <0x00 0xff0d0000 0x00 0x1000>; clock-names = "pclk\0hclk\0tx_clk\0rx_clk\0tsu_clk"; #address-cells = <0x01>; #size-cells = <0x00>; #stream-id-cells = <0x01>; iommus = <0x0d 0x876>; power-domains = <0x0c 0x1f>; clocks = <0x03 0x1f 0x03 0x6a 0x03 0x2f 0x03 0x33 0x03 0x2c>; phandle = <0x5f>; }; ethernet@ff0e0000 { compatible = "cdns,zynqmp-gem\0cdns,gem"; status = "disabled"; interrupt-parent = <0x04>; interrupts = <0x00 0x3f 0x04 0x00 0x3f 0x04>; reg = <0x00 0xff0e0000 0x00 0x1000>; clock-names = "pclk\0hclk\0tx_clk\0rx_clk\0tsu_clk"; #address-cells = <0x01>; #size-cells = <0x00>; #stream-id-cells = <0x01>; iommus = <0x0d 0x877>; power-domains = <0x0c 0x20>; clocks = <0x03 0x1f 0x03 0x6b 0x03 0x30 0x03 0x34 0x03 0x2c>; phandle = <0x60>; }; gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x02>; gpio-controller; interrupt-parent = <0x04>; interrupts = <0x00 0x10 0x04>; interrupt-controller; #interrupt-cells = <0x02>; reg = <0x00 0xff0a0000 0x00 0x1000>; power-domains = <0x0c 0x2e>; clocks = <0x03 0x1f>; phandle = <0x12>; }; i2c@ff020000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <0x04>; interrupts = <0x00 0x11 0x04>; reg = <0x00 0xff020000 0x00 0x1000>; #address-cells = <0x01>; #size-cells = <0x00>; power-domains = <0x0c 0x25>; clocks = <0x03 0x3d>; phandle = <0x61>; }; i2c@ff030000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <0x04>; interrupts = <0x00 0x12 0x04>; reg = <0x00 0xff030000 0x00 0x1000>; #address-cells = <0x01>; #size-cells = <0x00>; power-domains = <0x0c 0x26>; clocks = <0x03 0x3e>; phandle = <0x62>; }; memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x00 0xff960000 0x00 0x1000>; interrupt-parent = <0x04>; interrupts = <0x00 0x0a 0x04>; phandle = <0x63>; }; perf-monitor@ffa00000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x00 0xffa00000 0x00 0x10000>; interrupts = <0x00 0x19 0x04>; interrupt-parent = <0x04>; xlnx,enable-profile = <0x00>; xlnx,enable-trace = <0x00>; xlnx,num-monitor-slots = <0x01>; xlnx,enable-event-count = <0x01>; xlnx,enable-event-log = <0x01>; xlnx,have-sampled-metric-cnt = <0x01>; xlnx,num-of-counters = <0x08>; xlnx,metric-count-width = <0x20>; xlnx,metrics-sample-count-width = <0x20>; xlnx,global-count-width = <0x20>; xlnx,metric-count-scale = <0x01>; clocks = <0x03 0x1f>; phandle = <0x64>; }; perf-monitor@fd0b0000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x00 0xfd0b0000 0x00 0x10000>; interrupts = <0x00 0x7b 0x04>; interrupt-parent = <0x04>; xlnx,enable-profile = <0x00>; xlnx,enable-trace = <0x00>; xlnx,num-monitor-slots = <0x06>; xlnx,enable-event-count = <0x01>; xlnx,enable-event-log = <0x00>; xlnx,have-sampled-metric-cnt = <0x01>; xlnx,num-of-counters = <0x0a>; xlnx,metric-count-width = <0x20>; xlnx,metrics-sample-count-width = <0x20>; xlnx,global-count-width = <0x20>; xlnx,metric-count-scale = <0x01>; clocks = <0x03 0x1c>; phandle = <0x65>; }; perf-monitor@fd490000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x00 0xfd490000 0x00 0x10000>; interrupts = <0x00 0x7b 0x04>; interrupt-parent = <0x04>; xlnx,enable-profile = <0x00>; xlnx,enable-trace = <0x00>; xlnx,num-monitor-slots = <0x01>; xlnx,enable-event-count = <0x01>; xlnx,enable-event-log = <0x00>; xlnx,have-sampled-metric-cnt = <0x01>; xlnx,num-of-counters = <0x08>; xlnx,metric-count-width = <0x20>; xlnx,metrics-sample-count-width = <0x20>; xlnx,global-count-width = <0x20>; xlnx,metric-count-scale = <0x01>; clocks = <0x03 0x1c>; phandle = <0x66>; }; perf-monitor@ffa10000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x00 0xffa10000 0x00 0x10000>; interrupts = <0x00 0x19 0x04>; interrupt-parent = <0x04>; xlnx,enable-profile = <0x00>; xlnx,enable-trace = <0x00>; xlnx,num-monitor-slots = <0x01>; xlnx,enable-event-count = <0x01>; xlnx,enable-event-log = <0x01>; xlnx,have-sampled-metric-cnt = <0x01>; xlnx,num-of-counters = <0x08>; xlnx,metric-count-width = <0x20>; xlnx,metrics-sample-count-width = <0x20>; xlnx,global-count-width = <0x20>; xlnx,metric-count-scale = <0x01>; clocks = <0x03 0x1f>; phandle = <0x67>; }; pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <0x03>; #size-cells = <0x02>; #interrupt-cells = <0x01>; msi-controller; device_type = "pci"; interrupt-parent = <0x04>; interrupts = <0x00 0x76 0x04 0x00 0x75 0x04 0x00 0x74 0x04 0x00 0x73 0x04 0x00 0x72 0x04>; interrupt-names = "misc\0dummy\0intx\0msi1\0msi0"; msi-parent = <0x0e>; reg = <0x00 0xfd0e0000 0x00 0x1000 0x00 0xfd480000 0x00 0x1000 0x80 0x00 0x00 0x1000000>; reg-names = "breg\0pcireg\0cfg"; ranges = <0x2000000 0x00 0xe0000000 0x00 0xe0000000 0x00 0x10000000 0x43000000 0x06 0x00 0x06 0x00 0x02 0x00>; interrupt-map-mask = <0x00 0x00 0x00 0x07>; bus-range = <0x00 0xff>; interrupt-map = <0x00 0x00 0x00 0x01 0x0f 0x01 0x00 0x00 0x00 0x02 0x0f 0x02 0x00 0x00 0x00 0x03 0x0f 0x03 0x00 0x00 0x00 0x04 0x0f 0x04>; #stream-id-cells = <0x01>; iommus = <0x0d 0x4d0>; power-domains = <0x0c 0x3b>; clocks = <0x03 0x17>; phandle = <0x0e>; legacy-interrupt-controller { interrupt-controller; #address-cells = <0x00>; #interrupt-cells = <0x01>; phandle = <0x0f>; }; }; spi@ff0f0000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk\0pclk"; interrupts = <0x00 0x0f 0x04>; interrupt-parent = <0x04>; num-cs = <0x01>; reg = <0x00 0xff0f0000 0x00 0x1000 0x00 0xc0000000 0x00 0x8000000>; #address-cells = <0x01>; #size-cells = <0x00>; #stream-id-cells = <0x01>; iommus = <0x0d 0x873>; power-domains = <0x0c 0x2d>; clocks = <0x03 0x35 0x03 0x1f>; phandle = <0x68>; }; phy@fd400000 { compatible = "xlnx,zynqmp-psgtr-v1.1"; status = "disabled"; reg = <0x00 0xfd400000 0x00 0x40000 0x00 0xfd3d0000 0x00 0x1000>; reg-names = "serdes\0siou"; #phy-cells = <0x04>; phandle = <0x69>; }; rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x00 0xffa60000 0x00 0x100>; interrupt-parent = <0x04>; interrupts = <0x00 0x1a 0x04 0x00 0x1b 0x04>; interrupt-names = "alarm\0sec"; calibration = <0x8000>; phandle = <0x6a>; }; ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x00 0xfd0c0000 0x00 0x2000>; interrupt-parent = <0x04>; interrupts = <0x00 0x85 0x04>; power-domains = <0x0c 0x1c>; resets = <0x10 0x10>; #stream-id-cells = <0x04>; clocks = <0x03 0x16>; phandle = <0x6b>; }; mmc@ff160000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a\0arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <0x04>; interrupts = <0x00 0x30 0x04>; reg = <0x00 0xff160000 0x00 0x1000>; clock-names = "clk_xin\0clk_ahb"; xlnx,device_id = <0x00>; #stream-id-cells = <0x01>; iommus = <0x0d 0x870>; power-domains = <0x0c 0x27>; nvmem-cells = <0x11>; nvmem-cell-names = "soc_revision"; #clock-cells = <0x01>; clock-output-names = "clk_out_sd0\0clk_in_sd0"; clocks = <0x03 0x36 0x03 0x1f>; phandle = <0x6c>; }; mmc@ff170000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a\0arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <0x04>; interrupts = <0x00 0x31 0x04>; reg = <0x00 0xff170000 0x00 0x1000>; clock-names = "clk_xin\0clk_ahb"; xlnx,device_id = <0x01>; #stream-id-cells = <0x01>; iommus = <0x0d 0x871>; power-domains = <0x0c 0x28>; nvmem-cells = <0x11>; nvmem-cell-names = "soc_revision"; #clock-cells = <0x01>; clock-output-names = "clk_out_sd1\0clk_in_sd1"; clocks = <0x03 0x37 0x03 0x1f>; phandle = <0x6d>; }; spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "okay"; interrupt-parent = <0x04>; interrupts = <0x00 0x13 0x04>; reg = <0x00 0xff040000 0x00 0x1000>; clock-names = "ref_clk\0pclk"; #address-cells = <0x01>; #size-cells = <0x00>; power-domains = <0x0c 0x23>; clocks = <0x03 0x3a 0x03 0x1f>; phandle = <0x6e>; ad9528-1@0 { compatible = "adi,ad9528"; reg = <0x00>; #address-cells = <0x01>; #size-cells = <0x00>; spi-max-frequency = <0x989680>; clock-output-names = "ad9528-1_out0\0ad9528-1_out1\0ad9528-1_out2\0ad9528-1_out3\0ad9528-1_out4\0ad9528-1_out5\0ad9528-1_out6\0ad9528-1_out7\0ad9528-1_out8\0ad9528-1_out9\0ad9528-1_out10\0ad9528-1_out11\0ad9528-1_out12\0ad9528-1_out13"; #clock-cells = <0x01>; adi,vcxo-freq = <0x7530000>; adi,refa-enable; adi,refa-diff-rcv-enable; adi,refa-r-div = <0x01>; adi,osc-in-cmos-neg-inp-enable; adi,pll1-feedback-div = <0x04>; adi,pll1-charge-pump-current-nA = <0x1388>; adi,pll2-vco-div-m1 = <0x03>; adi,pll2-n2-div = <0x0a>; adi,pll2-r1-div = <0x01>; adi,pll2-charge-pump-current-nA = <0xc4888>; adi,sysref-src = <0x02>; adi,sysref-pattern-mode = <0x00>; adi,sysref-k-div = <0x200>; adi,sysref-nshot-mode = <0x03>; adi,sysref-request-trigger-mode = <0x00>; adi,rpole2 = <0x00>; adi,rzero = <0x07>; adi,cpole1 = <0x02>; adi,status-mon-pin0-function-select = <0x01>; adi,status-mon-pin1-function-select = <0x07>; reset-gpios = <0x12 0x89 0x00>; jesd204-device; #jesd204-cells = <0x02>; jesd204-sysref-provider; adi,jesd204-max-sysref-frequency-hz = <0x1312d>; phandle = <0x16>; channel@13 { reg = <0x0d>; adi,extended-name = "DEV_CLK"; adi,driver-mode = <0x00>; adi,divider-phase = <0x00>; adi,channel-divider = <0x0a>; adi,signal-source = <0x00>; phandle = <0x6f>; }; channel@1 { reg = <0x01>; adi,extended-name = "FMC_CLK"; adi,driver-mode = <0x00>; adi,divider-phase = <0x00>; adi,channel-divider = <0x0a>; adi,signal-source = <0x00>; phandle = <0x70>; }; channel@12 { reg = <0x0c>; adi,extended-name = "DEV_SYSREF"; adi,driver-mode = <0x00>; adi,divider-phase = <0x00>; adi,channel-divider = <0x0a>; adi,signal-source = <0x02>; phandle = <0x71>; }; channel@3 { reg = <0x03>; adi,extended-name = "FMC_SYSREF"; adi,driver-mode = <0x00>; adi,divider-phase = <0x00>; adi,channel-divider = <0x0a>; adi,signal-source = <0x02>; phandle = <0x72>; }; }; ad9371-phy@1 { compatible = "adi,ad9371"; reg = <0x01>; spi-max-frequency = <0x17d7840>; clocks = <0x13 0x14 0x15 0x16 0x0d 0x16 0x01 0x16 0x0c 0x16 0x03>; clock-names = "jesd_rx_clk\0jesd_tx_clk\0jesd_rx_os_clk\0dev_clk\0fmc_clk\0sysref_dev_clk\0sysref_fmc_clk"; clock-output-names = "rx_sampl_clk\0rx_os_sampl_clk\0tx_sampl_clk"; #clock-cells = <0x01>; adi,clocks-clk-pll-vco-freq_khz = <0x960000>; adi,clocks-device-clock_khz = <0x1e000>; adi,clocks-clk-pll-hs-div = <0x04>; adi,clocks-clk-pll-vco-div = <0x02>; adi,jesd204-obs-framer-over-sample = <0x00>; adi,rx-profile-adc-div = <0x01>; adi,rx-profile-en-high-rej-dec5 = <0x01>; adi,rx-profile-iq-rate_khz = <0x1e000>; adi,rx-profile-rf-bandwidth_hz = <0x5f5e100>; adi,rx-profile-rhb1-decimation = <0x01>; adi,rx-profile-rx-bbf-3db-corner_khz = <0x186a0>; adi,rx-profile-rx-dec5-decimation = <0x05>; adi,rx-profile-rx-fir-decimation = <0x02>; adi,rx-profile-rx-fir-gain_db = <0xfffffffa>; adi,rx-profile-rx-fir-num-fir-coefs = <0x30>; adi,rx-profile-rx-fir-coefs = <0xfffbffe6 0x200033 0xffbdff8c 0x8c00d4 0xff04fe91 0x1ad0253 0xfd50fc5d 0x4300593 0xf98ef774 0xa340da8 0xed3ee259 0x25b87e3d 0x7e3d25b8 0xe259ed3e 0xda80a34 0xf774f98e 0x5930430 0xfc5dfd50 0x25301ad 0xfe91ff04 0xd4008c 0xff8cffbd 0x330020 0xffe6fffb>; adi,rx-profile-custom-adc-profile = <0x2160182 0xc90062 0x50001eb 0x6370117 0x51a0068 0x318001c 0x300027 0x1700bb>; adi,obs-profile-adc-div = <0x01>; adi,obs-profile-en-high-rej-dec5 = <0x01>; adi,obs-profile-iq-rate_khz = <0x3c000>; adi,obs-profile-rf-bandwidth_hz = <0xbebc200>; adi,obs-profile-rhb1-decimation = <0x01>; adi,obs-profile-rx-bbf-3db-corner_khz = <0x186a0>; adi,obs-profile-rx-dec5-decimation = <0x05>; adi,obs-profile-rx-fir-decimation = <0x01>; adi,obs-profile-rx-fir-gain_db = <0x06>; adi,obs-profile-rx-fir-num-fir-coefs = <0x18>; adi,obs-profile-rx-fir-coefs = <0xfedf0051 0xffe9ffaa 0xe5fe9e 0x18dff17 0xfd6f06a3 0xefb459e2 0xefb406a3 0xfd6fff17 0x18dfe9e 0xe5ffaa 0xffe90051 0xfedf0000>; adi,obs-profile-custom-adc-profile = <0x1c2015d 0xc90062 0x50002da 0x65a0332 0x5c402dc 0x3420014 0x290024 0x1800c8>; adi,obs-settings-custom-loopback-adc-profile = <0x2390171 0xc90062 0x5000123 0x6050095 0x528003a 0x3270022 0x300028 0x1700bd>; adi,tx-profile-dac-div = <0x01>; adi,tx-profile-iq-rate_khz = <0x3c000>; adi,tx-profile-primary-sig-bandwidth_hz = <0x47868c0>; adi,tx-profile-rf-bandwidth_hz = <0xbebc200>; adi,tx-profile-thb1-interpolation = <0x02>; adi,tx-profile-thb2-interpolation = <0x01>; adi,tx-profile-tx-bbf-3db-corner_khz = <0x186a0>; adi,tx-profile-tx-dac-3db-corner_khz = <0x2da78>; adi,tx-profile-tx-fir-interpolation = <0x01>; adi,tx-profile-tx-input-hb-interpolation = <0x01>; adi,tx-profile-tx-fir-gain_db = <0x06>; adi,tx-profile-tx-fir-num-fir-coefs = <0x10>; adi,tx-profile-tx-fir-coefs = <0x6fef2 0xcbff58 0xffac03d7 0xf36a5297 0xf36a03d7 0xffacff58 0xcbfef2 0x60000>; adi,sniffer-profile-adc-div = <0x01>; adi,sniffer-profile-en-high-rej-dec5 = <0x00>; adi,sniffer-profile-iq-rate_khz = <0x7800>; adi,sniffer-profile-rf-bandwidth_hz = <0x1312d00>; adi,sniffer-profile-rhb1-decimation = <0x02>; adi,sniffer-profile-rx-bbf-3db-corner_khz = <0x186a0>; adi,sniffer-profile-rx-dec5-decimation = <0x05>; adi,sniffer-profile-rx-fir-decimation = <0x04>; reset-gpios = <0x12 0x82 0x00>; test-gpios = <0x12 0x83 0x00>; sysref_req-gpios = <0x12 0x88 0x00>; rx2_enable-gpios = <0x12 0x84 0x00>; rx1_enable-gpios = <0x12 0x85 0x00>; tx2_enable-gpios = <0x12 0x86 0x00>; tx1_enable-gpios = <0x12 0x87 0x00>; adi,jesd204-deframer-eq-setting = <0x03>; jesd204-device; #jesd204-cells = <0x02>; jesd204-top-device = <0x00>; jesd204-link-ids = <0x00 0x01 0x02>; jesd204-inputs = <0x13 0x00 0x01 0x15 0x00 0x02 0x17 0x00 0x00>; phandle = <0x1f>; }; }; spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <0x04>; interrupts = <0x00 0x14 0x04>; reg = <0x00 0xff050000 0x00 0x1000>; clock-names = "ref_clk\0pclk"; #address-cells = <0x01>; #size-cells = <0x00>; power-domains = <0x0c 0x24>; clocks = <0x03 0x3b 0x03 0x1f>; phandle = <0x73>; }; timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <0x04>; interrupts = <0x00 0x24 0x04 0x00 0x25 0x04 0x00 0x26 0x04>; reg = <0x00 0xff110000 0x00 0x1000>; timer-width = <0x20>; power-domains = <0x0c 0x18>; clocks = <0x03 0x1f>; phandle = <0x74>; }; timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <0x04>; interrupts = <0x00 0x27 0x04 0x00 0x28 0x04 0x00 0x29 0x04>; reg = <0x00 0xff120000 0x00 0x1000>; timer-width = <0x20>; power-domains = <0x0c 0x19>; clocks = <0x03 0x1f>; phandle = <0x75>; }; timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <0x04>; interrupts = <0x00 0x2a 0x04 0x00 0x2b 0x04 0x00 0x2c 0x04>; reg = <0x00 0xff130000 0x00 0x1000>; timer-width = <0x20>; power-domains = <0x0c 0x1a>; clocks = <0x03 0x1f>; phandle = <0x76>; }; timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <0x04>; interrupts = <0x00 0x2d 0x04 0x00 0x2e 0x04 0x00 0x2f 0x04>; reg = <0x00 0xff140000 0x00 0x1000>; timer-width = <0x20>; power-domains = <0x0c 0x1b>; clocks = <0x03 0x1f>; phandle = <0x77>; }; serial@ff000000 { u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12\0xlnx,xuartps"; status = "disabled"; interrupt-parent = <0x04>; interrupts = <0x00 0x15 0x04>; reg = <0x00 0xff000000 0x00 0x1000>; clock-names = "uart_clk\0pclk"; power-domains = <0x0c 0x21>; clocks = <0x03 0x38 0x03 0x1f>; phandle = <0x78>; }; serial@ff010000 { u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12\0xlnx,xuartps"; status = "disabled"; interrupt-parent = <0x04>; interrupts = <0x00 0x16 0x04>; reg = <0x00 0xff010000 0x00 0x1000>; clock-names = "uart_clk\0pclk"; power-domains = <0x0c 0x22>; clocks = <0x03 0x39 0x03 0x1f>; phandle = <0x79>; }; usb0@ff9d0000 { #address-cells = <0x02>; #size-cells = <0x02>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x00 0xff9d0000 0x00 0x100>; clock-names = "bus_clk\0ref_clk"; power-domains = <0x0c 0x16>; resets = <0x10 0x3b 0x10 0x3d 0x10 0x3f>; reset-names = "usb_crst\0usb_hibrst\0usb_apbrst"; reset-gpio = <0x18 0x01 0x00>; ranges; nvmem-cells = <0x11>; nvmem-cell-names = "soc_revision"; clocks = <0x03 0x20 0x03 0x22>; phandle = <0x7a>; dwc3@fe200000 { compatible = "snps,dwc3"; status = "okay"; reg = <0x00 0xfe200000 0x00 0x40000>; interrupt-parent = <0x04>; interrupt-names = "dwc_usb3\0otg\0hiber"; interrupts = <0x00 0x41 0x04 0x00 0x45 0x04 0x00 0x4b 0x04>; #stream-id-cells = <0x01>; iommus = <0x0d 0x860>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; dr_mode = "otg"; phandle = <0x7b>; }; }; usb1@ff9e0000 { #address-cells = <0x02>; #size-cells = <0x02>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x00 0xff9e0000 0x00 0x100>; clock-names = "bus_clk\0ref_clk"; power-domains = <0x0c 0x17>; resets = <0x10 0x3c 0x10 0x3e 0x10 0x40>; reset-names = "usb_crst\0usb_hibrst\0usb_apbrst"; ranges; nvmem-cells = <0x11>; nvmem-cell-names = "soc_revision"; clocks = <0x03 0x21 0x03 0x22>; phandle = <0x7c>; dwc3@fe300000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x00 0xfe300000 0x00 0x40000>; interrupt-parent = <0x04>; interrupt-names = "dwc_usb3\0otg\0hiber"; interrupts = <0x00 0x46 0x04 0x00 0x4a 0x04 0x00 0x4c 0x04>; #stream-id-cells = <0x01>; iommus = <0x0d 0x861>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; phandle = <0x7d>; }; }; watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <0x04>; interrupts = <0x00 0x71 0x01>; reg = <0x00 0xfd4d0000 0x00 0x1000>; timeout-sec = <0x3c>; reset-on-timeout; clocks = <0x03 0x4b>; phandle = <0x7e>; }; watchdog@ff150000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <0x04>; interrupts = <0x00 0x34 0x01>; reg = <0x00 0xff150000 0x00 0x1000>; timeout-sec = <0x0a>; clocks = <0x03 0x70>; phandle = <0x7f>; }; ams@ffa50000 { compatible = "xlnx,zynqmp-ams"; status = "disabled"; interrupt-parent = <0x04>; interrupts = <0x00 0x38 0x04>; interrupt-names = "ams-irq"; reg = <0x00 0xffa50000 0x00 0x800>; reg-names = "ams-base"; #address-cells = <0x02>; #size-cells = <0x02>; #io-channel-cells = <0x01>; ranges; clocks = <0x03 0x46>; phandle = <0x80>; ams_ps@ffa50800 { compatible = "xlnx,zynqmp-ams-ps"; status = "disabled"; reg = <0x00 0xffa50800 0x00 0x400>; phandle = <0x81>; }; ams_pl@ffa50c00 { compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x00 0xffa50c00 0x00 0x400>; phandle = <0x82>; }; }; dma-controller@fd4c0000 { compatible = "xlnx,zynqmp-dpdma"; status = "disabled"; reg = <0x00 0xfd4c0000 0x00 0x1000>; interrupts = <0x00 0x7a 0x04>; interrupt-parent = <0x04>; clock-names = "axi_clk"; power-domains = <0x0c 0x29>; dma-channels = <0x06>; #stream-id-cells = <0x01>; iommus = <0x0d 0xce4>; #dma-cells = <0x01>; clocks = <0x03 0x14>; phandle = <0x19>; }; display@fd4a0000 { compatible = "xlnx,zynqmp-dpsub-1.7"; status = "disabled"; reg = <0x00 0xfd4a0000 0x00 0x1000 0x00 0xfd4aa000 0x00 0x1000 0x00 0xfd4ab000 0x00 0x1000 0x00 0xfd4ac000 0x00 0x1000>; reg-names = "dp\0blend\0av_buf\0aud"; interrupts = <0x00 0x77 0x04>; interrupt-parent = <0x04>; #stream-id-cells = <0x01>; iommus = <0x0d 0xce3>; clock-names = "dp_apb_clk\0dp_aud_clk\0dp_vtc_pixel_clk_in"; power-domains = <0x0c 0x29>; resets = <0x10 0x03>; dma-names = "vid0\0vid1\0vid2\0gfx0"; dmas = <0x19 0x00 0x19 0x01 0x19 0x02 0x19 0x03>; clocks = <0x1a 0x03 0x11 0x03 0x10>; phandle = <0x83>; i2c-bus { }; zynqmp_dp_snd_codec0 { compatible = "xlnx,dp-snd-codec"; clock-names = "aud_clk"; clocks = <0x03 0x11>; phandle = <0x1d>; }; zynqmp_dp_snd_pcm0 { compatible = "xlnx,dp-snd-pcm"; dmas = <0x19 0x04>; dma-names = "tx"; phandle = <0x1b>; }; zynqmp_dp_snd_pcm1 { compatible = "xlnx,dp-snd-pcm"; dmas = <0x19 0x05>; dma-names = "tx"; phandle = <0x1c>; }; zynqmp_dp_snd_card { compatible = "xlnx,dp-snd-card"; xlnx,dp-snd-pcm = <0x1b 0x1c>; xlnx,dp-snd-codec = <0x1d>; phandle = <0x84>; }; }; }; fclk0 { status = "okay"; compatible = "xlnx,fclk"; clocks = <0x03 0x47>; phandle = <0x85>; }; fclk1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <0x03 0x48>; phandle = <0x86>; }; fclk2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <0x03 0x49>; phandle = <0x87>; }; fclk3 { status = "okay"; compatible = "xlnx,fclk"; clocks = <0x03 0x4a>; phandle = <0x88>; }; pss_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <0x1fca055>; phandle = <0x06>; }; video_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <0x19bfcc0>; phandle = <0x07>; }; pss_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <0x00>; phandle = <0x08>; }; gt_crx_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <0x66ff300>; phandle = <0x0a>; }; aux_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <0x19bfcc0>; phandle = <0x09>; }; dp_aclk { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <0x5f5e100>; clock-accuracy = <0x64>; phandle = <0x1a>; }; chosen { bootargs = " earlycon console=ttyPS0,115200 clk_ignore_unused init_fatal_sh=1"; stdout-path = "serial0:115200n8"; }; aliases { ethernet0 = "/axi/ethernet@ff0e0000"; i2c0 = "/axi/i2c@ff020000"; serial0 = "/axi/serial@ff000000"; spi0 = "/axi/spi@ff0f0000"; spi1 = "/axi/spi@ff040000"; spi2 = "/axi/spi@ff050000"; }; memory { device_type = "memory"; reg = <0x00 0x00 0x00 0x7ff00000 0x08 0x00 0x00 0x80000000>; }; fpga-axi@0 { interrupt-parent = <0x04>; compatible = "simple-bus"; #address-cells = <0x01>; #size-cells = <0x01>; ranges = <0x00 0x00 0x00 0xffffffff>; phandle = <0x89>; dma@9c400000 { compatible = "adi,axi-dmac-1.00.a"; reg = <0x9c400000 0x10000>; #dma-cells = <0x01>; #clock-cells = <0x00>; interrupts = <0x00 0x6d 0x04>; clocks = <0x03 0x49>; phandle = <0x1e>; adi,channels { #size-cells = <0x00>; #address-cells = <0x01>; dma-channel@0 { reg = <0x00>; adi,source-bus-width = <0x40>; adi,source-bus-type = <0x02>; adi,destination-bus-width = <0x40>; adi,destination-bus-type = <0x00>; }; }; }; dma@9c440000 { compatible = "adi,axi-dmac-1.00.a"; reg = <0x9c440000 0x10000>; #dma-cells = <0x01>; #clock-cells = <0x00>; interrupts = <0x00 0x6b 0x04>; clocks = <0x03 0x49>; phandle = <0x20>; adi,channels { #size-cells = <0x00>; #address-cells = <0x01>; dma-channel@0 { reg = <0x00>; adi,source-bus-width = <0x40>; adi,source-bus-type = <0x02>; adi,destination-bus-width = <0x40>; adi,destination-bus-type = <0x00>; }; }; }; dma@9c420000 { compatible = "adi,axi-dmac-1.00.a"; reg = <0x9c420000 0x10000>; #dma-cells = <0x01>; #clock-cells = <0x00>; interrupts = <0x00 0x6c 0x04>; clocks = <0x03 0x49>; phandle = <0x21>; adi,channels { #size-cells = <0x00>; #address-cells = <0x01>; dma-channel@0 { reg = <0x00>; adi,source-bus-width = <0x40>; adi,source-bus-type = <0x00>; adi,destination-bus-width = <0x80>; adi,destination-bus-type = <0x01>; }; }; }; axi-ad9371-rx-hpc@84a00000 { compatible = "adi,axi-ad9371-rx-1.0"; reg = <0x84a00000 0x8000>; dmas = <0x1e 0x00>; dma-names = "rx"; spibus-connected = <0x1f>; adi,axi-decimation-core-available; decimation-gpios = <0x12 0x8b 0x00>; phandle = <0x8a>; }; axi-ad9371-rx-obs-hpc@84a08000 { compatible = "adi,axi-ad9371-obs-1.0"; reg = <0x84a08000 0x1000>; dmas = <0x20 0x00>; dma-names = "rx"; clocks = <0x1f 0x01>; clock-names = "sampl_clk"; phandle = <0x8b>; }; axi-ad9371-tx-hpc@84a04000 { compatible = "adi,axi-ad9371-tx-1.0"; reg = <0x84a04000 0x4000>; dmas = <0x21 0x00>; dma-names = "tx"; clocks = <0x1f 0x02>; clock-names = "sampl_clk"; spibus-connected = <0x1f>; adi,axi-pl-fifo-enable; adi,axi-interpolation-core-available; interpolation-gpios = <0x12 0x8c 0x00>; plddrbypass-gpios = <0x12 0x8a 0x00>; jesd204-device; #jesd204-cells = <0x02>; jesd204-inputs = <0x14 0x00 0x00>; phandle = <0x17>; }; axi-jesd204-rx@84aa0000 { compatible = "adi,axi-jesd204-rx-1.0"; reg = <0x84aa0000 0x1000>; interrupts = <0x00 0x6a 0x04>; clocks = <0x03 0x47 0x22 0x23 0x00>; clock-names = "s_axi_aclk\0device_clk\0lane_clk"; #clock-cells = <0x00>; clock-output-names = "jesd_rx_lane_clk"; adi,octets-per-frame = <0x04>; adi,frames-per-multiframe = <0x20>; jesd204-device; #jesd204-cells = <0x02>; jesd204-inputs = <0x23 0x00 0x01>; phandle = <0x13>; }; axi-jesd204-tx@84a90000 { compatible = "adi,axi-jesd204-tx-1.0"; reg = <0x84a90000 0x1000>; interrupts = <0x00 0x69 0x04>; clocks = <0x03 0x47 0x24 0x25 0x00>; clock-names = "s_axi_aclk\0device_clk\0lane_clk"; #clock-cells = <0x00>; clock-output-names = "jesd_tx_lane_clk"; adi,octets-per-frame = <0x02>; adi,frames-per-multiframe = <0x20>; adi,converter-resolution = <0x0e>; adi,bits-per-sample = <0x10>; adi,converters-per-device = <0x04>; adi,control-bits-per-sample = <0x02>; jesd204-device; #jesd204-cells = <0x02>; jesd204-inputs = <0x25 0x00 0x00>; phandle = <0x14>; }; axi-jesd204-rx-os@84ab0000 { compatible = "adi,axi-jesd204-rx-1.0"; reg = <0x84ab0000 0x1000>; interrupts = <0x00 0x68 0x04>; clocks = <0x03 0x47 0x26 0x27 0x00>; clock-names = "s_axi_aclk\0device_clk\0lane_clk"; #clock-cells = <0x00>; clock-output-names = "jesd_rx_os_lane_clk"; adi,octets-per-frame = <0x02>; adi,frames-per-multiframe = <0x20>; jesd204-device; #jesd204-cells = <0x02>; jesd204-inputs = <0x27 0x00 0x02>; phandle = <0x15>; }; axi-clkgen@83c00000 { compatible = "adi,axi-clkgen-2.00.a"; reg = <0x83c00000 0x10000>; #clock-cells = <0x00>; clocks = <0x03 0x47 0x16 0x01>; clock-names = "s_axi_aclk\0clkin1"; clock-output-names = "axi_tx_clkgen"; phandle = <0x24>; }; axi-clkgen@83c10000 { compatible = "adi,axi-clkgen-2.00.a"; reg = <0x83c10000 0x10000>; #clock-cells = <0x00>; clocks = <0x03 0x47 0x16 0x01>; clock-names = "s_axi_aclk\0clkin1"; clock-output-names = "axi_rx_clkgen"; phandle = <0x22>; }; axi-clkgen@83c20000 { compatible = "adi,axi-clkgen-2.00.a"; reg = <0x83c20000 0x10000>; #clock-cells = <0x00>; clocks = <0x03 0x47 0x16 0x01>; clock-names = "s_axi_aclk\0clkin1"; clock-output-names = "axi_rx_os_clkgen"; phandle = <0x26>; }; axi-adxcvr-rx@84a60000 { #address-cells = <0x01>; #size-cells = <0x00>; compatible = "adi,axi-adxcvr-1.0"; reg = <0x84a60000 0x1000>; clocks = <0x16 0x01>; clock-names = "conv"; #clock-cells = <0x01>; clock-output-names = "rx_gt_clk\0rx_out_clk"; adi,sys-clk-select = <0x00>; adi,out-clk-select = <0x03>; adi,use-lpm-enable; jesd204-device; #jesd204-cells = <0x02>; jesd204-inputs = <0x16 0x00 0x01>; phandle = <0x23>; }; axi-adxcvr-rx-os@84a50000 { #address-cells = <0x01>; #size-cells = <0x00>; compatible = "adi,axi-adxcvr-1.0"; reg = <0x84a50000 0x1000>; clocks = <0x16 0x01>; clock-names = "conv"; #clock-cells = <0x01>; clock-output-names = "rx_os_gt_clk\0rx_os_out_clk"; adi,sys-clk-select = <0x00>; adi,out-clk-select = <0x03>; adi,use-lpm-enable; jesd204-device; #jesd204-cells = <0x02>; jesd204-inputs = <0x16 0x00 0x02>; phandle = <0x27>; }; axi-adxcvr-tx@84a80000 { #address-cells = <0x01>; #size-cells = <0x00>; compatible = "adi,axi-adxcvr-1.0"; reg = <0x84a80000 0x1000>; clocks = <0x16 0x01>; clock-names = "conv"; #clock-cells = <0x01>; clock-output-names = "tx_gt_clk\0tx_out_clk"; adi,sys-clk-select = <0x03>; adi,out-clk-select = <0x03>; jesd204-device; #jesd204-cells = <0x02>; jesd204-inputs = <0x16 0x00 0x00>; phandle = <0x25>; }; axi-sysid-0@85000000 { compatible = "adi,axi-sysid-1.00.a"; reg = <0x85000000 0x10000>; phandle = <0x8c>; }; }; __symbols__ { amba_pl = "/amba_pl@0"; misc_clk_0 = "/amba_pl@0/misc_clk_0"; cpu0 = "/cpus/cpu@0"; cpu1 = "/cpus/cpu@1"; cpu2 = "/cpus/cpu@2"; cpu3 = "/cpus/cpu@3"; CPU_SLEEP_0 = "/cpus/idle-states/cpu-sleep-0"; cpu_opp_table = "/cpu-opp-table"; zynqmp_ipi = "/zynqmp_ipi"; ipi_mailbox_pmu1 = "/zynqmp_ipi/mailbox@ff990400"; dcc = "/dcc"; zynqmp_firmware = "/firmware/zynqmp-firmware"; zynqmp_power = "/firmware/zynqmp-firmware/zynqmp-power"; soc_revision = "/firmware/zynqmp-firmware/nvmem_firmware/soc_revision@0"; efuse_dna = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_dna@c"; efuse_usr0 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr0@20"; efuse_usr1 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr1@24"; efuse_usr2 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr2@28"; efuse_usr3 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr3@2c"; efuse_usr4 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr4@30"; efuse_usr5 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr5@34"; efuse_usr6 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr6@38"; efuse_usr7 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr7@3c"; efuse_miscusr = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_miscusr@40"; efuse_chash = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_chash@50"; efuse_pufmisc = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_pufmisc@54"; efuse_sec = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_sec@58"; efuse_spkid = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_spkid@5c"; efuse_ppk0hash = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_ppk0hash@a0"; efuse_ppk1hash = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_ppk1hash@d0"; zynqmp_pcap = "/firmware/zynqmp-firmware/pcap"; xlnx_aes = "/firmware/zynqmp-firmware/zynqmp-aes"; zynqmp_reset = "/firmware/zynqmp-firmware/reset-controller"; pinctrl0 = "/firmware/zynqmp-firmware/pinctrl"; xlnx_keccak_384 = "/firmware/zynqmp-firmware/sha384"; xlnx_rsa = "/firmware/zynqmp-firmware/zynqmp-rsa"; modepin_gpio = "/firmware/zynqmp-firmware/gpio"; zynqmp_clk = "/firmware/zynqmp-firmware/clock-controller"; fpga_full = "/fpga-full"; smmu = "/smmu@fd800000"; amba = "/axi"; can0 = "/axi/can@ff060000"; can1 = "/axi/can@ff070000"; cci = "/axi/cci@fd6e0000"; fpd_dma_chan1 = "/axi/dma@fd500000"; fpd_dma_chan2 = "/axi/dma@fd510000"; fpd_dma_chan3 = "/axi/dma@fd520000"; fpd_dma_chan4 = "/axi/dma@fd530000"; fpd_dma_chan5 = "/axi/dma@fd540000"; fpd_dma_chan6 = "/axi/dma@fd550000"; fpd_dma_chan7 = "/axi/dma@fd560000"; fpd_dma_chan8 = "/axi/dma@fd570000"; gic = "/axi/interrupt-controller@f9010000"; gpu = "/axi/gpu@fd4b0000"; lpd_dma_chan1 = "/axi/dma@ffa80000"; lpd_dma_chan2 = "/axi/dma@ffa90000"; lpd_dma_chan3 = "/axi/dma@ffaa0000"; lpd_dma_chan4 = "/axi/dma@ffab0000"; lpd_dma_chan5 = "/axi/dma@ffac0000"; lpd_dma_chan6 = "/axi/dma@ffad0000"; lpd_dma_chan7 = "/axi/dma@ffae0000"; lpd_dma_chan8 = "/axi/dma@ffaf0000"; mc = "/axi/memory-controller@fd070000"; nand0 = "/axi/nand-controller@ff100000"; gem0 = "/axi/ethernet@ff0b0000"; gem1 = "/axi/ethernet@ff0c0000"; gem2 = "/axi/ethernet@ff0d0000"; gem3 = "/axi/ethernet@ff0e0000"; gpio = "/axi/gpio@ff0a0000"; i2c0 = "/axi/i2c@ff020000"; i2c1 = "/axi/i2c@ff030000"; ocm = "/axi/memory-controller@ff960000"; perf_monitor_ocm = "/axi/perf-monitor@ffa00000"; perf_monitor_ddr = "/axi/perf-monitor@fd0b0000"; perf_monitor_cci = "/axi/perf-monitor@fd490000"; perf_monitor_lpd = "/axi/perf-monitor@ffa10000"; pcie = "/axi/pcie@fd0e0000"; pcie_intc = "/axi/pcie@fd0e0000/legacy-interrupt-controller"; qspi = "/axi/spi@ff0f0000"; psgtr = "/axi/phy@fd400000"; rtc = "/axi/rtc@ffa60000"; sata = "/axi/ahci@fd0c0000"; sdhci0 = "/axi/mmc@ff160000"; sdhci1 = "/axi/mmc@ff170000"; spi0 = "/axi/spi@ff040000"; clk0_ad9528 = "/axi/spi@ff040000/ad9528-1@0"; ad9528_0_c13 = "/axi/spi@ff040000/ad9528-1@0/channel@13"; ad9528_0_c1 = "/axi/spi@ff040000/ad9528-1@0/channel@1"; ad9528_0_c12 = "/axi/spi@ff040000/ad9528-1@0/channel@12"; ad9528_0_c3 = "/axi/spi@ff040000/ad9528-1@0/channel@3"; trx0_ad9371 = "/axi/spi@ff040000/ad9371-phy@1"; spi1 = "/axi/spi@ff050000"; ttc0 = "/axi/timer@ff110000"; ttc1 = "/axi/timer@ff120000"; ttc2 = "/axi/timer@ff130000"; ttc3 = "/axi/timer@ff140000"; uart0 = "/axi/serial@ff000000"; uart1 = "/axi/serial@ff010000"; usb0 = "/axi/usb0@ff9d0000"; dwc3_0 = "/axi/usb0@ff9d0000/dwc3@fe200000"; usb1 = "/axi/usb1@ff9e0000"; dwc3_1 = "/axi/usb1@ff9e0000/dwc3@fe300000"; watchdog0 = "/axi/watchdog@fd4d0000"; lpd_watchdog = "/axi/watchdog@ff150000"; xilinx_ams = "/axi/ams@ffa50000"; ams_ps = "/axi/ams@ffa50000/ams_ps@ffa50800"; ams_pl = "/axi/ams@ffa50000/ams_pl@ffa50c00"; zynqmp_dpdma = "/axi/dma-controller@fd4c0000"; zynqmp_dpsub = "/axi/display@fd4a0000"; zynqmp_dp_snd_codec0 = "/axi/display@fd4a0000/zynqmp_dp_snd_codec0"; zynqmp_dp_snd_pcm0 = "/axi/display@fd4a0000/zynqmp_dp_snd_pcm0"; zynqmp_dp_snd_pcm1 = "/axi/display@fd4a0000/zynqmp_dp_snd_pcm1"; zynqmp_dp_snd_card0 = "/axi/display@fd4a0000/zynqmp_dp_snd_card"; fclk0 = "/fclk0"; fclk1 = "/fclk1"; fclk2 = "/fclk2"; fclk3 = "/fclk3"; pss_ref_clk = "/pss_ref_clk"; video_clk = "/video_clk"; pss_alt_ref_clk = "/pss_alt_ref_clk"; gt_crx_ref_clk = "/gt_crx_ref_clk"; aux_ref_clk = "/aux_ref_clk"; dp_aclk = "/dp_aclk"; fpga_axi = "/fpga-axi@0"; rx_dma = "/fpga-axi@0/dma@9c400000"; rx_obs_dma = "/fpga-axi@0/dma@9c440000"; tx_dma = "/fpga-axi@0/dma@9c420000"; axi_ad9371_core_rx = "/fpga-axi@0/axi-ad9371-rx-hpc@84a00000"; axi_ad9371_core_rx_obs = "/fpga-axi@0/axi-ad9371-rx-obs-hpc@84a08000"; axi_ad9371_core_tx = "/fpga-axi@0/axi-ad9371-tx-hpc@84a04000"; axi_ad9371_rx_jesd = "/fpga-axi@0/axi-jesd204-rx@84aa0000"; axi_ad9371_tx_jesd = "/fpga-axi@0/axi-jesd204-tx@84a90000"; axi_ad9371_rx_os_jesd = "/fpga-axi@0/axi-jesd204-rx-os@84ab0000"; axi_tx_clkgen = "/fpga-axi@0/axi-clkgen@83c00000"; axi_rx_clkgen = "/fpga-axi@0/axi-clkgen@83c10000"; axi_rx_os_clkgen = "/fpga-axi@0/axi-clkgen@83c20000"; axi_ad9371_adxcvr_rx = "/fpga-axi@0/axi-adxcvr-rx@84a60000"; axi_ad9371_adxcvr_rx_os = "/fpga-axi@0/axi-adxcvr-rx-os@84a50000"; axi_ad9371_adxcvr_tx = "/fpga-axi@0/axi-adxcvr-tx@84a80000"; axi_sysid_0 = "/fpga-axi@0/axi-sysid-0@85000000"; }; }; When booting the system through SD-Card we had the following log, where we can see the jesd procedure not advancing after the JESD204[0:2] transition clocks_enable -> link_enable step: TE0808 TE_XFsbl_HookPsuInit_Custom Configure Carrier I2C Switch 0x77 Configure PLL: SI5345-B Si534x Init Registers Write. Si534x Init Complete. PLL Status Register 0xC:0x0, 0xE:0x0, 0xD:0x0, 0x11:0, 0xF:0.or calibration...256 us). Configure Carrier I2C Switch 0x73 Configure PLL: SI5338-x-B Si5338 Init Start. Si5338 Init Registers Write. Si5338 Init Complete. PLL Status Register 0xC:0x0, 0xE:0x0, 0xD:0x10, 0x11:0, 0xF:0.or calibration...256 us). USB Reset Complete PCIe Reset Complete -------------------------------------------------------------------------------- Xilinx Zynq MP First Stage Boot Loader Release 2021.1 Jul 15 2023 - 01:38:19 -------------------------------------------------------------------------------- TE0808 TE_XFsbl_BoardInit_Custom NOTICE: ATF running on XCZU9EG/silicon v4/RTL5.1 at 0xfffea000 NOTICE: BL31: v2.4(release):xlnx_rebase_v2.4_2021.1_update1 NOTICE: BL31: Built : 08:27:07, Apr 28 2021 U-Boot 2021.01 (Jun 01 2021 - 11:54:06 +0000) Board: Xilinx ZynqMP DRAM: 4 GiB PMUFW: v1.1 EL Level: EL2 Chip ID: zu9eg NAND: 0 MiB MMC: mmc@ff160000: 0, mmc@ff170000: 1 Loading Environment from FAT... unable to select a mode : -70 In: serial Out: serial Err: serial Bootmode: SD_MODE1 Reset reason: EXTERNAL Net: ZYNQ GEM: ff0e0000, mdio bus ff0e0000, phyaddr -1, interface rgmii-id Warning: ethernet@ff0e0000 (eth0) using random MAC address - 02:b9:c0:65:1a:c5 eth0: ethernet@ff0e0000 Hit any key to stop autoboot: 0 switch to partitions #0, OK mmc1 is current device Scanning mmc 1:1... Found U-Boot script /boot.scr 2594 bytes read in 13 ms (194.3 KiB/s) ## Executing script at 20000000 Trying to load boot images from mmc1 16332184 bytes read in 1068 ms (14.6 MiB/s) ## Loading kernel from FIT Image at 10000000 ... Using 'conf-system-top.dtb' configuration Trying 'kernel-1' kernel subimage Description: Linux kernel Created: 2023-02-06 12:44:01 UTC Type: Kernel Image Compression: gzip compressed Data Start: 0x10000104 Data Size: 11158276 Bytes = 10.6 MiB Architecture: AArch64 OS: Linux Load Address: 0x00080000 Entry Point: 0x00080000 Hash algo: sha256 Hash value: 4eaa6818cad8f57e787cd7afd25b1760969aafecb1c0fd288f6b656eea660c66 Verifying Hash Integrity ... sha256+ OK ## Loading ramdisk from FIT Image at 10000000 ... Using 'conf-system-top.dtb' configuration Trying 'ramdisk-1' ramdisk subimage Description: petalinux-initramfs-image Created: 2023-02-06 12:44:01 UTC Type: RAMDisk Image Compression: uncompressed Data Start: 0x10ab08bc Data Size: 5121890 Bytes = 4.9 MiB Architecture: AArch64 OS: Linux Load Address: unavailable Entry Point: unavailable Hash algo: sha256 Hash value: ba62fe02738995dd99e14eaa7884db12b204ca94d8a4ba8aaf6476d91df1b003 Verifying Hash Integrity ... sha256+ OK ## Loading fdt from FIT Image at 10000000 ... Using 'conf-system-top.dtb' configuration Trying 'fdt-system-top.dtb' fdt subimage Description: Flattened Device Tree blob Created: 2023-02-06 12:44:01 UTC Type: Flat Device Tree Compression: uncompressed Data Start: 0x10aa4518 Data Size: 49869 Bytes = 48.7 KiB Architecture: AArch64 Hash algo: sha256 Hash value: 5e49ef0f74a1b79e10adec4099252315cd19209940335133c0639cc83a5560b3 Verifying Hash Integrity ... sha256+ OK Booting using the fdt blob at 0x10aa4518 Uncompressing Kernel Image Loading Ramdisk to 7d82f000, end 7dd11762 ... OK Loading Device Tree to 000000007d81f000, end 000000007d82e2cc ... OK Starting kernel ... [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034] [ 0.000000] Linux version 5.10.0-xilinx-v2021.1 (oe-user@oe-host) (aarch64-xilinx-linux-gcc (GCC) 10.2.0, GNU ld (GNU Binutils) 2.35.1) #1 SMP Mon Feb 6 12:44:01 UTC 2023 [ 0.000000] Machine model: xlnx,zynqmp [ 0.000000] earlycon: cdns0 at MMIO 0x00000000ff000000 (options '115200n8') [ 0.000000] printk: bootconsole [cdns0] enabled [ 0.000000] efi: UEFI not found. [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader! [ 0.000000] cma: Reserved 256 MiB at 0x000000006d800000 [ 0.000000] Zone ranges: [ 0.000000] DMA [mem 0x0000000000000000-0x000000003fffffff] [ 0.000000] DMA32 [mem 0x0000000040000000-0x00000000ffffffff] [ 0.000000] Normal [mem 0x0000000100000000-0x000000087fffffff] [ 0.000000] Movable zone start for each node [ 0.000000] Early memory node ranges [ 0.000000] node 0: [mem 0x0000000000000000-0x000000007fefffff] [ 0.000000] node 0: [mem 0x0000000800000000-0x000000087fffffff] [ 0.000000] Zeroed struct page in unavailable ranges: 256 pages [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x000000087fffffff] [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv1.1 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. [ 0.000000] psci: SMC Calling Convention v1.2 [ 0.000000] percpu: Embedded 22 pages/cpu s50968 r8192 d30952 u90112 [ 0.000000] Detected VIPT I-cache on CPU0 [ 0.000000] CPU features: detected: ARM erratum 845719 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031940 [ 0.000000] Kernel command line: earlycon console=ttyPS0,115200 clk_ignore_unused init_fatal_sh=1 [ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear) [ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear) [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off [ 0.000000] software IO TLB: mapped [mem 0x000000003bfff000-0x000000003ffff000] (64MB) [ 0.000000] Memory: 3746584K/4193280K available (15936K kernel code, 1722K rwdata, 12040K rodata, 2624K init, 658K bss, 184552K reserved, 262144K cma-reserved) [ 0.000000] rcu: Hierarchical RCU implementation. [ 0.000000] rcu: RCU event tracing is enabled. [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4. [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4 [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 [ 0.000000] GIC: Adjusting CPU interface base to 0x00000000f902f000 [ 0.000000] GIC: Using split EOI/Deactivate mode [ 0.000000] random: get_random_bytes called from start_kernel+0x31c/0x524 with crng_init=0 [ 0.000000] arch_timer: cp15 timer(s) running at 33.33MHz (phys). [ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x7b00c47c0, max_idle_ns: 440795202120 ns [ 0.000003] sched_clock: 56 bits at 33MHz, resolution 30ns, wraps every 2199023255541ns [ 0.008307] Console: colour dummy device 80x25 [ 0.012395] Calibrating delay loop (skipped), value calculated using timer frequency.. 66.66 BogoMIPS (lpj=133333) [ 0.022668] pid_max: default: 32768 minimum: 301 [ 0.027412] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear) [ 0.034615] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear) [ 0.043348] rcu: Hierarchical SRCU implementation. [ 0.047331] EFI services will not be available. [ 0.051778] smp: Bringing up secondary CPUs ... [ 0.219167] Detected VIPT I-cache on CPU1 [ 0.219204] CPU1: Booted secondary processor 0x0000000001 [0x410fd034] [ 0.580784] Detected VIPT I-cache on CPU2 [ 0.580806] CPU2: Booted secondary processor 0x0000000002 [0x410fd034] [ 0.971869] Detected VIPT I-cache on CPU3 [ 0.971891] CPU3: Booted secondary processor 0x0000000003 [0x410fd034] [ 0.971938] smp: Brought up 1 node, 4 CPUs [ 1.001795] SMP: Total of 4 processors activated. [ 1.006467] CPU features: detected: 32-bit EL0 Support [ 1.011571] CPU features: detected: CRC32 instructions [ 1.016716] CPU: All CPU(s) started at EL2 [ 1.020749] alternatives: patching kernel code [ 1.026198] devtmpfs: initialized [ 1.032896] Registered cp15_barrier emulation handler [ 1.033461] Registered setend emulation handler [ 1.038057] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns [ 1.047649] futex hash table entries: 1024 (order: 4, 65536 bytes, linear) [ 1.060424] pinctrl core: initialized pinctrl subsystem [ 1.061055] NET: Registered protocol family 16 [ 1.065414] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations [ 1.071497] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations [ 1.079220] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations [ 1.087042] audit: initializing netlink subsys (disabled) [ 1.092498] audit: type=2000 audit(1.028:1): state=initialized audit_enabled=0 res=1 [ 1.100087] cpuidle: using governor menu [ 1.104019] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers. [ 1.110759] ASID allocator initialised with 65536 entries [ 1.135184] HugeTLB registered 1.00 GiB page size, pre-allocated 0 pages [ 1.136248] HugeTLB registered 32.0 MiB page size, pre-allocated 0 pages [ 1.142904] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages [ 1.149564] HugeTLB registered 64.0 KiB page size, pre-allocated 0 pages [ 2.121507] DRBG: Continuing without Jitter RNG [ 2.200923] raid6: neonx8 gen() 2354 MB/s [ 2.268972] raid6: neonx8 xor() 1753 MB/s [ 2.337035] raid6: neonx4 gen() 2404 MB/s [ 2.405092] raid6: neonx4 xor() 1719 MB/s [ 2.473149] raid6: neonx2 gen() 2280 MB/s [ 2.541205] raid6: neonx2 xor() 1578 MB/s [ 2.609266] raid6: neonx1 gen() 1948 MB/s [ 2.677324] raid6: neonx1 xor() 1339 MB/s [ 2.745389] raid6: int64x8 gen() 1578 MB/s [ 2.813440] raid6: int64x8 xor() 846 MB/s [ 2.881506] raid6: int64x4 gen() 1758 MB/s [ 2.949558] raid6: int64x4 xor() 896 MB/s [ 3.017623] raid6: int64x2 gen() 1533 MB/s [ 3.085677] raid6: int64x2 xor() 823 MB/s [ 3.153735] raid6: int64x1 gen() 1134 MB/s [ 3.221791] raid6: int64x1 xor() 567 MB/s [ 3.221828] raid6: using algorithm neonx4 gen() 2404 MB/s [ 3.225783] raid6: .... xor() 1719 MB/s, rmw enabled [ 3.230719] raid6: using neon recovery algorithm [ 3.235718] iommu: Default domain type: Translated [ 3.240347] SCSI subsystem initialized [ 3.244011] usbcore: registered new interface driver usbfs [ 3.249341] usbcore: registered new interface driver hub [ 3.254615] usbcore: registered new device driver usb [ 3.259735] mc: Linux media interface: v0.10 [ 3.263864] videodev: Linux video capture interface: v2.00 [ 3.269354] EDAC MC: Ver: 3.0.0 [ 3.272788] zynqmp-ipi-mbox mailbox@ff990400: Registered ZynqMP IPI mbox with TX/RX channels. [ 3.281244] jesd204: created con: id=0, topo=0, link=0, /axi/spi@ff040000/ad9528-1@0 <-> /fpga-axi@0/axi-adxcvr-tx@84a80000 [ 3.291973] jesd204: created con: id=1, topo=0, link=2, /axi/spi@ff040000/ad9528-1@0 <-> /fpga-axi@0/axi-adxcvr-rx-os@84a50000 [ 3.303303] jesd204: created con: id=2, topo=0, link=1, /axi/spi@ff040000/ad9528-1@0 <-> /fpga-axi@0/axi-adxcvr-rx@84a60000 [ 3.314373] jesd204: created con: id=3, topo=0, link=2, /fpga-axi@0/axi-adxcvr-rx-os@84a50000 <-> /fpga-axi@0/axi-jesd204-rx-os@84ab0000 [ 3.326571] jesd204: created con: id=4, topo=0, link=0, /fpga-axi@0/axi-adxcvr-tx@84a80000 <-> /fpga-axi@0/axi-jesd204-tx@84a90000 [ 3.338251] jesd204: created con: id=5, topo=0, link=1, /fpga-axi@0/axi-adxcvr-rx@84a60000 <-> /fpga-axi@0/axi-jesd204-rx@84aa0000 [ 3.349925] jesd204: created con: id=6, topo=0, link=0, /fpga-axi@0/axi-jesd204-tx@84a90000 <-> /fpga-axi@0/axi-ad9371-tx-hpc@84a04000 [ 3.361953] jesd204: created con: id=7, topo=0, link=1, /fpga-axi@0/axi-jesd204-rx@84aa0000 <-> /axi/spi@ff040000/ad9371-phy@1 [ 3.373281] jesd204: created con: id=8, topo=0, link=2, /fpga-axi@0/axi-jesd204-rx-os@84ab0000 <-> /axi/spi@ff040000/ad9371-phy@1 [ 3.384872] jesd204: created con: id=9, topo=0, link=0, /fpga-axi@0/axi-ad9371-tx-hpc@84a04000 <-> /axi/spi@ff040000/ad9371-phy@1 [ 3.396469] jesd204: /axi/spi@ff040000/ad9371-phy@1: JESD204[0:0] transition uninitialized -> initialized [ 3.405972] jesd204: /axi/spi@ff040000/ad9371-phy@1: JESD204[0:1] transition uninitialized -> initialized [ 3.415486] jesd204: /axi/spi@ff040000/ad9371-phy@1: JESD204[0:2] transition uninitialized -> initialized [ 3.424997] jesd204: found 9 devices and 1 topologies [ 3.430042] FPGA manager framework [ 3.433504] Advanced Linux Sound Architecture Driver Initialized. [ 3.439801] Bluetooth: Core ver 2.22 [ 3.443000] NET: Registered protocol family 31 [ 3.447402] Bluetooth: HCI device and connection manager initialized [ 3.453718] Bluetooth: HCI socket layer initialized [ 3.458561] Bluetooth: L2CAP socket layer initialized [ 3.463588] Bluetooth: SCO socket layer initialized [ 3.468728] clocksource: Switched to clocksource arch_sys_counter [ 3.474611] VFS: Disk quotas dquot_6.6.0 [ 3.478409] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes) [ 3.488980] NET: Registered protocol family 2 [ 3.489856] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear) [ 3.498049] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear) [ 3.506059] TCP bind hash table entries: 32768 (order: 7, 524288 bytes, linear) [ 3.513496] TCP: Hash tables configured (established 32768 bind 32768) [ 3.519693] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear) [ 3.526356] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear) [ 3.533525] NET: Registered protocol family 1 [ 3.538011] RPC: Registered named UNIX socket transport module. [ 3.543599] RPC: Registered udp transport module. [ 3.548263] RPC: Registered tcp transport module. [ 3.552931] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 3.559878] PCI: CLS 0 bytes, default 64 [ 3.563330] Trying to unpack rootfs image as initramfs... [ 3.784019] Freeing initrd memory: 5000K [ 3.784414] hw perfevents: no interrupt-affinity property for /pmu, guessing. [ 3.789577] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available [ 3.797956] Initialise system trusted keyrings [ 3.801645] workingset: timestamp_bits=46 max_order=20 bucket_order=0 [ 3.808565] NFS: Registering the id_resolver key type [ 3.812978] Key type id_resolver registered [ 3.817089] Key type id_legacy registered [ 3.821082] nfs4filelayout_init: NFSv4 File Layout Driver Registering... [ 3.827742] jffs2: version 2.2. (NAND) (SUMMARY) © 2001-2006 Red Hat, Inc. [ 3.834928] fuse: init (API version 7.32) [ 3.871629] NET: Registered protocol family 38 [ 3.871671] xor: measuring software checksum speed [ 3.878987] 8regs : 2593 MB/sec [ 3.882713] 32regs : 3071 MB/sec [ 3.887601] arm64_neon : 2612 MB/sec [ 3.888157] xor: using function: 32regs (3071 MB/sec) [ 3.893183] Key type asymmetric registered [ 3.897244] Asymmetric key parser 'x509' registered [ 3.902106] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 248) [ 3.909443] io scheduler mq-deadline registered [ 3.913938] io scheduler kyber registered [ 3.944064] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled [ 3.948190] cacheinfo: Unable to detect cache hierarchy for CPU 0 [ 3.954961] brd: module loaded [ 3.959080] loop: module loaded [ 3.959367] Registered mathworks_ip class [ 3.962894] libphy: Fixed MDIO Bus: probed [ 3.965970] tun: Universal TUN/TAP device driver, 1.6 [ 3.970114] CAN device driver interface [ 3.974553] usbcore: registered new interface driver asix [ 3.979242] usbcore: registered new interface driver ax88179_178a [ 3.985278] usbcore: registered new interface driver cdc_ether [ 3.991071] usbcore: registered new interface driver net1080 [ 3.996695] usbcore: registered new interface driver cdc_subset [ 4.002577] usbcore: registered new interface driver zaurus [ 4.008123] usbcore: registered new interface driver cdc_ncm [ 4.014449] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver [ 4.020207] ehci-pci: EHCI PCI platform driver [ 4.024981] usbcore: registered new interface driver uas [ 4.029922] usbcore: registered new interface driver usb-storage [ 4.035907] usbcore: registered new interface driver usbserial_generic [ 4.042361] usbserial: USB Serial support registered for generic [ 4.048336] usbcore: registered new interface driver ftdi_sio [ 4.054037] usbserial: USB Serial support registered for FTDI USB Serial Device [ 4.061310] usbcore: registered new interface driver upd78f0730 [ 4.067187] usbserial: USB Serial support registered for upd78f0730 [ 4.074720] rtc_zynqmp ffa60000.rtc: registered as rtc0 [ 4.078609] rtc_zynqmp ffa60000.rtc: setting system clock to 1970-01-01T00:00:06 UTC (6) [ 4.086682] i2c /dev entries driver [ 4.091751] usbcore: registered new interface driver uvcvideo [ 4.095807] USB Video Class driver (1.1.1) [ 4.100867] Bluetooth: HCI UART driver ver 2.3 [ 4.104279] Bluetooth: HCI UART protocol H4 registered [ 4.109388] Bluetooth: HCI UART protocol BCSP registered [ 4.114677] Bluetooth: HCI UART protocol LL registered [ 4.119766] Bluetooth: HCI UART protocol ATH3K registered [ 4.125139] Bluetooth: HCI UART protocol Three-wire (H5) registered [ 4.131391] Bluetooth: HCI UART protocol Intel registered [ 4.136735] Bluetooth: HCI UART protocol QCA registered [ 4.141932] usbcore: registered new interface driver bcm203x [ 4.147555] usbcore: registered new interface driver bpa10x [ 4.153090] usbcore: registered new interface driver bfusb [ 4.158541] usbcore: registered new interface driver btusb [ 4.164003] usbcore: registered new interface driver ath3k [ 4.169490] EDAC MC: ECC not enabled [ 4.173102] EDAC DEVICE0: Giving out device to module zynqmp-ocm-edac controller zynqmp_ocm: DEV ff960000.memory-controller (INTERRUPT) [ 4.185382] sdhci: Secure Digital Host Controller Interface driver [ 4.191215] sdhci: Copyright(c) Pierre Ossman [ 4.195540] sdhci-pltfm: SDHCI platform and OF driver helper [ 4.201521] ledtrig-cpu: registered to indicate activity on CPUs [ 4.207144] SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping .... [ 4.213569] zynqmp_firmware_probe Platform Management API v1.1 [ 4.219331] zynqmp_firmware_probe Trustzone version v1.0 [ 4.283805] zynqmp-aes firmware:zynqmp-firmware:zynqmp-aes: will run requests pump with realtime priority [ 4.300689] alg: No test for xilinx-keccak-384 (zynqmp-keccak-384) [ 4.301405] alg: No test for xilinx-zynqmp-rsa (zynqmp-rsa) [ 4.306905] usbcore: registered new interface driver usbhid [ 4.312301] usbhid: USB HID core driver [ 4.323382] axi_sysid 85000000.axi-sysid-0: AXI System ID core version (1.01.a) found [ 4.325726] axi_sysid 85000000.axi-sysid-0: system ID header version mismatch. Expected 2, Reported 0 [ 4.334750] axi_sysid: probe of 85000000.axi-sysid-0 failed with error -14 [ 4.341980] fpga_manager fpga0: Xilinx ZynqMP FPGA Manager registered [ 4.348426] usbcore: registered new interface driver snd-usb-audio [ 4.355707] pktgen: Packet Generator for packet performance testing. Version: 2.75 [ 4.362188] Initializing XFRM netlink socket [ 4.365933] NET: Registered protocol family 10 [ 4.370671] Segment Routing with IPv6 [ 4.374057] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver [ 4.380108] NET: Registered protocol family 17 [ 4.384218] NET: Registered protocol family 15 [ 4.388693] can: controller area network core [ 4.392970] NET: Registered protocol family 29 [ 4.397357] can: raw protocol [ 4.400290] can: broadcast manager protocol [ 4.404451] can: netlink gateway - max_hops=1 [ 4.408856] Bluetooth: RFCOMM TTY layer initialized [ 4.413626] Bluetooth: RFCOMM socket layer initialized [ 4.418733] Bluetooth: RFCOMM ver 1.11 [ 4.422443] Bluetooth: BNEP (Ethernet Emulation) ver 1.3 [ 4.427715] Bluetooth: BNEP filters: protocol multicast [ 4.432907] Bluetooth: BNEP socket layer initialized [ 4.437835] Bluetooth: HIDP (Human Interface Emulation) ver 1.2 [ 4.443719] Bluetooth: HIDP socket layer initialized [ 4.448777] 9pnet: Installing 9P2000 support [ 4.452912] NET: Registered protocol family 36 [ 4.457313] Key type dns_resolver registered [ 4.461709] registered taskstats version 1 [ 4.465609] Loading compiled-in X.509 certificates [ 4.470717] Btrfs loaded, crc32c=crc32c-generic [ 4.482935] ff000000.serial: ttyPS0 at MMIO 0xff000000 (irq = 56, base_baud = 6249999) is a xuartps [ 4.491953] printk: console [ttyPS0] enabled [ 4.491953] printk: console [ttyPS0] enabled [ 4.496247] printk: bootconsole [cdns0] disabled [ 4.496247] printk: bootconsole [cdns0] disabled [ 4.505516] of-fpga-region fpga-full: FPGA Region probed [ 4.515557] nwl-pcie fd0e0000.pcie: host bridge /axi/pcie@fd0e0000 ranges: [ 4.522449] nwl-pcie fd0e0000.pcie: MEM 0x00e0000000..0x00efffffff -> 0x00e0000000 [ 4.530449] nwl-pcie fd0e0000.pcie: MEM 0x0600000000..0x07ffffffff -> 0x0600000000 [ 4.538517] nwl-pcie fd0e0000.pcie: Link is DOWN [ 4.543278] nwl-pcie fd0e0000.pcie: PCI host bridge to bus 0000:00 [ 4.549456] pci_bus 0000:00: root bus resource [bus 00-ff] [ 4.554937] pci_bus 0000:00: root bus resource [mem 0xe0000000-0xefffffff] [ 4.561802] pci_bus 0000:00: root bus resource [mem 0x600000000-0x7ffffffff pref] [ 4.569298] pci 0000:00:00.0: [10ee:d021] type 01 class 0x060400 [ 4.575361] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot [ 4.583752] pci 0000:00:00.0: PCI bridge to [bus 01-0c] [ 4.590668] xilinx-zynqmp-dma fd500000.dma: ZynqMP DMA driver Probe success [ 4.597833] xilinx-zynqmp-dma fd510000.dma: ZynqMP DMA driver Probe success [ 4.604986] xilinx-zynqmp-dma fd520000.dma: ZynqMP DMA driver Probe success [ 4.612138] xilinx-zynqmp-dma fd530000.dma: ZynqMP DMA driver Probe success [ 4.619286] xilinx-zynqmp-dma fd540000.dma: ZynqMP DMA driver Probe success [ 4.626450] xilinx-zynqmp-dma fd550000.dma: ZynqMP DMA driver Probe success [ 4.633600] xilinx-zynqmp-dma fd560000.dma: ZynqMP DMA driver Probe success [ 4.640761] xilinx-zynqmp-dma fd570000.dma: ZynqMP DMA driver Probe success [ 4.647983] xilinx-zynqmp-dma ffa80000.dma: ZynqMP DMA driver Probe success [ 4.655143] xilinx-zynqmp-dma ffa90000.dma: ZynqMP DMA driver Probe success [ 4.662305] xilinx-zynqmp-dma ffaa0000.dma: ZynqMP DMA driver Probe success [ 4.669459] xilinx-zynqmp-dma ffab0000.dma: ZynqMP DMA driver Probe success [ 4.676609] xilinx-zynqmp-dma ffac0000.dma: ZynqMP DMA driver Probe success [ 4.683779] xilinx-zynqmp-dma ffad0000.dma: ZynqMP DMA driver Probe success [ 4.690933] xilinx-zynqmp-dma ffae0000.dma: ZynqMP DMA driver Probe success [ 4.698104] xilinx-zynqmp-dma ffaf0000.dma: ZynqMP DMA driver Probe success [ 4.705277] ahci-ceva fd0c0000.ahci: supply ahci not found, using dummy regulator [ 4.712820] ahci-ceva fd0c0000.ahci: supply phy not found, using dummy regulator [ 4.720235] ahci-ceva fd0c0000.ahci: supply target not found, using dummy regulator [ 4.728016] ahci-ceva fd0c0000.ahci: AHCI 0001.0301 32 slots 2 ports 6 Gbps 0x3 impl platform mode [ 4.736970] ahci-ceva fd0c0000.ahci: flags: 64bit ncq sntf pm clo only pmp fbs pio slum part ccc sds apst [ 4.746773] zynqmp_pll_disable() clock disable failed for dpll_int, ret = -13 [ 4.754733] scsi host0: ahci-ceva [ 4.758327] scsi host1: ahci-ceva [ 4.761746] ata1: SATA max UDMA/133 mmio [mem 0xfd0c0000-0xfd0c1fff] port 0x100 irq 51 [ 4.769657] ata2: SATA max UDMA/133 mmio [mem 0xfd0c0000-0xfd0c1fff] port 0x180 irq 51 [ 4.778562] ad9528 spi1.0: supply vcc not found, using dummy regulator [ 4.806214] jesd204: /axi/spi@ff040000/ad9528-1@0,jesd204:0,parent=spi1.0: Using as SYSREF provider [ 4.815485] ad9371 spi1.1: ad9371_probe : enter [ 4.824667] macb ff0e0000.ethernet: Not enabling partial store and forward [ 4.835508] libphy: MACB_mii_bus: probed [ 4.839471] macb ff0e0000.ethernet eth0: Cadence GEM rev 0x50070106 at 0xff0e0000 irq 37 (02:b9:c0:65:1a:c5) [ 4.849703] xilinx-axipmon ffa00000.perf-monitor: Probed Xilinx APM [ 4.856247] xilinx-axipmon fd0b0000.perf-monitor: Probed Xilinx APM [ 4.862757] xilinx-axipmon fd490000.perf-monitor: Probed Xilinx APM [ 4.869264] xilinx-axipmon ffa10000.perf-monitor: Probed Xilinx APM [ 4.878806] cdns-i2c ff020000.i2c: 400 kHz mmio ff020000 irq 39 [ 4.885164] cdns-wdt fd4d0000.watchdog: Xilinx Watchdog Timer with timeout 60s [ 4.892640] cdns-wdt ff150000.watchdog: Xilinx Watchdog Timer with timeout 10s [ 4.921984] cf_axi_adc 84a00000.axi-ad9371-rx-hpc: ADI AIM (10.01.b) at 0x84A00000 mapped to 0x(____ptrval____), probed ADC AD9371 as MASTER [ 4.932729] mmc0: SDHCI controller on ff160000.mmc [ff160000.mmc] using ADMA 64-bit [ 4.936818] mmc1: SDHCI controller on ff170000.mmc [ff170000.mmc] using ADMA 64-bit [ 4.953159] cf_axi_dds 84a04000.axi-ad9371-tx-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x84A04000 mapped to 0x(____ptrval____), probed DDS AD9371 [ 4.969188] axi_adxcvr 84a60000.axi-adxcvr-rx: AXI-ADXCVR-RX (17.05.a) using CPLL on GTH4 at 0x84A60000. Number of lanes: 2. [ 4.982388] axi_adxcvr 84a50000.axi-adxcvr-rx-os: AXI-ADXCVR-RX (17.05.a) using CPLL on GTH4 at 0x84A50000. Number of lanes: 2. [ 4.994827] axi_adxcvr 84a80000.axi-adxcvr-tx: AXI-ADXCVR-TX (17.05.a) using QPLL on GTH4 at 0x84A80000. Number of lanes: 4. [ 5.008806] axi-jesd204-rx 84aa0000.axi-jesd204-rx: AXI-JESD204-RX (1.07.a) at 0x84AA0000. Encoder 8b10b, width 4/4, lanes 2, jesd204-fsm. [ 5.016031] mmc0: new HS200 MMC card at address 0001 [ 5.021712] axi-jesd204-rx 84ab0000.axi-jesd204-rx-os: AXI-JESD204-RX (1.07.a) at 0x84AB0000. Encoder 8b10b, width 4/4, lanes 2, jesd204-fsm. [ 5.026553] mmcblk0: mmc0:0001 Q2J54A 3.59 GiB [ 5.029154] mmc1: error -110 whilst initialising SD card [ 5.039290] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition initialized -> probed [ 5.043578] mmcblk0boot0: mmc0:0001 Q2J54A partition 1 16.0 MiB [ 5.048705] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition initialized -> probed [ 5.059905] mmcblk0boot1: mmc0:0001 Q2J54A partition 2 16.0 MiB [ 5.065648] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition initialized -> probed [ 5.076772] mmcblk0rpmb: mmc0:0001 Q2J54A partition 3 512 KiB, chardev (245:0) [ 5.082587] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition probed -> idle [ 5.096409] ata2: SATA link down (SStatus 0 SControl 330) [ 5.100830] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition probed -> idle [ 5.100839] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition probed -> idle [ 5.111279] ata1: SATA link down (SStatus 0 SControl 330) [ 5.116657] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition idle -> device_init [ 5.153748] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition idle -> device_init [ 5.164614] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition idle -> device_init [ 5.175480] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition device_init -> link_init [ 5.176686] random: fast init done [ 5.186778] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition device_init -> link_init [ 5.201445] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition device_init -> link_init [ 5.212756] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_init -> link_supported [ 5.224317] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_init -> link_supported [ 5.235878] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_init -> link_supported [ 5.247717] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_supported -> link_pre_setup [ 5.259719] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_supported -> link_pre_setup [ 5.271713] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_supported -> link_pre_setup [ 5.283877] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_pre_setup -> clk_sync_stage1 [ 5.295956] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_pre_setup -> clk_sync_stage1 [ 5.308035] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_pre_setup -> clk_sync_stage1 [ 5.320121] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage1 -> clk_sync_stage2 [ 5.332287] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clk_sync_stage1 -> clk_sync_stage2 [ 5.344457] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clk_sync_stage1 -> clk_sync_stage2 [ 5.356633] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage3 [ 5.368796] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clk_sync_stage2 -> clk_sync_stage3 [ 5.380968] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage3 [ 5.395153] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage3 -> link_setup [ 5.406882] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clk_sync_stage3 -> link_setup [ 5.418618] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clk_sync_stage3 -> link_setup [ 6.148503] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_setup -> opt_setup_stage1 [ 6.160330] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_setup -> opt_setup_stage1 [ 6.172148] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_setup -> opt_setup_stage1 [ 11.272735] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage1 -> opt_setup_stage2 [ 11.285080] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage1 -> opt_setup_stage2 [ 11.297419] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage1 -> opt_setup_stage2 [ 11.309766] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage2 -> opt_setup_stage3 [ 11.322106] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage2 -> opt_setup_stage3 [ 11.334445] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage2 -> opt_setup_stage3 [ 11.346785] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage3 -> opt_setup_stage4 [ 11.359125] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage3 -> opt_setup_stage4 [ 11.371467] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage3 -> opt_setup_stage4 [ 11.383813] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage4 -> opt_setup_stage5 [ 11.396151] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage4 -> opt_setup_stage5 [ 11.408490] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage4 -> opt_setup_stage5 [ 11.421176] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage5 -> clocks_enable [ 11.433262] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage5 -> clocks_enable [ 11.445342] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage5 -> clocks_enable [ 11.463784] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clocks_enable -> link_enable [ 11.475430] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clocks_enable -> link_enable [ 11.487076] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clocks_enable -> link_enable [ 11.772729] axi-jesd204-tx 84a90000.axi-jesd204-tx: axi_jesd204_tx_jesd204_link_running: Link0 status failed (CGS) [ 11.783075] jesd204: /fpga-axi@0/axi-jesd204-tx@84a90000,jesd204:4,parent=84a90000.axi-jesd204-tx: JESD204[0:0] In link_running got error from cb: -1 [ 11.796457] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: Rolling back from 'link_enable', got error -1 [ 11.807502] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_enable -> link_running [ 11.819061] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_enable -> link_running [ 11.830621] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_enable -> link_running [ 11.842197] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_running -> link_enable [ 11.853754] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_running -> link_enable [ 11.865315] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_running -> link_enable [ 11.876883] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_enable -> clocks_enable [ 11.888526] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_enable -> clocks_enable [ 11.900178] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_enable -> clocks_enable [ 11.911830] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clocks_enable -> opt_setup_stage5 [ 11.923905] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clocks_enable -> opt_setup_stage5 [ 11.935988] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clocks_enable -> opt_setup_stage5 [ 11.948074] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage5 -> opt_setup_stage4 [ 11.960412] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage5 -> opt_setup_stage4 [ 11.972747] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage5 -> opt_setup_stage4 [ 11.985094] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage4 -> opt_setup_stage3 [ 11.997434] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage4 -> opt_setup_stage3 [ 12.009776] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage4 -> opt_setup_stage3 [ 12.022126] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage3 -> opt_setup_stage2 [ 12.034462] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage3 -> opt_setup_stage2 [ 12.046805] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage3 -> opt_setup_stage2 [ 12.059151] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage2 -> opt_setup_stage1 [ 12.071492] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage2 -> opt_setup_stage1 [ 12.083834] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage2 -> opt_setup_stage1 [ 12.096183] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage1 -> link_setup [ 12.108000] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage1 -> link_setup [ 12.119821] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage1 -> link_setup [ 12.131646] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_setup -> clk_sync_stage3 [ 12.143379] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_setup -> clk_sync_stage3 [ 12.155117] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_setup -> clk_sync_stage3 [ 12.166853] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clk_sync_stage3 -> clk_sync_stage2 [ 12.179019] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clk_sync_stage3 -> clk_sync_stage2 [ 12.191188] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage3 -> clk_sync_stage2 [ 12.203361] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage1 [ 12.215527] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clk_sync_stage2 -> clk_sync_stage1 [ 12.227696] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage1 [ 12.239870] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clk_sync_stage1 -> link_pre_setup [ 12.251949] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clk_sync_stage1 -> link_pre_setup [ 12.264031] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage1 -> link_pre_setup [ 12.276118] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_pre_setup -> link_supported [ 12.288112] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_pre_setup -> link_supported [ 12.300105] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_pre_setup -> link_supported [ 12.312105] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_supported -> link_init [ 12.323662] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_supported -> link_init [ 12.335224] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_supported -> link_init [ 12.346789] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_init -> device_init [ 12.358087] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_init -> device_init [ 12.369388] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_init -> device_init [ 12.380694] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition device_init -> idle [ 12.391556] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition device_init -> idle [ 12.402416] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition device_init -> idle [ 12.413292] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition idle -> idle [ 12.423552] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition idle -> idle [ 12.433811] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition idle -> idle [ 12.444075] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition idle -> device_init [ 12.454939] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition idle -> device_init [ 12.465806] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition idle -> device_init [ 12.476678] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition device_init -> link_init [ 12.487975] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition device_init -> link_init [ 12.499276] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition device_init -> link_init [ 12.510586] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_init -> link_supported [ 12.522148] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_init -> link_supported [ 12.533710] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_init -> link_supported [ 12.545502] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_supported -> link_pre_setup [ 12.557496] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_supported -> link_pre_setup [ 12.569489] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_supported -> link_pre_setup [ 12.581650] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_pre_setup -> clk_sync_stage1 [ 12.593735] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_pre_setup -> clk_sync_stage1 [ 12.605815] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_pre_setup -> clk_sync_stage1 [ 12.617902] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage1 -> clk_sync_stage2 [ 12.630067] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clk_sync_stage1 -> clk_sync_stage2 [ 12.642236] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clk_sync_stage1 -> clk_sync_stage2 [ 12.654411] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage3 [ 12.666575] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clk_sync_stage2 -> clk_sync_stage3 [ 12.678749] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage3 [ 12.692995] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage3 -> link_setup [ 12.704732] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clk_sync_stage3 -> link_setup [ 12.716467] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clk_sync_stage3 -> link_setup [ 13.476523] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_setup -> opt_setup_stage1 [ 13.488349] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_setup -> opt_setup_stage1 [ 13.500168] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_setup -> opt_setup_stage1 [ 17.136757] random: crng init done [ 18.600734] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage1 -> opt_setup_stage2 [ 18.613080] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage1 -> opt_setup_stage2 [ 18.625423] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage1 -> opt_setup_stage2 [ 18.637768] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage2 -> opt_setup_stage3 [ 18.650108] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage2 -> opt_setup_stage3 [ 18.662453] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage2 -> opt_setup_stage3 [ 18.674797] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage3 -> opt_setup_stage4 [ 18.687136] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage3 -> opt_setup_stage4 [ 18.699479] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage3 -> opt_setup_stage4 [ 18.711825] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage4 -> opt_setup_stage5 [ 18.724165] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage4 -> opt_setup_stage5 [ 18.736511] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage4 -> opt_setup_stage5 [ 18.749192] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage5 -> clocks_enable [ 18.761275] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage5 -> clocks_enable [ 18.773354] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage5 -> clocks_enable [ 18.791665] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clocks_enable -> link_enable [ 18.803312] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clocks_enable -> link_enable [ 18.814958] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clocks_enable -> link_enable [ 19.088729] axi-jesd204-rx 84ab0000.axi-jesd204-rx-os: axi_jesd204_rx_jesd204_link_running: Link2 status failed (CGS) [ 19.099335] jesd204: /fpga-axi@0/axi-jesd204-rx-os@84ab0000,jesd204:5,parent=84ab0000.axi-jesd204-rx-os: JESD204[0:2] In link_running got error from cb: -1 [ 19.113238] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: Rolling back from 'link_enable', got error -1 [ 19.124282] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_enable -> link_running [ 19.135839] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_enable -> link_running [ 19.147403] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_enable -> link_running [ 19.158971] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_running -> link_enable [ 19.170537] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_running -> link_enable [ 19.182095] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_running -> link_enable [ 19.193664] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_enable -> clocks_enable [ 19.205307] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_enable -> clocks_enable [ 19.216958] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_enable -> clocks_enable [ 19.228606] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clocks_enable -> opt_setup_stage5 [ 19.240684] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clocks_enable -> opt_setup_stage5 [ 19.252758] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clocks_enable -> opt_setup_stage5 [ 19.264836] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage5 -> opt_setup_stage4 [ 19.277176] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage5 -> opt_setup_stage4 [ 19.289519] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage5 -> opt_setup_stage4 [ 19.301865] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage4 -> opt_setup_stage3 [ 19.314205] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage4 -> opt_setup_stage3 [ 19.326548] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage4 -> opt_setup_stage3 [ 19.338894] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage3 -> opt_setup_stage2 [ 19.351237] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage3 -> opt_setup_stage2 [ 19.363577] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage3 -> opt_setup_stage2 [ 19.375923] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage2 -> opt_setup_stage1 [ 19.388263] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage2 -> opt_setup_stage1 [ 19.400605] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage2 -> opt_setup_stage1 [ 19.412954] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage1 -> link_setup [ 19.424771] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage1 -> link_setup [ 19.436593] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage1 -> link_setup [ 19.448417] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_setup -> clk_sync_stage3 [ 19.460151] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_setup -> clk_sync_stage3 [ 19.471886] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_setup -> clk_sync_stage3 [ 19.483628] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clk_sync_stage3 -> clk_sync_stage2 [ 19.495791] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clk_sync_stage3 -> clk_sync_stage2 [ 19.507960] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage3 -> clk_sync_stage2 [ 19.520132] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage1 [ 19.532298] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clk_sync_stage2 -> clk_sync_stage1 [ 19.544467] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage1 [ 19.556642] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clk_sync_stage1 -> link_pre_setup [ 19.568723] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clk_sync_stage1 -> link_pre_setup [ 19.580802] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage1 -> link_pre_setup [ 19.592888] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_pre_setup -> link_supported [ 19.604884] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_pre_setup -> link_supported [ 19.616877] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_pre_setup -> link_supported [ 19.628876] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_supported -> link_init [ 19.640435] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_supported -> link_init [ 19.651996] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_supported -> link_init [ 19.663561] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_init -> device_init [ 19.674859] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_init -> device_init [ 19.686160] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_init -> device_init [ 19.697465] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition device_init -> idle [ 19.708329] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition device_init -> idle [ 19.719196] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition device_init -> idle [ 19.730072] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition idle -> idle [ 19.740324] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition idle -> idle [ 19.750583] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition idle -> idle [ 19.760847] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition idle -> device_init [ 19.771710] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition idle -> device_init [ 19.782578] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition idle -> device_init [ 19.793449] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition device_init -> link_init [ 19.804747] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition device_init -> link_init [ 19.816047] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition device_init -> link_init [ 19.827356] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_init -> link_supported [ 19.838911] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_init -> link_supported [ 19.850472] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_init -> link_supported [ 19.862255] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_supported -> link_pre_setup [ 19.874251] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_supported -> link_pre_setup [ 19.886243] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_supported -> link_pre_setup [ 19.908766] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_pre_setup -> clk_sync_stage1 [ 19.920845] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_pre_setup -> clk_sync_stage1 [ 19.932925] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_pre_setup -> clk_sync_stage1 [ 19.945010] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage1 -> clk_sync_stage2 [ 19.957176] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clk_sync_stage1 -> clk_sync_stage2 [ 19.969348] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clk_sync_stage1 -> clk_sync_stage2 [ 19.981518] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage3 [ 19.993686] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clk_sync_stage2 -> clk_sync_stage3 [ 20.005854] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage3 [ 20.020080] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage3 -> link_setup [ 20.031819] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clk_sync_stage3 -> link_setup [ 20.043551] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clk_sync_stage3 -> link_setup [ 20.772487] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_setup -> opt_setup_stage1 [ 20.784308] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_setup -> opt_setup_stage1 [ 20.796125] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_setup -> opt_setup_stage1 [ 25.896735] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage1 -> opt_setup_stage2 [ 25.909082] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage1 -> opt_setup_stage2 [ 25.921425] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage1 -> opt_setup_stage2 [ 25.933769] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage2 -> opt_setup_stage3 [ 25.946109] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage2 -> opt_setup_stage3 [ 25.958450] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage2 -> opt_setup_stage3 [ 25.970797] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage3 -> opt_setup_stage4 [ 25.983136] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage3 -> opt_setup_stage4 [ 25.995480] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage3 -> opt_setup_stage4 [ 26.007826] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage4 -> opt_setup_stage5 [ 26.020165] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage4 -> opt_setup_stage5 [ 26.032511] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage4 -> opt_setup_stage5 [ 26.045190] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage5 -> clocks_enable [ 26.057275] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage5 -> clocks_enable [ 26.069354] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage5 -> clocks_enable [ 26.087789] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clocks_enable -> link_enable [ 26.099433] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clocks_enable -> link_enable [ 26.111079] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clocks_enable -> link_enable [ 26.396728] axi-jesd204-tx 84a90000.axi-jesd204-tx: axi_jesd204_tx_jesd204_link_running: Link0 status failed (CGS) [ 26.407078] jesd204: /fpga-axi@0/axi-jesd204-tx@84a90000,jesd204:4,parent=84a90000.axi-jesd204-tx: JESD204[0:0] In link_running got error from cb: -1 [ 26.420461] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: Rolling back from 'link_enable', got error -1 [ 26.431503] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_enable -> link_running [ 26.443065] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_enable -> link_running [ 26.454625] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_enable -> link_running [ 26.466199] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_running -> link_enable [ 26.477758] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_running -> link_enable [ 26.489319] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_running -> link_enable [ 26.500886] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_enable -> clocks_enable [ 26.512530] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_enable -> clocks_enable [ 26.524181] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_enable -> clocks_enable [ 26.535829] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clocks_enable -> opt_setup_stage5 [ 26.547910] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clocks_enable -> opt_setup_stage5 [ 26.559991] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clocks_enable -> opt_setup_stage5 [ 26.572077] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage5 -> opt_setup_stage4 [ 26.584417] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage5 -> opt_setup_stage4 [ 26.596760] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage5 -> opt_setup_stage4 [ 26.609106] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage4 -> opt_setup_stage3 [ 26.621445] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage4 -> opt_setup_stage3 [ 26.633781] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage4 -> opt_setup_stage3 [ 26.646130] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage3 -> opt_setup_stage2 [ 26.658466] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage3 -> opt_setup_stage2 [ 26.670809] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage3 -> opt_setup_stage2 [ 26.683155] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage2 -> opt_setup_stage1 [ 26.695495] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage2 -> opt_setup_stage1 [ 26.707837] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage2 -> opt_setup_stage1 [ 26.720186] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage1 -> link_setup [ 26.732004] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage1 -> link_setup [ 26.743824] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage1 -> link_setup [ 26.755640] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_setup -> clk_sync_stage3 [ 26.767375] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_setup -> clk_sync_stage3 [ 26.779113] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_setup -> clk_sync_stage3 [ 26.790848] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clk_sync_stage3 -> clk_sync_stage2 [ 26.803014] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clk_sync_stage3 -> clk_sync_stage2 [ 26.815184] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage3 -> clk_sync_stage2 [ 26.827356] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage1 [ 26.839522] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clk_sync_stage2 -> clk_sync_stage1 [ 26.851691] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage1 [ 26.863864] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clk_sync_stage1 -> link_pre_setup [ 26.875943] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clk_sync_stage1 -> link_pre_setup [ 26.888026] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage1 -> link_pre_setup [ 26.900112] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_pre_setup -> link_supported [ 26.912108] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_pre_setup -> link_supported [ 26.924103] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_pre_setup -> link_supported [ 26.936099] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_supported -> link_init [ 26.947658] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_supported -> link_init [ 26.959220] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_supported -> link_init [ 26.970783] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_init -> device_init [ 26.982083] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_init -> device_init [ 26.993382] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_init -> device_init [ 27.004678] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition device_init -> idle [ 27.015544] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition device_init -> idle [ 27.026410] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition device_init -> idle [ 27.037278] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition idle -> idle [ 27.047539] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition idle -> idle [ 27.057798] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition idle -> idle [ 27.068061] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition idle -> device_init [ 27.078924] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition idle -> device_init [ 27.089784] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition idle -> device_init [ 27.100655] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition device_init -> link_init [ 27.111952] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition device_init -> link_init [ 27.123246] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition device_init -> link_init [ 27.134553] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_init -> link_supported [ 27.146109] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_init -> link_supported [ 27.157669] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_init -> link_supported [ 27.169468] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_supported -> link_pre_setup [ 27.181466] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_supported -> link_pre_setup [ 27.193458] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_supported -> link_pre_setup [ 27.205622] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_pre_setup -> clk_sync_stage1 [ 27.217705] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_pre_setup -> clk_sync_stage1 [ 27.229784] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_pre_setup -> clk_sync_stage1 [ 27.241870] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage1 -> clk_sync_stage2 [ 27.254036] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clk_sync_stage1 -> clk_sync_stage2 [ 27.266204] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clk_sync_stage1 -> clk_sync_stage2 [ 27.278372] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage3 [ 27.290537] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clk_sync_stage2 -> clk_sync_stage3 [ 27.302709] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage3 [ 27.316945] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage3 -> link_setup [ 27.328675] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clk_sync_stage3 -> link_setup [ 27.340410] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clk_sync_stage3 -> link_setup [ 28.100523] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_setup -> opt_setup_stage1 [ 28.112344] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_setup -> opt_setup_stage1 [ 28.124164] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_setup -> opt_setup_stage1 [ 33.224735] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage1 -> opt_setup_stage2 [ 33.237077] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage1 -> opt_setup_stage2 [ 33.249418] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage1 -> opt_setup_stage2 [ 33.261764] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage2 -> opt_setup_stage3 [ 33.274104] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage2 -> opt_setup_stage3 [ 33.286449] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage2 -> opt_setup_stage3 [ 33.298793] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage3 -> opt_setup_stage4 [ 33.311132] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage3 -> opt_setup_stage4 [ 33.323474] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage3 -> opt_setup_stage4 [ 33.335820] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage4 -> opt_setup_stage5 [ 33.348160] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage4 -> opt_setup_stage5 [ 33.360507] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage4 -> opt_setup_stage5 [ 33.373188] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage5 -> clocks_enable [ 33.385270] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage5 -> clocks_enable [ 33.397349] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage5 -> clocks_enable [ 33.415770] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clocks_enable -> link_enable [ 33.427421] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clocks_enable -> link_enable [ 33.439066] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clocks_enable -> link_enable [ 33.724728] axi-jesd204-tx 84a90000.axi-jesd204-tx: axi_jesd204_tx_jesd204_link_running: Link0 status failed (CGS) [ 33.735074] jesd204: /fpga-axi@0/axi-jesd204-tx@84a90000,jesd204:4,parent=84a90000.axi-jesd204-tx: JESD204[0:0] In link_running got error from cb: -1 [ 33.748457] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: Rolling back from 'link_enable', got error -1 [ 33.759500] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_enable -> link_running [ 33.771061] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_enable -> link_running [ 33.782620] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_enable -> link_running [ 33.794193] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_running -> link_enable [ 33.805754] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_running -> link_enable [ 33.817314] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_running -> link_enable [ 33.828881] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_enable -> clocks_enable [ 33.840525] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_enable -> clocks_enable [ 33.852177] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_enable -> clocks_enable [ 33.863826] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clocks_enable -> opt_setup_stage5 [ 33.875904] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clocks_enable -> opt_setup_stage5 [ 33.887986] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clocks_enable -> opt_setup_stage5 [ 33.900072] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage5 -> opt_setup_stage4 [ 33.912413] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage5 -> opt_setup_stage4 [ 33.924759] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage5 -> opt_setup_stage4 [ 33.937101] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage4 -> opt_setup_stage3 [ 33.949442] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage4 -> opt_setup_stage3 [ 33.961784] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage4 -> opt_setup_stage3 [ 33.974134] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage3 -> opt_setup_stage2 [ 33.986470] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage3 -> opt_setup_stage2 [ 33.998814] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage3 -> opt_setup_stage2 [ 34.011159] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage2 -> opt_setup_stage1 [ 34.023498] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage2 -> opt_setup_stage1 [ 34.035842] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage2 -> opt_setup_stage1 [ 34.048190] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition opt_setup_stage1 -> link_setup [ 34.060007] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition opt_setup_stage1 -> link_setup [ 34.071828] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage1 -> link_setup [ 34.083654] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_setup -> clk_sync_stage3 [ 34.095386] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_setup -> clk_sync_stage3 [ 34.107126] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_setup -> clk_sync_stage3 [ 34.118861] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clk_sync_stage3 -> clk_sync_stage2 [ 34.131027] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clk_sync_stage3 -> clk_sync_stage2 [ 34.143196] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage3 -> clk_sync_stage2 [ 34.155368] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage1 [ 34.167534] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clk_sync_stage2 -> clk_sync_stage1 [ 34.179704] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage1 [ 34.191877] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition clk_sync_stage1 -> link_pre_setup [ 34.203956] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition clk_sync_stage1 -> link_pre_setup [ 34.216038] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage1 -> link_pre_setup [ 34.228125] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_pre_setup -> link_supported [ 34.240121] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_pre_setup -> link_supported [ 34.252113] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_pre_setup -> link_supported [ 34.264112] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_supported -> link_init [ 34.275670] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_supported -> link_init [ 34.287232] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_supported -> link_init [ 34.298796] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition link_init -> device_init [ 34.310095] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition link_init -> device_init [ 34.321397] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_init -> device_init [ 34.332701] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:2] transition device_init -> idle [ 34.343565] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:1] transition device_init -> idle [ 34.354432] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition device_init -> idle [ 34.365303] jesd204: /axi/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi1.1: FSM completed with error -1 [ 34.374785] axi-jesd204-tx 84a90000.axi-jesd204-tx: AXI-JESD204-TX (1.06.a) at 0x84A90000. Encoder 8b10b, width 4/4, lanes 4, jesd204-fsm. [ 34.389722] of_cfs_init [ 34.392173] of_cfs_init: OK [ 34.395119] cfg80211: Loading compiled-in X.509 certificates for regulatory database [ 34.519751] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7' [ 34.526283] clk: Not disabling unused clocks [ 34.530799] ALSA device list: [ 34.533756] No soundcards found. [ 34.537411] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2 [ 34.546020] cfg80211: failed to load regulatory.db [ 34.551502] Freeing unused kernel memory: 2624K [ 34.568797] Run /init as init process udhcpc: started, v1.32.0 [ 34.646337] macb ff0e0000.ethernet eth0: PHY [ff0e0000.ethernet-ffffffff:01] driver [Marvell 88E1510] (irq=POLL) [ 34.656522] macb ff0e0000.ethernet eth0: configuring for phy/rgmii-id link mode udhcpc: sending discover udhcpc: sending discover Via ILAs we confirmed the reference clock signal programmed via SPI produced by the ad9258 was alive, and then proceeded to check the RX, TX and RXObs clocks generated by the AXI CLKGEN IPs ( https://wiki.analog.com/resources/fpga/docs/axi_clkgen ) which were not working. Checking the axi_clkgen IP's register space, we noticed the reset register was still active (0x0040, bit 0) and the MMCM_LOCKED register was not enabled (0x005C) which explained why the clocks were not being generated, even though the input clock appeared to be working. We checked our device tree and explored the adrv9371/jesd204 drivers to see where the problem might lay with no success as of now. We also noticed that the tx clock is active for a moment during the kernel boot and goes down when the following line appears on the boot log : [ 34.374785] axi-jesd204-tx 84a90000.axi-jesd204-tx: AXI-JESD204-TX (1.06.a) at 0x84A90000. Encoder 8b10b, width 4/4, lanes 4, jesd204-fsm. The same must happen to the rx and rx_obs clocks but their respective lines appear much sooner within the kernel boot, and therefore is harder to detect. Having presented the issue, we got a few questions: Is the JESD link enable issue related with the fact that no RX/TX/RXobs clocks are active, or are they seperate issues? What could be causing the axi_clkGen IPs to have their reset signals active? Thanks in advance!

ffaserodio · Accepted Answer

It was indeed the SYNC signal polarity that was inverted: inverted the polarity, tested and now the link is in DATA state and we can see signal on our VSA. 
 The polarity was inverted to begin with because of how the TEBF0808's routes its pins onto the FMC interface, which swaps the polarity. Swapping the pins through constraints/top-level would yield an error while writing bitstream in Vivado, and thus, when we first started porting the design, we mantainned the swapped pins just to be able to write a bitstream and start testing. 
 To fix this I added an inverter on the BD just before the axi-jesd204-tx's sync port, which inverted the signal back to the correct polarity and now everything works as expected. 
 /sys/bus/platform/drivers/axi-jesd204-tx/84a90000.axi-jesd204-tx/status:Link is enabled
/sys/bus/platform/drivers/axi-jesd204-tx/84a90000.axi-jesd204-tx/status:Measured Link Clock: 122.881 MHz
/sys/bus/platform/drivers/axi-jesd204-tx/84a90000.axi-jesd204-tx/status:Reported Link Clock: 122.880 MHz
/sys/bus/platform/drivers/axi-jesd204-tx/84a90000.axi-jesd204-tx/status:Measured Device Clock: 122.881 MHz
/sys/bus/platform/drivers/axi-jesd204-tx/84a90000.axi-jesd204-tx/status:Reported Device Clock: 122.880 MHz
/sys/bus/platform/drivers/axi-jesd204-tx/84a90000.axi-jesd204-tx/status:Desired Device Clock: 122.880 MHz
/sys/bus/platform/drivers/axi-jesd204-tx/84a90000.axi-jesd204-tx/status:Lane rate: 4915.200 MHz
/sys/bus/platform/drivers/axi-jesd204-tx/84a90000.axi-jesd204-tx/status:Lane rate / 40: 122.880 MHz
/sys/bus/platform/drivers/axi-jesd204-tx/84a90000.axi-jesd204-tx/status:LMFC rate: 7.680 MHz
/sys/bus/platform/drivers/axi-jesd204-tx/84a90000.axi-jesd204-tx/status:SYNC~: deasserted
/sys/bus/platform/drivers/axi-jesd204-tx/84a90000.axi-jesd204-tx/status:Link status: DATA
/sys/bus/platform/drivers/axi-jesd204-tx/84a90000.axi-jesd204-tx/status:SYSREF captured: Yes
/sys/bus/platform/drivers/axi-jesd204-tx/84a90000.axi-jesd204-tx/status:SYSREF alignment error: No 
 Thank you for the help!)

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ADRV9371 + ZCU102 reference design port to custom board: RX, TX and RXObs Clocks not working