Product Number: AD9081
Software Version: N/A
Hi,
I'm trying to generate custom configurations for the MxFE, with a VCU118<->MxFE system. When I've booted and ran the implementation I get the errors: "QPLL1 TX/RX buffer overflow/underflow". The system works to an extent: I can interface with PyADI and operate the NCOs but I can't generate DMA based signals from the FPGA. Furthermore, the DAC, ADC Tx and Rx frequencies/sample rates appear correct.
I have used ADI's ACE GUI to validate the JESD and MxFE configuration:
I have taken the vcu118_ad9081_204c_txmode_10_rxmode_11.dts and modified it to the following:
// SPDX-License-Identifier: GPL-2.0
/*
* Analog Devices AD9081-FMC-EBZ
* https://wiki.analog.com/resources/tools-software/linux-drivers/iio-mxfe/ad9081
* https://wiki.analog.com/resources/eval/user-guides/ad9081_fmca_ebz/ad9081_fmca_ebz_hdl
*
* hdl_project: <ad9081_fmca_ebz/vcu118>
* board_revision: <>
*
* Copyright (C) 2019-2020 Analog Devices Inc.
*/
/*
* Lane Rate = 16.5 Gpbs
* Link Clock = 250 MHz
*/
#include "vcu118_ad9081.dts"
#define HMC7044_FPGA_XCVR_CLKDIV 12
#define HMC7044_FPGA_LINK_CLKDIV_TX 12
#define HMC7044_FPGA_LINK_CLKDIV_RX 12
#define HMC7044_SYSREF_CLKDIV 1024
#define AD9081_DAC_FREQUENCY 3000000000 // was (12000000000)
#define AD9081_ADC_FREQUENCY 1500000000 // was (4000000000)
/* TX path */
#define AD9081_TX_MAIN_INTERPOLATION 2 // was (12)
#define AD9081_TX_CHAN_INTERPOLATION 3 // was (1)
#define AD9081_TX_MAIN_NCO_SHIFT 0 // was (2800000000)
#define AD9081_TX_CHAN_NCO_SHIFT 0
#define AD9081_GAIN 1024
#define AD9081_TX_JESD_MODE 10
#define AD9081_TX_JESD_SUBCLASS 1
#define AD9081_TX_JESD_VERSION 2
#define AD9081_TX_JESD_M 4
#define AD9081_TX_JESD_F 2
#define AD9081_TX_JESD_K 128
#define AD9081_TX_JESD_N 16
#define AD9081_TX_JESD_NP 16
#define AD9081_TX_JESD_CS 0
#define AD9081_TX_JESD_L 4
#define AD9081_TX_JESD_S 1
#define AD9081_TX_JESD_HD 1
#define AD9081_JRX_TPL_PHASE_ADJUST 15
/* RX path */
#define AD9081_RX_MAIN_DECIMATION 1 // was (4)
#define AD9081_RX_CHAN_DECIMATION 3 // was (1)
#define AD9081_RX_MAIN_NCO_SHIFT 0 // was (1000000000)
#define AD9081_RX_CHAN_NCO_SHIFT 0
#define AD9081_RX_JESD_MODE 11
#define AD9081_RX_JESD_SUBCLASS 1
#define AD9081_RX_JESD_VERSION 2
#define AD9081_RX_JESD_M 4
#define AD9081_RX_JESD_F 2
#define AD9081_RX_JESD_K 128
#define AD9081_RX_JESD_N 16
#define AD9081_RX_JESD_NP 16
#define AD9081_RX_JESD_CS 0
#define AD9081_RX_JESD_L 4
#define AD9081_RX_JESD_S 1
#define AD9081_RX_JESD_HD 1
&axi_ad9081_adxcvr_rx {
adi,sys-clk-select = <XCVR_QPLL1>;
adi,out-clk-select = <XCVR_REFCLK>;
};
&axi_ad9081_adxcvr_tx {
adi,sys-clk-select = <XCVR_QPLL1>;
adi,out-clk-select = <XCVR_REFCLK>;
};
&hmc7044 {
adi,pll2-output-frequency = <3000000000>;
hmc7044_c2: channel@2 {
reg = <2>;
adi,extended-name = "DEV_REFCLK";
adi,divider = <12>; // 250
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>; // LVDS
};
hmc7044_c3: channel@3 {
reg = <3>;
adi,extended-name = "DEV_SYSREF";
adi,divider = <HMC7044_SYSREF_CLKDIV>; //
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>; // LVDS
adi,jesd204-sysref-chan;
};
hmc7044_c6: channel@6 {
reg = <6>;
adi,extended-name = "CORE_CLK_TX";
adi,divider = <HMC7044_FPGA_LINK_CLKDIV_TX>; // 250
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>; // LVDS
};
hmc7044_c8: channel@8 {
reg = <8>;
adi,extended-name = "CORE_CLK_RX";
adi,divider = <HMC7044_FPGA_LINK_CLKDIV_RX>; // 250
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>; // LVDS
};
hmc7044_c12: channel@12 {
reg = <12>;
adi,extended-name = "FPGA_REFCLK";
adi,divider = <HMC7044_FPGA_XCVR_CLKDIV>; // 250
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>; // LVDS
};
hmc7044_c13: channel@13 {
reg = <13>;
adi,extended-name = "FPGA_SYSREF";
adi,divider = <HMC7044_SYSREF_CLKDIV>; //
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>; // LVDS
adi,jesd204-sysref-chan;
};
};
&trx0_ad9081 {
adi,tx-dacs {
#size-cells = <0>;
#address-cells = <1>;
adi,dac-frequency-hz = /bits/ 64 <AD9081_DAC_FREQUENCY>;
adi,main-data-paths {
#address-cells = <1>;
#size-cells = <0>;
adi,interpolation = <AD9081_TX_MAIN_INTERPOLATION>;
trx0_ad9081_dac0: dac@0 {
reg = <0>;
adi,crossbar-select = <&trx0_ad9081_tx_fddc_chan0>;
adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_TX_MAIN_NCO_SHIFT>; /* 100 MHz */
};
trx0_ad9081_dac1: dac@1 {
reg = <1>;
adi,crossbar-select = <&trx0_ad9081_tx_fddc_chan1>;
adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_TX_MAIN_NCO_SHIFT>; /* 200 MHz */
};
};
adi,channelizer-paths {
#address-cells = <1>;
#size-cells = <0>;
adi,interpolation = <AD9081_TX_CHAN_INTERPOLATION>;
trx0_ad9081_tx_fddc_chan0: channel@0 {
reg = <0>;
adi,gain = <AD9081_GAIN>; /* value * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_TX_CHAN_NCO_SHIFT>;
};
trx0_ad9081_tx_fddc_chan1: channel@1 {
reg = <1>;
adi,gain = <AD9081_GAIN>; /* value * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_TX_CHAN_NCO_SHIFT>;
};
};
adi,jesd-links {
#size-cells = <0>;
#address-cells = <1>;
adi,ctle-filter-settings = /bits/ 8 <1 1 1 1 1 1 1 1>;
trx0_ad9081_tx_jesd_l0: link@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
adi,tpl-phase-adjust = <AD9081_JRX_TPL_PHASE_ADJUST>;
adi,logical-lane-mapping = /bits/ 8 <0 2 7 6 1 5 4 3>;
adi,link-mode = <AD9081_TX_JESD_MODE>; /* JESD Quick Configuration Mode */
adi,subclass = <AD9081_TX_JESD_SUBCLASS>; /* JESD SUBCLASS 0,1,2 */
adi,version = <AD9081_TX_JESD_VERSION>; /* JESD VERSION 0=204A,1=204B,2=204C */
adi,dual-link = <0>; /* JESD Dual Link Mode */
adi,converters-per-device = <AD9081_TX_JESD_M>; /* JESD M */
adi,octets-per-frame = <AD9081_TX_JESD_F>; /* JESD F */
adi,frames-per-multiframe = <AD9081_TX_JESD_K>; /* JESD K */
adi,converter-resolution = <AD9081_TX_JESD_N>; /* JESD N */
adi,bits-per-sample = <AD9081_TX_JESD_N>; /* JESD NP' */
adi,control-bits-per-sample = <AD9081_TX_JESD_CS>; /* JESD CS */
adi,lanes-per-device = <AD9081_TX_JESD_L>; /* JESD L */
adi,samples-per-converter-per-frame = <AD9081_TX_JESD_S>; /* JESD S */
adi,high-density = <AD9081_TX_JESD_HD>; /* JESD HD */
};
};
};
adi,rx-adcs {
#size-cells = <0>;
#address-cells = <1>;
adi,adc-frequency-hz = /bits/ 64 <AD9081_ADC_FREQUENCY>;
adi,nyquist-zone = <AD9081_ADC_NYQUIST_ZONE_EVEN>;
adi,main-data-paths {
#address-cells = <1>;
#size-cells = <0>;
trx0_ad9081_adc0: adc@0 {
reg = <0>;
adi,decimation = <AD9081_RX_MAIN_DECIMATION>;
adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_RX_MAIN_NCO_SHIFT>;
adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
//adi,crossbar-select = <&trx0_ad9081_rx_fddc_chan0>, <&trx0_ad9081_rx_fddc_chan2>; /* Static for now */
};
trx0_ad9081_adc1: adc@1 {
reg = <1>;
adi,decimation = <AD9081_RX_MAIN_DECIMATION>;
adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_RX_MAIN_NCO_SHIFT>;
adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
//adi,crossbar-select = <&trx0_ad9081_rx_fddc_chan1>, <&trx0_ad9081_rx_fddc_chan3>; /* Static for now */
};
};
adi,channelizer-paths {
#address-cells = <1>;
#size-cells = <0>;
trx0_ad9081_rx_fddc_chan0: channel@0 {
reg = <0>;
adi,decimation = <AD9081_RX_CHAN_DECIMATION>;
adi,gain = <AD9081_GAIN>; /* value * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_RX_CHAN_NCO_SHIFT>;
};
trx0_ad9081_rx_fddc_chan1: channel@1 {
reg = <1>;
adi,decimation = <AD9081_RX_CHAN_DECIMATION>;
adi,gain = <AD9081_GAIN>; /* value * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_RX_CHAN_NCO_SHIFT>;
};
};
adi,jesd-links {
#size-cells = <0>;
#address-cells = <1>;
trx0_ad9081_rx_jesd_l0: link@0 {
reg = <0>;
adi,converter-select =
<&trx0_ad9081_rx_fddc_chan0 FDDC_I>, <&trx0_ad9081_rx_fddc_chan0 FDDC_Q>,
<&trx0_ad9081_rx_fddc_chan1 FDDC_I>, <&trx0_ad9081_rx_fddc_chan1 FDDC_Q>;
adi,logical-lane-mapping = /bits/ 8 <2 0 7 6 5 4 3 1>;
adi,link-mode = <AD9081_RX_JESD_MODE>; /* JESD Quick Configuration Mode */
adi,subclass = <AD9081_RX_JESD_SUBCLASS>; /* JESD SUBCLASS 0,1,2 */
adi,version = <AD9081_RX_JESD_VERSION>; /* JESD VERSION 0=204A,1=204B,2=204C */
adi,dual-link = <0>; /* JESD Dual Link Mode */
adi,device-id = <3>;
adi,converters-per-device = <AD9081_RX_JESD_M>; /* JESD M */
adi,octets-per-frame = <AD9081_RX_JESD_F>; /* JESD F */
adi,frames-per-multiframe = <AD9081_RX_JESD_K>; /* JESD K */
adi,converter-resolution = <AD9081_RX_JESD_N>; /* JESD N */
adi,bits-per-sample = <AD9081_RX_JESD_NP>; /* JESD NP' */
adi,control-bits-per-sample = <AD9081_RX_JESD_CS>; /* JESD CS */
adi,lanes-per-device = <AD9081_RX_JESD_L>; /* JESD L */
adi,samples-per-converter-per-frame = <AD9081_RX_JESD_S>; /* JESD S */
adi,high-density = <AD9081_RX_JESD_HD>; /* JESD HD */
};
};
};
};
I took the pre-built HDL design 2021_r2_vcu118_ad9081_204c_txmode_10_rxmode_11.zip, from here Loading [Analog Devices Wiki].
If I power-cycle the MxFE I get the following output:
# echo 0 > powerdown jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition device_init -> idle jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition device_init -> idle jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition idle -> idle jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition idle -> idle jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition idle -> device_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition idle -> device_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition device_init -> link_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition device_init -> link_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_init -> link_supported jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_init -> link_supported jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_supported -> link_pre_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_supported -> link_pre_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_pre_setup -> clk_sync_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_pre_setup -> clk_sync_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clk_sync_stage1 -> clk_sync_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clk_sync_stage1 -> clk_sync_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage3 axi_adxcvr 44b60000.axi-adxcvr-tx: adxcvr_clk_enable: QPLL1 TX buffer overflow error, status: 0x41 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clk_sync_stage3 -> link_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clk_sync_stage3 -> link_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_setup -> opt_setup_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_setup -> opt_setup_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage1 -> opt_setup_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage1 -> opt_setup_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage2 -> opt_setup_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage2 -> opt_setup_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage3 -> opt_setup_stage4 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage3 -> opt_setup_stage4 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage4 -> opt_setup_stage5 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage4 -> opt_setup_stage5 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage5 -> clocks_enable jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage5 -> clocks_enable axi_adxcvr 44a60000.axi-adxcvr-rx: adxcvr_clk_enable: QPLL1 RX buffer underflow error, status: 0x21 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clocks_enable -> link_enable jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clocks_enable -> link_enable axi-jesd204-rx 44a90000.axi-jesd204-rx: axi_jesd204_rx_jesd204_link_running: Link2 status failed (BLOCK_SYNC) jesd204: /amba_pl/axi-jesd204-rx@44a90000,jesd204:4,parent=44a90000.axi-jesd204-rx: JESD204[0:2] In link_running got error from cb: -1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: Rolling back from 'link_enable', got error -1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_enable -> link_running jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_enable -> link_running jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_running -> link_enable jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_running -> link_enable jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_enable -> clocks_enable jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_enable -> clocks_enable jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clocks_enable -> opt_setup_stage5 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clocks_enable -> opt_setup_stage5 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage5 -> opt_setup_stage4 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage5 -> opt_setup_stage4 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage4 -> opt_setup_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage4 -> opt_setup_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage3 -> opt_setup_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage3 -> opt_setup_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage2 -> opt_setup_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage2 -> opt_setup_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage1 -> link_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage1 -> link_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_setup -> clk_sync_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_setup -> clk_sync_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clk_sync_stage3 -> clk_sync_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clk_sync_stage3 -> clk_sync_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clk_sync_stage1 -> link_pre_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clk_sync_stage1 -> link_pre_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_pre_setup -> link_supported jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_pre_setup -> link_supported jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_supported -> link_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_supported -> link_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_init -> device_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_init -> device_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition device_init -> idle jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition device_init -> idle jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition idle -> idle jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition idle -> idle jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition idle -> device_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition idle -> device_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition device_init -> link_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition device_init -> link_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_init -> link_supported jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_init -> link_supported jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_supported -> link_pre_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_supported -> link_pre_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_pre_setup -> clk_sync_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_pre_setup -> clk_sync_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clk_sync_stage1 -> clk_sync_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clk_sync_stage1 -> clk_sync_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage3 axi_adxcvr 44b60000.axi-adxcvr-tx: adxcvr_clk_enable: QPLL1 TX buffer overflow error, status: 0x41 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clk_sync_stage3 -> link_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clk_sync_stage3 -> link_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_setup -> opt_setup_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_setup -> opt_setup_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage1 -> opt_setup_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage1 -> opt_setup_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage2 -> opt_setup_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage2 -> opt_setup_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage3 -> opt_setup_stage4 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage3 -> opt_setup_stage4 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage4 -> opt_setup_stage5 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage4 -> opt_setup_stage5 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage5 -> clocks_enable jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage5 -> clocks_enable axi_adxcvr 44a60000.axi-adxcvr-rx: adxcvr_clk_enable: QPLL1 RX buffer underflow error, status: 0x21 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clocks_enable -> link_enable jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clocks_enable -> link_enable axi-jesd204-rx 44a90000.axi-jesd204-rx: axi_jesd204_rx_jesd204_link_running: Link2 status failed (BLOCK_SYNC) jesd204: /amba_pl/axi-jesd204-rx@44a90000,jesd204:4,parent=44a90000.axi-jesd204-rx: JESD204[0:2] In link_running got error from cb: -1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: Rolling back from 'link_enable', got error -1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_enable -> link_running jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_enable -> link_running jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_running -> link_enable jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_running -> link_enable jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_enable -> clocks_enable jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_enable -> clocks_enable jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clocks_enable -> opt_setup_stage5 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clocks_enable -> opt_setup_stage5 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage5 -> opt_setup_stage4 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage5 -> opt_setup_stage4 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage4 -> opt_setup_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage4 -> opt_setup_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage3 -> opt_setup_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage3 -> opt_setup_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage2 -> opt_setup_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage2 -> opt_setup_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage1 -> link_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage1 -> link_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_setup -> clk_sync_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_setup -> clk_sync_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clk_sync_stage3 -> clk_sync_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clk_sync_stage3 -> clk_sync_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clk_sync_stage1 -> link_pre_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clk_sync_stage1 -> link_pre_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_pre_setup -> link_supported jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_pre_setup -> link_supported jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_supported -> link_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_supported -> link_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_init -> device_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_init -> device_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition device_init -> idle jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition device_init -> idle jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition idle -> idle jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition idle -> idle jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition idle -> device_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition idle -> device_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition device_init -> link_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition device_init -> link_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_init -> link_supported jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_init -> link_supported jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_supported -> link_pre_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_supported -> link_pre_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_pre_setup -> clk_sync_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_pre_setup -> clk_sync_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clk_sync_stage1 -> clk_sync_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clk_sync_stage1 -> clk_sync_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage3 axi_adxcvr 44b60000.axi-adxcvr-tx: adxcvr_clk_enable: QPLL1 TX buffer overflow error, status: 0x41 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clk_sync_stage3 -> link_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clk_sync_stage3 -> link_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_setup -> opt_setup_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_setup -> opt_setup_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage1 -> opt_setup_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage1 -> opt_setup_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage2 -> opt_setup_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage2 -> opt_setup_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage3 -> opt_setup_stage4 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage3 -> opt_setup_stage4 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage4 -> opt_setup_stage5 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage4 -> opt_setup_stage5 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage5 -> clocks_enable jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage5 -> clocks_enable axi_adxcvr 44a60000.axi-adxcvr-rx: adxcvr_clk_enable: QPLL1 RX buffer underflow error, status: 0x21 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clocks_enable -> link_enable jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clocks_enable -> link_enable axi-jesd204-rx 44a90000.axi-jesd204-rx: axi_jesd204_rx_jesd204_link_running: Link2 status failed (BLOCK_SYNC) jesd204: /amba_pl/axi-jesd204-rx@44a90000,jesd204:4,parent=44a90000.axi-jesd204-rx: JESD204[0:2] In link_running got error from cb: -1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: Rolling back from 'link_enable', got error -1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_enable -> link_running jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_enable -> link_running jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_running -> link_enable jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_running -> link_enable jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_enable -> clocks_enable jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_enable -> clocks_enable jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clocks_enable -> opt_setup_stage5 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clocks_enable -> opt_setup_stage5 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage5 -> opt_setup_stage4 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage5 -> opt_setup_stage4 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage4 -> opt_setup_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage4 -> opt_setup_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage3 -> opt_setup_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage3 -> opt_setup_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage2 -> opt_setup_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage2 -> opt_setup_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage1 -> link_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage1 -> link_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_setup -> clk_sync_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_setup -> clk_sync_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clk_sync_stage3 -> clk_sync_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clk_sync_stage3 -> clk_sync_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clk_sync_stage1 -> link_pre_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clk_sync_stage1 -> link_pre_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_pre_setup -> link_supported jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_pre_setup -> link_supported jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_supported -> link_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_supported -> link_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_init -> device_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_init -> device_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition device_init -> idle jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition device_init -> idle jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition idle -> idle jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition idle -> idle jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition idle -> device_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition idle -> device_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition device_init -> link_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition device_init -> link_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_init -> link_supported jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_init -> link_supported jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_supported -> link_pre_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_supported -> link_pre_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_pre_setup -> clk_sync_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_pre_setup -> clk_sync_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clk_sync_stage1 -> clk_sync_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clk_sync_stage1 -> clk_sync_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage3 axi_adxcvr 44b60000.axi-adxcvr-tx: adxcvr_clk_enable: QPLL1 TX buffer overflow error, status: 0x41 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clk_sync_stage3 -> link_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clk_sync_stage3 -> link_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_setup -> opt_setup_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_setup -> opt_setup_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage1 -> opt_setup_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage1 -> opt_setup_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage2 -> opt_setup_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage2 -> opt_setup_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage3 -> opt_setup_stage4 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage3 -> opt_setup_stage4 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage4 -> opt_setup_stage5 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage4 -> opt_setup_stage5 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage5 -> clocks_enable jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage5 -> clocks_enable axi_adxcvr 44a60000.axi-adxcvr-rx: adxcvr_clk_enable: QPLL1 RX buffer underflow error, status: 0x21 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clocks_enable -> link_enable jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clocks_enable -> link_enable axi-jesd204-rx 44a90000.axi-jesd204-rx: axi_jesd204_rx_jesd204_link_running: Link2 status failed (BLOCK_SYNC) jesd204: /amba_pl/axi-jesd204-rx@44a90000,jesd204:4,parent=44a90000.axi-jesd204-rx: JESD204[0:2] In link_running got error from cb: -1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: Rolling back from 'link_enable', got error -1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_enable -> link_running jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_enable -> link_running jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_running -> link_enable jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_running -> link_enable jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_enable -> clocks_enable jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_enable -> clocks_enable jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clocks_enable -> opt_setup_stage5 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clocks_enable -> opt_setup_stage5 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage5 -> opt_setup_stage4 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage5 -> opt_setup_stage4 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage4 -> opt_setup_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage4 -> opt_setup_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage3 -> opt_setup_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage3 -> opt_setup_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage2 -> opt_setup_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage2 -> opt_setup_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition opt_setup_stage1 -> link_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition opt_setup_stage1 -> link_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_setup -> clk_sync_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_setup -> clk_sync_stage3 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clk_sync_stage3 -> clk_sync_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clk_sync_stage3 -> clk_sync_stage2 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage1 jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition clk_sync_stage1 -> link_pre_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition clk_sync_stage1 -> link_pre_setup jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_pre_setup -> link_supported jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_pre_setup -> link_supported jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_supported -> link_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_supported -> link_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition link_init -> device_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition link_init -> device_init jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:0] transition device_init -> idle jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: JESD204[0:2] transition device_init -> idle jesd204: /amba_pl/spi@44a70000/ad9081@0,jesd204:1,parent=spi0.0: FSM completed with error -1
In a similar thread (QPLL RX buffer under/overflow flow error - Q&A - Clock and Timing - EngineerZone (analog.com)), the jesd and clock statuses were queried; therefore, I've included them below:
jesd_status
clk
Can you please help me understand the problem and, furthermore, any advice on the general approach to branching to custom JESD/MxFE configurations would be great!
Kind regards,
Deng
