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ad9361, digital tuning error on linux

Category: Hardware
Product Number: ad9361

A riddle from Jacques Fresco.
This error occurs. When I use NO-OS, there is no such error.
ad9361_spi_writem: reg 0x74 val 0x1
ad9361_spi_writem: reg 0x73 val 0x67
ad9361_spi_writem: reg 0x76 val 0x1
ad9361_spi_writem: reg 0x75 val 0x67
ad9361_spi_writem: reg 0x4A val 0x35
ad9361_spi_writem: reg 0x49 val 0x5B
ad9361_spi_writem: reg 0x48 val 0xE8
SAMPL CLK: 25000000 tuning: RX
0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:# # # # # # # # # # # # # # # #
1:# # # # # # # # # # # # # # # #
ad9361_spi_writem: reg 0x4A val 0x35
ad9361_spi_writem: reg 0x49 val 0x5B
ad9361_spi_writem: reg 0x48 val 0xE8
SAMPL CLK: 40000000 tuning: RX
0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:# # # # # # # # # # # # # # # #
1:# # # # # # # # # # # # # # # #
ad9361_spi_writem: reg 0x4A val 0x35
ad9361_spi_writem: reg 0x49 val 0x5B
ad9361_spi_writem: reg 0x48 val 0xE8
SAMPL CLK: 61440000 tuning: RX
0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:# # # # # # # # # # # # # # # #
1:# # # # # # # # # # # # # # # #
SAMPL CLK: 61440000 tuning: RX
0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:# # # # # # # # # # # # # # # #
1:# # # # # # # # # # # # # # # #
ad9361 spi2.0: ad9361_dig_tune_delay: Tuning RX FAILED!
ad9361_spi_writem: reg 0x74 val 0x0
ad9361_spi_writem: reg 0x73 val 0x28
ad9361_spi_writem: reg 0x76 val 0x0
ad9361_spi_writem: reg 0x75 val 0x28
cf_axi_adc: probe of 79020000.cf-ad9361-lpc failed with error -5

Here's a tree:

ptm@f889c000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0xf889c000 0x1000>;
clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
cpu = <&cpu0>;
out-ports {
port {
ptm0_out_port: endpoint {
remote-endpoint = <&funnel0_in_port0>;
};
};
};
};

ptm@f889d000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0xf889d000 0x1000>;
clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
cpu = <&cpu1>;
out-ports {
port {
ptm1_out_port: endpoint {
remote-endpoint = <&funnel0_in_port1>;
};
};
};
};
};
};
# 3 "zynq.dtsi" 2
/ {
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
aliases {
serial0 = &uart0;
spi0 = &qspi;
// spi1 = &axi_spi;
spi2 = &spi0;
};
memory {
device_type = "memory";
reg = <0x0 0x20000000>;
};
};

/ {
cpus {
cpu@0 {
operating-points = <800000 1000000 400000 1000000 200000 1000000>;
};
};
};
&gpio0 {
emio-gpio-width = <25>;
gpio-mask-high = <0x0>;
gpio-mask-low = <0x5600>;
};
&intc {
num_cpus = <2>;
num_interrupts = <96>;
};
&qspi {
is-dual = <0>;
num-cs = <0x1>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
status = "okay";
};
&sdhci0 {
status = "okay";
xlnx,has-cd = <0x1>;
xlnx,has-power = <0x0>;
xlnx,has-wp = <0x0>;
};
&spi0 {
is-decoded-cs = <0>;
num-cs = <0x3>;
status = "okay";
};
&uart0 {
cts-override ;
device_type = "serial";
port-number = <0>;
status = "okay";
};
&clkc {
fclk-enable = <0x3>;
ps-clk-frequency = <33333333>;
};
# 9 "zynq-antsdre200.dtsi" 2
# 1 "/home/vasiliy/scat_lib/zynq_timestamping/ant_device_tree/generate/include/dt-bindings/input/input.h" 1
# 13 "/home/vasiliy/scat_lib/zynq_timestamping/ant_device_tree/generate/include/dt-bindings/input/input.h"
# 1 "/home/vasiliy/scat_lib/zynq_timestamping/ant_device_tree/generate/include/dt-bindings/input/linux-event-codes.h" 1
# 14 "/home/vasiliy/scat_lib/zynq_timestamping/ant_device_tree/generate/include/dt-bindings/input/input.h" 2
# 10 "zynq-antsdre200.dtsi" 2
# 1 "/home/vasiliy/scat_lib/zynq_timestamping/ant_device_tree/generate/include/dt-bindings/gpio/gpio.h" 1
# 11 "zynq-antsdre200.dtsi" 2
# 1 "/home/vasiliy/scat_lib/zynq_timestamping/ant_device_tree/generate/include/dt-bindings/interrupt-controller/irq.h" 1
# 12 "zynq-antsdre200.dtsi" 2


# 1 "/home/vasiliy/scat_lib/zynq_timestamping/ant_device_tree/generate/include/dt-bindings/iio/adc/adi,ad9361.h" 1
# 15 "zynq-antsdre200.dtsi" 2

/ {
// model = "MicroPhase ANTSDR E200";
// memory {
// device_type = "memory";
// reg = <0x00000000 0x20000000>;
// };

// aliases {
// ethernet0 = &gem0;
// serial0 = &uart0;
// spi0 = &qspi;
// mmc0 = &sdhci0;
// };

// chosen {

// stdout-path = "/amba@0/uart@E0000000";
// };


clocks {
ad9361_clkin: clock@0 {
compatible = "fixed-clock";

clock-frequency = <40000000>;
clock-output-names = "ad9361_ext_refclk";
#clock-cells = <0>;
};
};

// ltc2630 {
// compatible = "microphase,ltc2630";
// status = "okay";
// ext_ref_locked = <&gpio0 68 1>;
// ext_ref_ispps = <&gpio0 69 0>;
// ref_sel = <&gpio0 70 0>;
// };


};


&sdhci0 {
status = "okay";
xlnx,has-cd = <0x0>;
xlnx,has-power = <0x0>;
xlnx,has-wp = <0x0>;
};

&watchdog0 {
status = "okay";
reset-on-timeout;
};

&uart0 {
status = "okay";
};
# 110 "zynq-antsdre200.dtsi"
&gem0 {
status = "okay";

phy-handle = <&phy0>;
phy-mode = "rgmii-rxid";
xlnx,has-mdio = <0x1>;
gmii2rgmii-phy-handle = <&gmii_to_rgmii_0>;

phy0: phy@1 {
compatible = "ethernet-phy-id011c.c916";
device_type = "ethernet-phy";
reg = <0x1>;

};

gmii_to_rgmii_0: gmiitorgmii@8 {
compatible = "xlnx,gmii-to-rgmii-1.0";
reg = <0x8>;
phy-handle = <&phy0>;
};

};

&qspi {
status = "okay";
is-dual = <0>;
num-cs = <1>;
primary_flash: ps7-qspi@0 {
#address-cells = <1>;
#size-cells = <1>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
compatible = "n25q256a", "n25q512a", "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <50000000>;
partition@qspi-fsbl-uboot {
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@qspi-uboot-env {
label = "qspi-uboot-env";
reg = <0x100000 0x20000>;
};
partition@qspi-nvmfs {
label = "qspi-nvmfs";
reg = <0x120000 0xE0000>;
};
partition@qspi-linux {
label = "qspi-linux";
reg = <0x200000 0x1E00000>;
};
};
};

&adc {
xlnx,channels {
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
};
};
};

/ {
fpga_axi: fpga-axi@0 {
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;

rx_dma: dma@7c400000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x7c400000 0x1000>;
#dma-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <0 57 4>;
clocks = <&clkc 16>;

adi,channels {
#size-cells = <0>;
#address-cells = <1>;

dma-channel@0 {
reg = <0>;
adi,source-bus-width = <32>;
adi,source-bus-type = <2>;
adi,destination-bus-width = <64>;
adi,destination-bus-type = <0>;
};
};
};

tx_dma: dma@7c420000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x7c420000 0x1000>;
#dma-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <0 56 4>;
clocks = <&clkc 16>;

adi,channels {
#size-cells = <0>;
#address-cells = <1>;

dma-channel@0 {
reg = <0>;
adi,source-bus-width = <64>;
adi,source-bus-type = <0>;
adi,destination-bus-width = <32>;
adi,destination-bus-type = <2>;
};
};
};

cf_ad9364_adc_core_0: cf-ad9361-lpc@79020000 {
compatible = "adi,axi-ad9361-6.00.a";
reg = <0x79020000 0x6000>;
dmas = <&rx_dma 0>;
dma-names = "rx";
spibus-connected = <&adc0_ad9361>;
adi,axi-decimation-core-available;
};

cf_ad9364_dac_core_0: cf-ad9361-dds-core-lpc@79024000 {
compatible = "adi,axi-ad9361-dds-6.00.a";
reg = <0x79024000 0x1000>;
clocks = <&adc0_ad9361 13>;
clock-names = "sampl_clk";
dmas = <&tx_dma 0>;
dma-names = "tx";
adi,axi-interpolation-core-available;
adi,axi-dds-default-scale = <0>;
};

mwipcore@43c00000 {
compatible = "mathworks,mwipcore-axi4lite-v1.00";
reg = <0x43c00000 0xffff>;
};
};
};

&spi0 {
status = "okay";

adc0_ad9361: ad9361-phy@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi,ad9361";

reg = <0>;

/* SPI Setup */
spi-cpha;
spi-max-frequency = <10000000>;

/* Clocks */
clocks = <&ad9361_clkin 0>;
clock-names = "ad9361_ext_refclk";
clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
#clock-cells = <1>;

// adi,debug-mode-enable;
/* Digital Interface Control */

/* adi,digital-interface-tune-skip-mode:
* 0 = TUNE RX&TX
* 1 = SKIP TX
* 2 = SKIP ALL
*/
adi,digital-interface-tune-skip-mode = <0>;

adi,pp-tx-swap-enable;
adi,pp-rx-swap-enable;
adi,rx-frame-pulse-mode-enable;
adi,lvds-mode-enable;
adi,lvds-bias-mV = <150>;
adi,lvds-rx-onchip-termination-enable;
adi,rx-data-delay = <4>;
adi,tx-fb-clock-delay = <7>;

//adi,fdd-rx-rate-2tx-enable;

adi,dcxo-coarse-and-fine-tune = <8 5920>;
//adi,xo-disable-use-ext-refclk-enable;

/* Mode Setup */

adi,2rx-2tx-mode-enable;
//adi,split-gain-table-mode-enable;

/* ENSM Mode */
adi,frequency-division-duplex-mode-enable;
//adi,ensm-enable-pin-pulse-mode-enable;
//adi,ensm-enable-txnrx-control-enable;


/* adi,rx-rf-port-input-select:
* 0 = (RX1A_N & RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced
* 1 = (RX1B_N & RX1B_P) and (RX2B_N & RX2B_P) enabled; balanced
* 2 = (RX1C_N & RX1C_P) and (RX2C_N & RX2C_P) enabled; balanced
*
* 3 = RX1A_N and RX2A_N enabled; unbalanced
* 4 = RX1A_P and RX2A_P enabled; unbalanced
* 5 = RX1B_N and RX2B_N enabled; unbalanced
* 6 = RX1B_P and RX2B_P enabled; unbalanced
* 7 = RX1C_N and RX2C_N enabled; unbalanced
* 8 = RX1C_P and RX2C_P enabled; unbalanced
*/

adi,rx-rf-port-input-select = <0>; /* (RX1A_N & RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced */

/* adi,tx-rf-port-input-select:
* 0 TX1A, TX2A
* 1 TX1B, TX2B
*/

adi,tx-rf-port-input-select = <0>; /* TX1A, TX2A */
//adi,update-tx-gain-in-alert-enable;
adi,tx-attenuation-mdB = <10000>;
adi,tx-lo-powerdown-managed-enable;

adi,rf-rx-bandwidth-hz = <18000000>;
adi,rf-tx-bandwidth-hz = <18000000>;
adi,rx-synthesizer-frequency-hz = /bits/ 64 <2400000000>;
adi,tx-synthesizer-frequency-hz = /bits/ 64 <2400000000>;

/* BBPLL ADC R2CLK R1CLK CLKRF RSAMPL */
adi,rx-path-clock-frequencies = <983040000 245760000 122880000 61440000 30720000 30720000>;
/* BBPLL DAC T2CLK T1CLK CLKTF TSAMPL */
adi,tx-path-clock-frequencies = <983040000 122880000 122880000 61440000 30720000 30720000>;

/* Gain Control */

//adi,gaintable-name = "ad9361_std_gaintable";

/* adi,gc-rx[1|2]-mode:
* 0 = RF_GAIN_MGC
* 1 = RF_GAIN_FASTATTACK_AGC
* 2 = RF_GAIN_SLOWATTACK_AGC
* 3 = RF_GAIN_HYBRID_AGC
*/

adi,gc-rx1-mode = <2>;
adi,gc-rx2-mode = <2>;
adi,gc-adc-ovr-sample-size = <4>; /* sum 4 samples */
adi,gc-adc-small-overload-thresh = <47>; /* sum of squares */
adi,gc-adc-large-overload-thresh = <58>; /* sum of squares */
adi,gc-lmt-overload-high-thresh = <800>; /* mV */
adi,gc-lmt-overload-low-thresh = <704>; /* mV */
adi,gc-dec-pow-measurement-duration = <8192>; /* 0..524288 Samples */
adi,gc-low-power-thresh = <24>; /* 0..-64 dBFS vals are set pos */
//adi,gc-dig-gain-enable;
//adi,gc-max-dig-gain = <15>;

/* Manual Gain Control Setup */

//adi,mgc-rx1-ctrl-inp-enable; /* uncomment to use ctrl inputs */
//adi,mgc-rx2-ctrl-inp-enable; /* uncomment to use ctrl inputs */
adi,mgc-inc-gain-step = <2>;
adi,mgc-dec-gain-step = <2>;

/* adi,mgc-split-table-ctrl-inp-gain-mode:
* (relevant if adi,split-gain-table-mode-enable is set)
* 0 = AGC determine this
* 1 = only in LPF
* 2 = only in LMT
*/

adi,mgc-split-table-ctrl-inp-gain-mode = <0>;

/* Automatic Gain Control Setup */

adi,agc-attack-delay-extra-margin-us= <1>; /* us */
adi,agc-outer-thresh-high = <5>; /* -dBFS */
adi,agc-outer-thresh-high-dec-steps = <2>; /* 0..15 */
adi,agc-inner-thresh-high = <10>; /* -dBFS */
adi,agc-inner-thresh-high-dec-steps = <1>; /* 0..7 */
adi,agc-inner-thresh-low = <12>; /* -dBFS */
adi,agc-inner-thresh-low-inc-steps = <1>; /* 0..7 */
adi,agc-outer-thresh-low = <18>; /* -dBFS */
adi,agc-outer-thresh-low-inc-steps = <2>; /* 0..15 */

adi,agc-adc-small-overload-exceed-counter = <10>; /* 0..15 */
adi,agc-adc-large-overload-exceed-counter = <10>; /* 0..15 */
adi,agc-adc-large-overload-inc-steps = <2>; /* 0..15 */
//adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable;
adi,agc-lmt-overload-large-exceed-counter = <10>; /* 0..15 */
adi,agc-lmt-overload-small-exceed-counter = <10>; /* 0..15 */
adi,agc-lmt-overload-large-inc-steps = <2>; /* 0..7 */
//adi,agc-dig-saturation-exceed-counter = <3>; /* 0..15 */
//adi,agc-dig-gain-step-size = <4>; /* 1..8 */

//adi,agc-sync-for-gain-counter-enable;
adi,agc-gain-update-interval-us = <1000>; /* 1ms */
//adi,agc-immed-gain-change-if-large-adc-overload-enable;
//adi,agc-immed-gain-change-if-large-lmt-overload-enable;

/* Fast AGC */

adi,fagc-dec-pow-measurement-duration = <64>; /* 64 Samples */
//adi,fagc-allow-agc-gain-increase-enable;
adi,fagc-lp-thresh-increment-steps = <1>;
adi,fagc-lp-thresh-increment-time = <5>;

adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <8>;
adi,fagc-final-overrange-count = <3>;
//adi,fagc-gain-increase-after-gain-lock-enable;
adi,fagc-gain-index-type-after-exit-rx-mode = <0>;
adi,fagc-lmt-final-settling-steps = <1>;
adi,fagc-lock-level = <10>;
adi,fagc-lock-level-gain-increase-upper-limit = <5>;
adi,fagc-lock-level-lmt-gain-increase-enable;

adi,fagc-lpf-final-settling-steps = <1>;
adi,fagc-optimized-gain-offset = <5>;
adi,fagc-power-measurement-duration-in-state5 = <64>;
adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <10>;
adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable;
adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0>;
adi,fagc-rst-gla-large-adc-overload-enable;
adi,fagc-rst-gla-large-lmt-overload-enable;
adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <10>;
adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable;
adi,fagc-state-wait-time-ns = <260>;
adi,fagc-use-last-lock-level-for-set-gain-enable;

/* RSSI */

/* adi,rssi-restart-mode:
* 0 = AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN,
* 1 = EN_AGC_PIN_IS_PULLED_HIGH,
* 2 = ENTERS_RX_MODE,
* 3 = GAIN_CHANGE_OCCURS,
* 4 = SPI_WRITE_TO_REGISTER,
* 5 = GAIN_CHANGE_OCCURS_OR_EN_AGC_PIN_PULLED_HIGH,
*/
adi,rssi-restart-mode = <3>;
//adi,rssi-unit-is-rx-samples-enable;
adi,rssi-delay = <1>; /* 1us */
adi,rssi-wait = <1>; /* 1us */
adi,rssi-duration = <1000>; /* 1ms */

//test
adi,lvds-invert1-control = <0xFF>;
adi,lvds-invert2-control = <0x0F>;
adi,aux-adc-decimation = <256>;
adi,aux-adc-rate = <40000000>;
adi,dc-offset-count-high-range = <0x28>;
adi,dc-offset-count-low-range = <0x32>;

/* Control Outputs */
adi,ctrl-outs-index = <0>;
adi,ctrl-outs-enable-mask = <0xFF>;

/* AuxADC Temp Sense Control */

adi,temp-sense-measurement-interval-ms = <1000>;
adi,temp-sense-offset-signed = <0xCE>;
adi,temp-sense-periodic-measurement-enable;

/* AuxDAC Control */

adi,aux-dac-manual-mode-enable;

adi,aux-dac1-default-value-mV = <0>;
//adi,aux-dac1-active-in-rx-enable;
//adi,aux-dac1-active-in-tx-enable;
//adi,aux-dac1-active-in-alert-enable;
adi,aux-dac1-rx-delay-us = <0>;
adi,aux-dac1-tx-delay-us = <0>;

adi,aux-dac2-default-value-mV = <0>;
//adi,aux-dac2-active-in-rx-enable;
//adi,aux-dac2-active-in-tx-enable;
//adi,aux-dac2-active-in-alert-enable;
adi,aux-dac2-rx-delay-us = <0>;
adi,aux-dac2-tx-delay-us = <0>;

adi,delay-rx-data = <0>;
adi,rx-data-clock-delay = <0>;
adi,tx-data-delay = <0>;


// en_agc-gpios = <&gpio0 122 0>;
sync-gpios = <&gpio0 99 0>;
reset-gpios = <&gpio0 54 0>;
enable-gpios = <&gpio0 55 0>;
txnrx-gpios = <&gpio0 56 0>;
};
};
# 11 "zynq-antsdre200.dts" 2
# 24 "zynq-antsdre200.dts"



Change q.
[edited by: Novas228 at 11:19 AM (GMT -4) on 24 May 2023]
Parents
  • Hello,

    Thanks for reaching us.

    There are multiple threads that addressed this issue or similar in the Linux Software Drivers subforum.

    Please take a look:
    RE: AD9361 not tuning.

     RE: digital tuning failing on one of 4 AD9361 chips 

     Need help to resolve the failures in digital tuning of the AD-FMCOMMS3-EBZ (AD9361 Transceiver) channels 

    Regards,
    Antoniu

  • In the last attempt, I used the driver from the master branch, built the kernel based on the config under pluto.
    The firmware consists of a modified project under pluto\antsdr, where I changed cmos to lvds, changed gpio a little,
     removed axi_spi, axi_i2, and of course changed the constraints.
  • ad9361 spi0.0: ad9361_spi_write: reg 0x138 val 0x0
    ad9361 spi0.0: ad9361_spi_write: reg 0x13A val 0x0
    ad9361 spi0.0: ad9361_spi_write: reg 0x139 val 0x0
    ad9361 spi0.0: ad9361_spi_write: reg 0x13B val 0x3E
    ad9361 spi0.0: ad9361_spi_write: reg 0x13F val 0x6
    ad9361 spi0.0: ad9361_spi_write: reg 0x13C val 0x0
    ad9361 spi0.0: ad9361_spi_write: reg 0x13C val 0x0
    ad9361 spi0.0: ad9361_spi_write: reg 0x13F val 0x2
    ad9361 spi0.0: ad9361_spi_write: reg 0x13C val 0x0
    ad9361 spi0.0: ad9361_spi_write: reg 0x13C val 0x0
    ad9361 spi0.0: ad9361_spi_write: reg 0x13F val 0x0
    ad9361 spi0.0: ad9361_gc_setup
    ad9361 spi0.0: ad9361_spi_write: reg 0xFA val 0xEA
    ad9361 spi0.0: ad9361_spi_readm: reg 0xFB val 0x8
    ad9361 spi0.0: ad9361_spi_write: reg 0xFB val 0x8
    ad9361 spi0.0: ad9361_spi_readm: reg 0xFB val 0x8
    ad9361 spi0.0: ad9361_spi_write: reg 0xFB val 0x8
    ad9361 spi0.0: ad9361_spi_readm: reg 0xFB val 0x8
    ad9361 spi0.0: ad9361_spi_write: reg 0xFB val 0x8
    ad9361 spi0.0: ad9361_spi_write: reg 0xFC val 0x23
    ad9361 spi0.0: ad9361_spi_write: reg 0xFE val 0x20
    ad9361 spi0.0: ad9361_spi_write: reg 0x104 val 0x2F
    ad9361 spi0.0: ad9361_spi_write: reg 0x105 val 0x3A
    ad9361 spi0.0: ad9361_spi_write: reg 0x108 val 0x31
    ad9361 spi0.0: ad9361_spi_readm: reg 0x107 val 0x3F
    ad9361 spi0.0: ad9361_spi_write: reg 0x107 val 0x2B
    ad9361 spi0.0: ad9361_spi_write: reg 0x10B val 0x0
    ad9361 spi0.0: ad9361_spi_write: reg 0x10E val 0x0
    ad9361 spi0.0: ad9361_spi_write: reg 0x114 val 0x30
    ad9361 spi0.0: ad9361_spi_write: reg 0x81 val 0x0
    ad9361 spi0.0: ad9361_spi_readm: reg 0x15C val 0x19
    ad9361 spi0.0: ad9361_spi_write: reg 0x15C val 0x59
    ad9361 spi0.0: ad9361_spi_readm: reg 0x15C val 0x59
    ad9361 spi0.0: ad9361_spi_write: reg 0x15C val 0x79
    ad9361 spi0.0: ad9361_spi_readm: reg 0x15C val 0x79
    ad9361 spi0.0: ad9361_spi_write: reg 0x15C val 0x79
    ad9361 spi0.0: ad9361_spi_readm: reg 0x101 val 0xA
    ad9361 spi0.0: ad9361_spi_write: reg 0x101 val 0xA
    ad9361 spi0.0: ad9361_spi_write: reg 0x120 val 0xC
    ad9361 spi0.0: ad9361_spi_write: reg 0x129 val 0x56
    ad9361 spi0.0: ad9361_spi_write: reg 0x12A val 0x22
    ad9361 spi0.0: ad9361_spi_write: reg 0x123 val 0x11
    ad9361 spi0.0: ad9361_spi_write: reg 0x122 val 0xAA
    ad9361 spi0.0: ad9361_spi_write: reg 0x106 val 0x22
    ad9361 spi0.0: ad9361_spi_write: reg 0x121 val 0xAA
    ad9361 spi0.0: ad9361_spi_readm: reg 0x103 val 0x8
    ad9361 spi0.0: ad9361_spi_write: reg 0x103 val 0x8
    ad9361 spi0.0: ad9361_spi_write: reg 0x128 val 0x3
    ad9361 spi0.0: ad9361_spi_readm: reg 0x110 val 0x2
    ad9361 spi0.0: ad9361_spi_write: reg 0x110 val 0x2
    ad9361 spi0.0: ad9361_spi_write: reg 0x11B val 0x5
    ad9361 spi0.0: ad9361_spi_readm: reg 0x117 val 0x8
    ad9361 spi0.0: ad9361_spi_write: reg 0x117 val 0x8
    ad9361 spi0.0: ad9361_spi_readm: reg 0x111 val 0xCB
    ad9361 spi0.0: ad9361_spi_write: reg 0x111 val 0xCB
    ad9361 spi0.0: ad9361_spi_readm: reg 0x118 val 0x3F
    ad9361 spi0.0: ad9361_spi_write: reg 0x118 val 0x5
    ad9361 spi0.0: ad9361_spi_readm: reg 0x112 val 0x4A
    ad9361 spi0.0: ad9361_spi_write: reg 0x112 val 0x4A
    ad9361 spi0.0: ad9361_spi_readm: reg 0x113 val 0x4A
    ad9361 spi0.0: ad9361_spi_write: reg 0x113 val 0x4A
    ad9361 spi0.0: ad9361_spi_readm: reg 0x116 val 0x65
    ad9361 spi0.0: ad9361_spi_write: reg 0x116 val 0x65
    ad9361 spi0.0: ad9361_spi_readm: reg 0x110 val 0x2
    ad9361 spi0.0: ad9361_spi_write: reg 0x110 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x110 val 0x2
    ad9361 spi0.0: ad9361_spi_write: reg 0x110 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x110 val 0x2
    ad9361 spi0.0: ad9361_spi_write: reg 0x110 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x111 val 0xCB
    ad9361 spi0.0: ad9361_spi_write: reg 0x111 val 0xCB
    ad9361 spi0.0: ad9361_spi_readm: reg 0x116 val 0x65
    ad9361 spi0.0: ad9361_spi_write: reg 0x116 val 0x65
    ad9361 spi0.0: ad9361_spi_readm: reg 0xFB val 0x8
    ad9361 spi0.0: ad9361_spi_write: reg 0xFB val 0x8
    ad9361 spi0.0: ad9361_spi_readm: reg 0x115 val 0x0
    ad9361 spi0.0: ad9361_spi_write: reg 0x115 val 0x0
    ad9361 spi0.0: ad9361_spi_readm: reg 0x113 val 0x4A
    ad9361 spi0.0: ad9361_spi_write: reg 0x113 val 0x4A
    ad9361 spi0.0: ad9361_spi_readm: reg 0x112 val 0x4A
    ad9361 spi0.0: ad9361_spi_write: reg 0x112 val 0x4A
    ad9361 spi0.0: ad9361_spi_readm: reg 0x110 val 0x2
    ad9361 spi0.0: ad9361_spi_write: reg 0x110 val 0x42
    ad9361 spi0.0: ad9361_spi_readm: reg 0x110 val 0x42
    ad9361 spi0.0: ad9361_spi_write: reg 0x110 val 0x42
    ad9361 spi0.0: ad9361_spi_readm: reg 0x119 val 0x8
    ad9361 spi0.0: ad9361_spi_write: reg 0x119 val 0x8
    ad9361 spi0.0: ad9361_spi_readm: reg 0x110 val 0x42
    ad9361 spi0.0: ad9361_spi_write: reg 0x110 val 0x40
    ad9361 spi0.0: ad9361_spi_readm: reg 0x114 val 0x30
    ad9361 spi0.0: ad9361_spi_write: reg 0x114 val 0x30
    ad9361 spi0.0: ad9361_spi_readm: reg 0x110 val 0x40
    ad9361 spi0.0: ad9361_spi_write: reg 0x110 val 0x40
    ad9361 spi0.0: ad9361_spi_readm: reg 0x111 val 0xCB
    ad9361 spi0.0: ad9361_spi_write: reg 0x111 val 0xCB
    ad9361 spi0.0: ad9361_spi_readm: reg 0x10A val 0x58
    ad9361 spi0.0: ad9361_spi_write: reg 0x10A val 0x58
    ad9361 spi0.0: ad9361_spi_readm: reg 0x109 val 0x4C
    ad9361 spi0.0: ad9361_spi_write: reg 0x109 val 0x4C
    ad9361 spi0.0: ad9361_spi_readm: reg 0x3 val 0xDC
    ad9361 spi0.0: ad9361_spi_readm: reg 0x3 val 0xDC
    ad9361 spi0.0: ad9361_spi_readm: reg 0x22 val 0x2
    ad9361 spi0.0: ad9361_spi_write: reg 0x22 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0xFE val 0x20
    ad9361 spi0.0: ad9361_spi_write: reg 0xFE val 0x25
    ad9361 spi0.0: ad9361_spi_readm: reg 0x111 val 0xCB
    ad9361 spi0.0: ad9361_spi_write: reg 0x111 val 0xCB
    ad9361 spi0.0: ad9361_spi_readm: reg 0x3 val 0xDC
    ad9361 spi0.0: ad9361_spi_readm: reg 0x15C val 0x79
    ad9361 spi0.0: ad9361_spi_write: reg 0x15C val 0x79
    ad9361 spi0.0: ad9361_spi_readm: reg 0x128 val 0x3
    ad9361 spi0.0: ad9361_spi_write: reg 0x128 val 0x3
    ad9361 spi0.0: ad9361_spi_write: reg 0x124 val 0xF4
    ad9361 spi0.0: ad9361_spi_write: reg 0x125 val 0x3B
    ad9361 spi0.0: ad9361_spi_readm: reg 0x117 val 0x8
    ad9361 spi0.0: ad9361_spi_write: reg 0x117 val 0x8
    ad9361 spi0.0: ad9361_rx_bb_analog_filter_calib : rx_bb_bw 9000000 bbpll_freq 983040000
    ad9361 spi0.0: ad9361_spi_write: reg 0x1F8 val 0x9
    ad9361 spi0.0: ad9361_spi_readm: reg 0x1F9 val 0x1E
    ad9361 spi0.0: ad9361_spi_write: reg 0x1F9 val 0x1E
    ad9361 spi0.0: ad9361_spi_write: reg 0x1FB val 0x9
    ad9361 spi0.0: ad9361_spi_write: reg 0x1FC val 0x0
    ad9361 spi0.0: ad9361_spi_write: reg 0x1D5 val 0x3F
    ad9361 spi0.0: ad9361_spi_write: reg 0x1C0 val 0x3
    ad9361 spi0.0: ad9361_spi_write: reg 0x1E2 val 0x2
    ad9361 spi0.0: ad9361_spi_write: reg 0x1E3 val 0x2
    ad9361 spi0.0: ad9361_spi_write: reg 0x16 val 0x80
    ad9361 spi0.0: ad9361_run_calibration: CAL Mask 0x80
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x0
    ad9361 spi0.0: ad9361_spi_write: reg 0x1E2 val 0x3
    ad9361 spi0.0: ad9361_spi_write: reg 0x1E3 val 0x3
    ad9361 spi0.0: ad9361_tx_bb_analog_filter_calib : tx_bb_bw 9000000 bbpll_freq 983040000
    ad9361 spi0.0: ad9361_spi_write: reg 0xD6 val 0x8
    ad9361 spi0.0: ad9361_spi_readm: reg 0xD7 val 0x1E
    ad9361 spi0.0: ad9361_spi_write: reg 0xD7 val 0x1E
    ad9361 spi0.0: ad9361_spi_write: reg 0xCA val 0x22
    ad9361 spi0.0: ad9361_spi_write: reg 0x16 val 0x40
    ad9361 spi0.0: ad9361_run_calibration: CAL Mask 0x40
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x0
    ad9361 spi0.0: ad9361_spi_write: reg 0xCA val 0x26
    ad9361 spi0.0: ad9361_spi_readm: reg 0x1EB val 0x0
    ad9361 spi0.0: ad9361_spi_readm: reg 0x1EC val 0x35
    ad9361 spi0.0: ad9361_spi_readm: reg 0x1E6 val 0x1
    ad9361 spi0.0: ad9361_rx_tia_calib : bb_bw_Hz 9000000
    ad9361 spi0.0: ad9361_spi_write: reg 0x1DB val 0x60
    ad9361 spi0.0: ad9361_spi_write: reg 0x1DC val 0x67
    ad9361 spi0.0: ad9361_spi_write: reg 0x1DD val 0x0
    ad9361 spi0.0: ad9361_spi_write: reg 0x1DE val 0x67
    ad9361 spi0.0: ad9361_spi_write: reg 0x1DF val 0x0
    ad9361 spi0.0: ad9361_tx_bb_second_filter_calib : tx_bb_bw 9000000
    ad9361 spi0.0: ad9361_spi_write: reg 0xD0 val 0x56
    ad9361 spi0.0: ad9361_spi_write: reg 0xD1 val 0xC
    ad9361 spi0.0: ad9361_spi_write: reg 0xD2 val 0x17
    ad9361 spi0.0: ad9361_spi_readm: reg 0xA val 0xA
    ad9361 spi0.0: ad9361_spi_readm: reg 0xA val 0xA
    ad9361 spi0.0: ad9361_spi_readm: reg 0x2 val 0xCC
    ad9361 spi0.0: ad9361_spi_readm: reg 0x2 val 0xCC
    ad9361 spi0.0: ad9361_spi_readm: reg 0x2 val 0xCC
    ad9361 spi0.0: ad9361_spi_readm: reg 0x2 val 0xCC
    ad9361 spi0.0: ad9361_spi_readm: reg 0x3 val 0xDC
    ad9361 spi0.0: ad9361_spi_readm: reg 0x3 val 0xDC
    ad9361 spi0.0: ad9361_spi_readm: reg 0x3 val 0xDC
    ad9361 spi0.0: ad9361_spi_readm: reg 0x3 val 0xDC
    ad9361 spi0.0: ad9361_spi_readm: reg 0x1EB val 0x0
    ad9361 spi0.0: ad9361_spi_readm: reg 0x1EC val 0x35
    ad9361 spi0.0: ad9361_spi_readm: reg 0x1E6 val 0x1
    ad9361 spi0.0: ad9361_rx_adc_setup : BBBW 8606895 : ADCfreq 245760000
    ad9361 spi0.0: c3_msb 0x0 : c3_lsb 0x35 : r2346 0x1 :
    ad9361 spi0.0: invrc_tconst_1e6 928281, sqrt_inv_rc_tconst_1e3 963
    ad9361 spi0.0: scaled_adc_clk_1e6 384000, inv_scaled_adc_clk_1e3 2604
    ad9361 spi0.0: tmp_1e3 1000, sqrt_term_1e3 619, min_sqrt_term_1e3 1000
    ad9361 spi0.0: ad9361_spi_write: reg 0x200 val 0x0
    ad9361 spi0.0: ad9361_spi_write: reg 0x201 val 0x0
    ad9361 spi0.0: ad9361_spi_write: reg 0x202 val 0x0
    ad9361 spi0.0: ad9361_spi_write: reg 0x203 val 0x24
    ad9361 spi0.0: ad9361_spi_write: reg 0x204 val 0x24
    ad9361 spi0.0: ad9361_spi_write: reg 0x205 val 0x0
    ad9361 spi0.0: ad9361_spi_write: reg 0x206 val 0x0
    ad9361 spi0.0: ad9361_spi_write: reg 0x207 val 0x79
    ad9361 spi0.0: ad9361_spi_write: reg 0x208 val 0x55
    ad9361 spi0.0: ad9361_spi_write: reg 0x209 val 0x3A
    ad9361 spi0.0: ad9361_spi_write: reg 0x20A val 0x49
    ad9361 spi0.0: ad9361_spi_write: reg 0x20B val 0x35
    ad9361 spi0.0: ad9361_spi_write: reg 0x20C val 0x4C
    ad9361 spi0.0: ad9361_spi_write: reg 0x20D val 0x33
    ad9361 spi0.0: ad9361_spi_write: reg 0x20E val 0x0
    ad9361 spi0.0: ad9361_spi_write: reg 0x20F val 0x7C
    ad9361 spi0.0: ad9361_spi_write: reg 0x210 val 0x7C
    ad9361 spi0.0: ad9361_spi_write: reg 0x211 val 0x7C
    ad9361 spi0.0: ad9361_spi_write: reg 0x212 val 0x47
    ad9361 spi0.0: ad9361_spi_write: reg 0x213 val 0x47
    ad9361 spi0.0: ad9361_spi_write: reg 0x214 val 0x47
    ad9361 spi0.0: ad9361_spi_write: reg 0x215 val 0x4A
    ad9361 spi0.0: ad9361_spi_write: reg 0x216 val 0x4A
    ad9361 spi0.0: ad9361_spi_write: reg 0x217 val 0x4A
    ad9361 spi0.0: ad9361_spi_write: reg 0x218 val 0x2E
    ad9361 spi0.0: ad9361_spi_write: reg 0x219 val 0x98
    ad9361 spi0.0: ad9361_spi_write: reg 0x21A val 0x1B
    ad9361 spi0.0: ad9361_spi_write: reg 0x21B val 0x13
    ad9361 spi0.0: ad9361_spi_write: reg 0x21C val 0x98
    ad9361 spi0.0: ad9361_spi_write: reg 0x21D val 0x1B
    ad9361 spi0.0: ad9361_spi_write: reg 0x21E val 0x13
    ad9361 spi0.0: ad9361_spi_write: reg 0x21F val 0x98
    ad9361 spi0.0: ad9361_spi_write: reg 0x220 val 0x1B
    ad9361 spi0.0: ad9361_spi_write: reg 0x221 val 0x26
    ad9361 spi0.0: ad9361_spi_write: reg 0x222 val 0x27
    ad9361 spi0.0: ad9361_spi_write: reg 0x223 val 0x40
    ad9361 spi0.0: ad9361_spi_write: reg 0x224 val 0x40
    ad9361 spi0.0: ad9361_spi_write: reg 0x225 val 0x2C
    ad9361 spi0.0: ad9361_spi_write: reg 0x226 val 0x0
    ad9361 spi0.0: ad9361_spi_write: reg 0x227 val 0x0
    ad9361 spi0.0: ad9361_bb_dc_offset_calib
    ad9361 spi0.0: ad9361_spi_write: reg 0x193 val 0x3F
    ad9361 spi0.0: ad9361_spi_write: reg 0x190 val 0xF
    ad9361 spi0.0: ad9361_spi_write: reg 0x194 val 0x1
    ad9361 spi0.0: ad9361_spi_write: reg 0x16 val 0x1
    ad9361 spi0.0: ad9361_run_calibration: CAL Mask 0x1
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x1
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x1
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x1
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x1
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x1
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x1
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x1
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x1
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x1
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x1
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x1
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x0
    ad9361 spi0.0: ad9361_rf_dc_offset_calib : rx_freq 2400000000
    ad9361 spi0.0: ad9361_spi_write: reg 0x185 val 0x20
    ad9361 spi0.0: ad9361_spi_write: reg 0x186 val 0x32
    ad9361 spi0.0: ad9361_spi_write: reg 0x187 val 0x24
    ad9361 spi0.0: ad9361_spi_write: reg 0x188 val 0x5
    ad9361 spi0.0: ad9361_spi_write: reg 0x18B val 0x83
    ad9361 spi0.0: ad9361_spi_write: reg 0x189 val 0x30
    ad9361 spi0.0: ad9361_spi_write: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_run_calibration: CAL Mask 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x0
    ad9361 spi0.0: ad9361_spi_readm: reg 0x3 val 0xDC
    ad9361 spi0.0: ad9361_spi_readm: reg 0x3 val 0xDC
    ad9361 spi0.0: ad9361_spi_readm: reg 0x2 val 0xCC
    ad9361 spi0.0: ad9361_spi_readm: reg 0x2 val 0xCC
    ad9361 spi0.0: ad9361_tx_quad_calib : bw_tx 9000000 clkrf 30720000 clktf 30720000
    ad9361 spi0.0: Tx NCO frequency: 1920000 (BW/4: 2250000) txnco_word 1
    ad9361 spi0.0: ad9361_spi_readm: reg 0x2 val 0xCC
    ad9361 spi0.0: ad9361_spi_readm: reg 0xA3 val 0x0
    ad9361 spi0.0: ad9361_spi_write: reg 0xA3 val 0x40
    ad9361 spi0.0: ad9361_spi_write: reg 0xA9 val 0xFF
    ad9361 spi0.0: ad9361_spi_write: reg 0xA2 val 0x7F
    ad9361 spi0.0: ad9361_spi_write: reg 0xA5 val 0x3
    ad9361 spi0.0: ad9361_spi_write: reg 0xA6 val 0x3
    ad9361 spi0.0: ad9361_spi_write: reg 0xAA val 0x25
    ad9361 spi0.0: ad9361_spi_write: reg 0xA4 val 0xF0
    ad9361 spi0.0: ad9361_spi_write: reg 0xAE val 0x0
    ad9361 spi0.0: ad9361_spi_write: reg 0xA0 val 0x3A
    ad9361 spi0.0: ad9361_spi_write: reg 0xA1 val 0x7F
    ad9361 spi0.0: ad9361_spi_write: reg 0xA1 val 0x7B
    ad9361 spi0.0: ad9361_spi_write: reg 0x16 val 0x10
    ad9361 spi0.0: ad9361_run_calibration: CAL Mask 0x10
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x10
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x10
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x10
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x10
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16 val 0x0
    ad9361 spi0.0: ad9361_spi_readm: reg 0xA7 val 0x87
    ad9361 spi0.0: ad9361_spi_readm: reg 0xA8 val 0xD3
    ad9361 spi0.0: LO leakage: 1 Quadrature Calibration: 1 : rx_phase 26
    ad9361 spi0.0: ad9361_tracking_control : bbdc_track=1, rfdc_track=1, rxquad_track=1
    ad9361 spi0.0: ad9361_spi_write: reg 0x16A val 0x75
    ad9361 spi0.0: ad9361_spi_write: reg 0x16B val 0x95
    ad9361 spi0.0: ad9361_spi_write: reg 0x18B val 0xAD
    ad9361 spi0.0: ad9361_spi_readm: reg 0x16F val 0x18
    ad9361 spi0.0: ad9361_spi_write: reg 0x16F val 0x18
    ad9361 spi0.0: ad9361_spi_write: reg 0x169 val 0xCF
    ad9361 spi0.0: ad9361_pp_port_setup
    ad9361 spi0.0: ad9361_spi_write: reg 0x12 val 0x10
    ad9361 spi0.0: ad9361_spi_write: reg 0x13 val 0x1
    ad9361 spi0.0: ad9361_spi_readm: reg 0x15 val 0x4
    ad9361 spi0.0: ad9361_spi_write: reg 0x15 val 0x4
    ad9361 spi0.0: ad9361_spi_readm: reg 0x77 val 0x40
    ad9361 spi0.0: ad9361_spi_write: reg 0x77 val 0x0
    ad9361 spi0.0: ad9361_set_tx_atten : attenuation 10000 mdB tx1=1 tx2=1
    ad9361 spi0.0: ad9361_spi_readm: reg 0x7C val 0x0
    ad9361 spi0.0: ad9361_spi_write: reg 0x7C val 0x0
    ad9361_spi_writem: reg 0x74 val 0x0
    ad9361_spi_writem: reg 0x73 val 0x28
    ad9361_spi_writem: reg 0x76 val 0x0
    ad9361_spi_writem: reg 0x75 val 0x28
    ad9361 spi0.0: ad9361_spi_readm: reg 0x7C val 0x0
    ad9361 spi0.0: ad9361_spi_write: reg 0x7C val 0x40
    ad9361 spi0.0: ad9361_rssi_setup
    ad9361 spi0.0: ad9361_spi_readm: reg 0x3 val 0xDC
    ad9361 spi0.0: ad9361_spi_write: reg 0x150 val 0xDE
    ad9361 spi0.0: ad9361_spi_write: reg 0x151 val 0xBC
    ad9361 spi0.0: ad9361_spi_write: reg 0x152 val 0x88
    ad9361 spi0.0: ad9361_spi_write: reg 0x153 val 0x44
    ad9361 spi0.0: ad9361_spi_write: reg 0x154 val 0x22
    ad9361 spi0.0: ad9361_spi_write: reg 0x155 val 0x11
    ad9361 spi0.0: ad9361_spi_write: reg 0x156 val 0x3
    ad9361 spi0.0: ad9361_spi_write: reg 0x157 val 0x7
    ad9361 spi0.0: ad9361_spi_write: reg 0x158 val 0xC
    ad9361 spi0.0: ad9361_spi_readm: reg 0xA val 0xA
    ad9361 spi0.0: ad9361_spi_write: reg 0xA val 0xA
    ad9361 spi0.0: ad9361_txmon_setup
    ad9361 spi0.0: ad9361_spi_write: reg 0x6E val 0x9
    ad9361 spi0.0: ad9361_spi_write: reg 0x69 val 0xFF
    ad9361 spi0.0: ad9361_spi_readm: reg 0x6A val 0x0
    ad9361 spi0.0: ad9361_spi_write: reg 0x6A val 0x1
    ad9361 spi0.0: ad9361_spi_write: reg 0x70 val 0xC2
    ad9361 spi0.0: ad9361_spi_write: reg 0x71 val 0xC2
    ad9361 spi0.0: ad9361_spi_write: reg 0x78 val 0x94
    ad9361 spi0.0: ad9361_spi_write: reg 0x68 val 0x18
    ad9361 spi0.0: ad9361_spi_write: reg 0x67 val 0x0
    ad9361 spi0.0: ad9361_spi_readm: reg 0x17 val 0x15
    ad9361 spi0.0: Device is in 5 state, moving to a
    ad9361 spi0.0: ad9361_spi_write: reg 0x14 val 0x29
    ad9361 spi0.0: ad9361_spi_readm: reg 0x37 val 0xA
    ad9361 spi0.0: ad9361_spi_readm: reg 0x3 val 0xDC
    ad9361 spi0.0: ad9361_probe : AD936x Rev 0 successfully initialized
    ad9361 spi0.0: ad9361_spi_readm: reg 0x2 val 0xCC
    cf_axi_dds 79024000.cf-ad9361-dds-core-lpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x79024000 mapped to 0x(ptrval), probed DDS AD9361
    axi_sysid 45000000.axi-sysid-0: AXI System ID core version (1.01.a) found
    axi_sysid 45000000.axi-sysid-0: [fmcomms2] on [zc706] git branch <hdl_2021_r2> git <d0336c0f6ff88061d906621c11b616145f96358e> clean [2023-05-31 06:28:30] UTC
    fpga_manager fpga0: Xilinx Zynq FPGA Manager registered
    usbcore: registered new interface driver snd-usb-audio
    NET: Registered protocol family 10
    Segment Routing with IPv6
    sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
    NET: Registered protocol family 17
    NET: Registered protocol family 36
    Key type dns_resolver registered
    Registering SWP/SWPB emulation handler
    of-fpga-region fpga-full: FPGA Region probed
    ad9361 spi0.0: ad9361_spi_readm: reg 0x17 val 0x1A
    ad9361 spi0.0: ad9361_spi_readm: reg 0x17 val 0x1A
    ad9361 spi0.0: Device is in a state, forcing to 5
    ad9361 spi0.0: ad9361_spi_readm: reg 0x14 val 0x29
    ad9361 spi0.0: ad9361_spi_write: reg 0x14 val 0x5
    ad9361 spi0.0: ad9361_spi_write: reg 0x14 val 0xD
    ad9361 spi0.0: ad9361_spi_write: reg 0x6 val 0x4
    ad9361 spi0.0: ad9361_spi_write: reg 0x7 val 0x70
    ad9361 spi0.0: ad9361_spi_readm: reg 0x14 val 0x9
    ad9361 spi0.0: ad9361_spi_write: reg 0x14 val 0x5
    ad9361 spi0.0: ad9361_spi_write: reg 0x14 val 0x29
    ad9361 spi0.0: ad9361_set_trx_clock_chain
    ad9361 spi0.0: ad9361_set_trx_clock_chain: 983040000 245760000 122880000 61440000 30720000 30720000
    ad9361 spi0.0: ad9361_set_trx_clock_chain: 983040000 122880000 122880000 61440000 30720000 30720000
    ad9361 spi0.0: ad9361_spi_readm: reg 0x3 val 0xDC
    ad9361 spi0.0: ad9361_spi_write: reg 0x3 val 0xDC
    ad9361 spi0.0: ad9361_spi_readm: reg 0x2 val 0xCC
    ad9361 spi0.0: ad9361_spi_write: reg 0x2 val 0xCC
    ad9361 spi0.0: ad9361_spi_readm: reg 0x3 val 0xDC
    ad9361 spi0.0: ad9361_spi_readm: reg 0x3 val 0xDC
    ad9361 spi0.0: ad9361_spi_readm: reg 0x22 val 0x2
    ad9361 spi0.0: ad9361_spi_write: reg 0x22 val 0x2
    ad9361 spi0.0: ad9361_spi_readm: reg 0xFE val 0x25
    ad9361 spi0.0: ad9361_spi_write: reg 0xFE val 0x25
    ad9361 spi0.0: ad9361_spi_readm: reg 0x111 val 0xCB
    ad9361 spi0.0: ad9361_spi_write: reg 0x111 val 0xCB
    ad9361 spi0.0: ad9361_spi_readm: reg 0x3 val 0xDC
    ad9361 spi0.0: ad9361_spi_readm: reg 0x15C val 0x79
    ad9361 spi0.0: ad9361_spi_write: reg 0x15C val 0x79
    ad9361 spi0.0: ad9361_spi_readm: reg 0x128 val 0x3
    ad9361 spi0.0: ad9361_spi_write: reg 0x128 val 0x3
    ad9361 spi0.0: ad9361_spi_write: reg 0x124 val 0xF4
    ad9361 spi0.0: ad9361_spi_write: reg 0x125 val 0x3B
    ad9361 spi0.0: ad9361_spi_readm: reg 0x117 val 0x8
    ad9361 spi0.0: ad9361_spi_write: reg 0x117 val 0x8
    ad9361 spi0.0: ad9361_rssi_setup
    ad9361 spi0.0: ad9361_spi_readm: reg 0x3 val 0xDC
    ad9361 spi0.0: ad9361_spi_write: reg 0x150 val 0xDE
    ad9361 spi0.0: ad9361_spi_write: reg 0x151 val 0xBC
    ad9361 spi0.0: ad9361_spi_write: reg 0x152 val 0x88
    ad9361 spi0.0: ad9361_spi_write: reg 0x153 val 0x44
    ad9361 spi0.0: ad9361_spi_write: reg 0x154 val 0x22
    ad9361 spi0.0: ad9361_spi_write: reg 0x155 val 0x11
    ad9361 spi0.0: ad9361_spi_write: reg 0x156 val 0x3
    ad9361 spi0.0: ad9361_spi_write: reg 0x157 val 0x7
    ad9361 spi0.0: ad9361_spi_write: reg 0x158 val 0xC
    ad9361 spi0.0: ad9361_spi_readm: reg 0x44 val 0x18
    ad9361 spi0.0: ad9361_spi_readm: reg 0x43 val 0x29
    ad9361 spi0.0: ad9361_spi_readm: reg 0x42 val 0x5C
    ad9361 spi0.0: ad9361_spi_readm: reg 0x41 val 0x12
    ad9361 spi0.0: ad9361_spi_readm: reg 0xA val 0xA
    ad9361 spi0.0: ad9361_spi_readm: reg 0xA val 0xA
    ad9361 spi0.0: ad9361_spi_readm: reg 0x2 val 0xCC
    ad9361 spi0.0: ad9361_spi_readm: reg 0x2 val 0xCC
    ad9361 spi0.0: ad9361_spi_readm: reg 0x2 val 0xCC
    ad9361 spi0.0: ad9361_spi_readm: reg 0x2 val 0xCC
    ad9361 spi0.0: ad9361_spi_readm: reg 0x3 val 0xDC
    ad9361 spi0.0: ad9361_spi_readm: reg 0x3 val 0xDC
    ad9361 spi0.0: ad9361_spi_readm: reg 0x3 val 0xDC
    ad9361 spi0.0: ad9361_spi_readm: reg 0x3 val 0xDC
    ad9361 spi0.0: ad9361_auxadc_setup
    ad9361 spi0.0: ad9361_spi_write: reg 0xB val 0xCE
    ad9361 spi0.0: ad9361_spi_write: reg 0xC val 0x0
    ad9361 spi0.0: ad9361_spi_write: reg 0xD val 0x5
    ad9361 spi0.0: ad9361_spi_write: reg 0xF val 0x0
    ad9361 spi0.0: ad9361_spi_write: reg 0x1C val 0x18
    ad9361 spi0.0: ad9361_spi_write: reg 0x1D val 0x0
    ad9361 spi0.0: ad9361_spi_readm: reg 0x17 val 0x1A
    ad9361 spi0.0: Device is in a state, forcing to 5
    ad9361 spi0.0: ad9361_spi_readm: reg 0x14 val 0x29
    ad9361 spi0.0: ad9361_spi_write: reg 0x14 val 0x5
    ad9361 spi0.0: ad9361_spi_write: reg 0x14 val 0xD
    ad9361 spi0.0: ad9361_spi_readm: reg 0x14 val 0x9
    ad9361 spi0.0: ad9361_spi_write: reg 0x14 val 0x5
    ad9361 spi0.0: ad9361_spi_write: reg 0x14 val 0x29
    cf_axi_adc 79020000.cf-ad9361-lpc: ADI AIM (10.02.b) at 0x79020000 mapped to 0x(ptrval) probed ADC AD9361 as MASTER
    input: gpio_keys as /devices/soc0/gpio_keys/input/input0
    of_cfs_init
    of_cfs_init: OK
    ALSA device list:
    No soundcards found.
    RAMDISK: gzip image found at block 0
    using deprecated initrd support, will be removed in 2021.
    EXT4-fs (ram0): mounting ext2 file system using the ext4 subsystem
    EXT4-fs (ram0): mounted filesystem without journal. Opts: (null)
    VFS: Mounted root (ext2 filesystem) on device 1:0.
    random: sshd: uninitialized urandom read (32 bytes read)
    ad9361 spi0.0: ad9361_spi_readm: reg 0x17 val 0x1A
    ad9361 spi0.0: ad9361_spi_readm: reg 0x17 val 0x1A
    ad9361 spi0.0: Device is in a state, forcing to 5
    ad9361 spi0.0: ad9361_spi_readm: reg 0x14 val 0x29
    ad9361 spi0.0: ad9361_spi_write: reg 0x14 val 0x5
    ad9361 spi0.0: ad9361_spi_write: reg 0x14 val 0xD
    ad9361 spi0.0: ad9361_spi_write: reg 0x6 val 0x4
    ad9361 spi0.0: ad9361_spi_write: reg 0x7 val 0x70
    ad9361 spi0.0: ad9361_spi_readm: reg 0x14 val 0x9
    ad9361 spi0.0: ad9361_spi_write: reg 0x14 val 0x5
    ad9361 spi0.0: ad9361_spi_write: reg 0x14 val 0x29
    ad9361 spi0.0: ad9361_spi_readm: reg 0x17 val 0x1A
    ad9361 spi0.0: ad9361_spi_readm: reg 0x17 val 0x1A
    ad9361 spi0.0: Device is in a state, forcing to 5
    ad9361 spi0.0: ad9361_spi_readm: reg 0x14 val 0x29
    ad9361 spi0.0: ad9361_spi_write: reg 0x14 val 0x5
    ad9361 spi0.0: ad9361_spi_write: reg 0x14 val 0xD
    ad9361 spi0.0: ad9361_spi_write: reg 0x6 val 0x4
    ad9361 spi0.0: ad9361_spi_write: reg 0x7 val 0x70
    ad9361 spi0.0: ad9361_spi_readm: reg 0x14 val 0x9
    ad9361 spi0.0: ad9361_spi_write: reg 0x14 val 0x5
    ad9361 spi0.0: ad9361_spi_write: reg 0x14 val 0x29
    zynq>

  • Can you run the bist_timing_analysis and provide output as well? Note that not all devices will appear in the sysfs debug as they all won't have debug attrs.

    -Travis

  • zynq> cd iio\:device0
    zynq> echo 1 > bist_random: crng init done
    zynq> echo 1 > bist_timing_analysis
    zynq>
    zynq> cat bist_t
    bist_timing_analysis bist_tone
    zynq> cat bist_timing_analysis
    ad9361_spi_writem: reg 0x74 val 0x1
    ad9361_spi_writem: reg 0x73 val 0x67
    ad9361_spi_writem: reg 0x76 val 0x1
    ad9361_spi_writem: reg 0x75 val 0x67
    ad9361_spi_writem: reg 0x74 val 0x0
    ad9361_spi_writem: reg 0x73 val 0x28
    ad9361_spi_writem: reg 0x76 val 0x0
    ad9361_spi_writem: reg 0x75 val 0x28
    CLK: 30720000 Hz 'o' = PASS
    DC0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
    0:. . . . . . . . . . . . . . . .
    1:. . . . . . . . . . . . . . . .
    2:. . . . . . . . . . . . . . . .
    3:. . . . . . . . . . . . . . . .
    4:. . . . . . . . . . . . . . . .
    5:. . . . . . . . . . . . . . . .
    6:. . . . . . . . . . . . . . . .
    7:. . . . . . . . . . . . . . . .
    8:. . . . . . . . . . . . . . . .
    9:. . . . . . . . . . . . . . . .
    a:. . . . . . . . . . . . . . . .
    b:. . . . . . . . . . . . . . . .
    c:. . . . . . . . . . . . . . . .
    d:. . . . . . . . . . . . . . . .
    e:. . . . . . . . . . . . . . . .
    f:. . . . . . . . . . . . . . . .

    zynq> cat bist_timing_analysis

  • The next thing I would check is access to the transceiver interface core. Can you verify the memory locations of the DAC-DDS and ADC nodes.

    Can you also verify No-OS with this exact bitstream.

    -Travis 

  • no-os works with this modified firmware, the addresses are correct (corresponding to device_tree, standard).
    I think this problem is due to ddr, I have 512 MB, when other boards have 1 GB each, Linux eats up about 240-300 MB, I think dma cannot transfer data correctly.

  • I want to show how the firmware works, where digital tune works as it should, I did not change Linux.


    Starting kernel ...

    Booting Linux on physical CPU 0x0
    Linux version 5.10.0-98755-g7809af2d00a1-dirty (vasiliy@vasiliyPC) (arm-linux-gnueabihf-gcc (Ubuntu 9.4.0-1ubuntu1~20.04.1) 9.4.0, GNU ld (GNU Binutils for Ubuntu) 2.34) #4 SMP PREEMPT T hu Jun 1 15:32:39 MSK 2023
    CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
    CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
    OF: fdt: Machine model: xlnx,zynq-7000
    earlycon: cdns0 at MMIO 0xe0000000 (options '115200n8')
    printk: bootconsole [cdns0] enabled
    Memory policy: Data cache writealloc
    cma: Reserved 256 MiB at 0x0e800000
    Zone ranges:
    Normal [mem 0x0000000000000000-0x000000001fffffff]
    HighMem empty
    Movable zone start for each node
    Early memory node ranges
    node 0: [mem 0x0000000000000000-0x000000001fffffff]
    Initmem setup node 0 [mem 0x0000000000000000-0x000000001fffffff]
    percpu: Embedded 15 pages/cpu s29580 r8192 d23668 u61440
    Built 1 zonelists, mobility grouping on. Total pages: 130048
    Kernel command line: earlycon
    Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
    Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
    mem auto-init: stack:off, heap alloc:off, heap free:off
    Memory: 242660K/524288K available (6144K kernel code, 661K rwdata, 1948K rodata, 1024K init, 133K bss, 19484K reserved, 262144K cma-reserved, 0K highmem)
    rcu: Preemptible hierarchical RCU implementation.
    rcu: RCU event tracing is enabled.
    rcu: RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
    Trampoline variant of Tasks RCU enabled.
    rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
    rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
    NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
    efuse mapped to (ptrval)
    slcr mapped to (ptrval)
    L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
    L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
    L2C-310 erratum 769419 enabled
    L2C-310 enabling early BRESP for Cortex-A9
    L2C-310 full line of zeros enabled for Cortex-A9
    L2C-310 ID prefetch enabled, offset 1 lines
    L2C-310 dynamic clock gating enabled, standby mode enabled
    L2C-310 cache controller enabled, 8 ways, 512 kB
    L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
    random: get_random_bytes called from start_kernel+0x2d8/0x4d8 with crng_init=0
    zynq_clock_init: clkc starts at (ptrval)
    Zynq clock init
    sched_clock: 64 bits at 399MHz, resolution 2ns, wraps every 4398046511103ns
    clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x5c4093a7d1, max_idle_ns: 440795210635 ns
    Switching to timer-based delay loop, resolution 2ns
    clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 447945978 ns
    timer #0 at (ptrval), irq=25
    Console: colour dummy device 80x30
    printk: console [tty0] enabled
    printk: bootconsole [cdns0] disabled
    Booting Linux on physical CPU 0x0
    Linux version 5.10.0-98755-g7809af2d00a1-dirty (vasiliy@vasiliyPC) (arm-linux-gnueabihf-gcc (Ubuntu 9.4.0-1ubuntu1~20.04.1) 9.4.0, GNU ld (GNU Binutils for Ubuntu) 2.34) #4 SMP PREEMPT T hu Jun 1 15:32:39 MSK 2023
    CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
    CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
    OF: fdt: Machine model: xlnx,zynq-7000
    earlycon: cdns0 at MMIO 0xe0000000 (options '115200n8')
    printk: bootconsole [cdns0] enabled
    Memory policy: Data cache writealloc
    cma: Reserved 256 MiB at 0x0e800000
    Zone ranges:
    Normal [mem 0x0000000000000000-0x000000001fffffff]
    HighMem empty
    Movable zone start for each node
    Early memory node ranges
    node 0: [mem 0x0000000000000000-0x000000001fffffff]
    Initmem setup node 0 [mem 0x0000000000000000-0x000000001fffffff]
    percpu: Embedded 15 pages/cpu s29580 r8192 d23668 u61440
    Built 1 zonelists, mobility grouping on. Total pages: 130048
    Kernel command line: earlycon
    Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
    Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
    mem auto-init: stack:off, heap alloc:off, heap free:off
    Memory: 242660K/524288K available (6144K kernel code, 661K rwdata, 1948K rodata, 1024K init, 133K bss, 19484K reserved, 262144K cma-reserved, 0K highmem)
    rcu: Preemptible hierarchical RCU implementation.
    rcu: RCU event tracing is enabled.
    rcu: RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
    Trampoline variant of Tasks RCU enabled.
    rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
    rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
    NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
    efuse mapped to (ptrval)
    slcr mapped to (ptrval)
    L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
    L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
    L2C-310 erratum 769419 enabled
    L2C-310 enabling early BRESP for Cortex-A9
    L2C-310 full line of zeros enabled for Cortex-A9
    L2C-310 ID prefetch enabled, offset 1 lines
    L2C-310 dynamic clock gating enabled, standby mode enabled
    L2C-310 cache controller enabled, 8 ways, 512 kB
    L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
    random: get_random_bytes called from start_kernel+0x2d8/0x4d8 with crng_init=0
    zynq_clock_init: clkc starts at (ptrval)
    Zynq clock init
    sched_clock: 64 bits at 399MHz, resolution 2ns, wraps every 4398046511103ns
    clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x5c4093a7d1, max_idle_ns: 440795210635 ns
    Switching to timer-based delay loop, resolution 2ns
    clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 447945978 ns
    timer #0 at (ptrval), irq=25
    Console: colour dummy device 80x30
    printk: console [tty0] enabled
    printk: bootconsole [cdns0] disabled
    Calibrating delay loop (skipped), value calculated using timer frequency.. 799.99 BogoMIPS (lpj=3999999)
    pid_max: default: 32768 minimum: 301
    Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
    Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
    CPU: Testing write buffer coherency: ok
    CPU0: Spectre v2: using BPIALL workaround
    CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
    Setting up static identity map for 0x100000 - 0x100060
    rcu: Hierarchical SRCU implementation.
    smp: Bringing up secondary CPUs ...
    CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
    CPU1: Spectre v2: using BPIALL workaround
    smp: Brought up 1 node, 2 CPUs
    SMP: Total of 2 processors activated (1599.99 BogoMIPS).
    CPU: All CPU(s) started in SVC mode.
    devtmpfs: initialized
    VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
    clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
    futex hash table entries: 512 (order: 3, 32768 bytes, linear)
    pinctrl core: initialized pinctrl subsystem
    NET: Registered protocol family 16
    DMA: preallocated 256 KiB pool for atomic coherent allocations
    thermal_sys: Registered thermal governor 'step_wise'
    cpuidle: using governor ladder
    hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
    hw-breakpoint: maximum watchpoint size is 4 bytes.
    zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0x(ptrval)
    e0000000.serial: ttyPS0 at MMIO 0xe0000000 (irq = 33, base_baud = 6249999) is a xuartps
    printk: console [ttyPS0] enabled
    SCSI subsystem initialized
    usbcore: registered new interface driver usbfs
    usbcore: registered new interface driver hub
    usbcore: registered new device driver usb
    FPGA manager framework
    clocksource: Switched to clocksource arm_global_timer
    NET: Registered protocol family 2
    tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes, linear)
    TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
    TCP bind hash table entries: 4096 (order: 3, 32768 bytes, linear)
    TCP: Hash tables configured (established 4096 bind 4096)
    UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
    UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
    NET: Registered protocol family 1
    Trying to unpack rootfs image as initramfs...
    Freeing initrd memory: 2724K
    hw perfevents: no interrupt-affinity property for /pmu@f8891000, guessing.
    hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
    Initialise system trusted keyrings
    workingset: timestamp_bits=30 max_order=17 bucket_order=0
    jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
    Key type asymmetric registered
    Asymmetric key parser 'x509' registered
    io scheduler mq-deadline registered
    io scheduler kyber registered
    zynq-pinctrl 700.pinctrl: zynq pinctrl initialized
    brd: module loaded
    loop: module loaded
    libphy: Fixed MDIO Bus: probed
    usbcore: registered new interface driver rt2500usb
    usbcore: registered new interface driver rt73usb
    usbcore: registered new interface driver rt2800usb
    usbcore: registered new interface driver rtl8187
    usbcore: registered new interface driver rtl8192cu
    usbcore: registered new interface driver rtl8xxxu
    usbcore: registered new interface driver r8152
    usbcore: registered new interface driver lan78xx
    usbcore: registered new interface driver asix
    usbcore: registered new interface driver ax88179_178a
    usbcore: registered new interface driver cdc_ether
    usbcore: registered new interface driver dm9601
    usbcore: registered new interface driver smsc75xx
    usbcore: registered new interface driver smsc95xx
    usbcore: registered new interface driver rndis_host
    ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
    usbcore: registered new interface driver usb-storage
    usbcore: registered new interface driver usbserial_generic
    usbserial: USB Serial support registered for generic
    usbcore: registered new interface driver ftdi_sio
    usbserial: USB Serial support registered for FTDI USB Serial Device
    i2c /dev entries driver
    cdns-wdt f8005000.watchdog: Xilinx Watchdog Timer with timeout 10s
    Xilinx Zynq CpuIdle Driver started
    ledtrig-cpu: registered to indicate activity on CPUs
    hid: raw HID events driver (C) Jiri Kosina
    usbcore: registered new interface driver usbhid
    usbhid: USB HID core driver
    usbcore: registered new interface driver r8712u
    usbcore: registered new interface driver r8188eu
    ad9361 spi1.0: ad9361_probe : enter (ad9361)
    ad9361_spi_writem: reg 0x4A val 0x35
    ad9361_spi_writem: reg 0x49 val 0x5B
    ad9361_spi_writem: reg 0x48 val 0xE8
    random: fast init done
    ad9361_spi_writem: reg 0x235 val 0x0
    ad9361_spi_writem: reg 0x234 val 0x0
    ad9361_spi_writem: reg 0x233 val 0x0
    ad9361_spi_writem: reg 0x232 val 0x0
    ad9361_spi_writem: reg 0x231 val 0x78
    ad9361_spi_writem: reg 0x275 val 0x3F
    ad9361_spi_writem: reg 0x274 val 0xFF
    ad9361_spi_writem: reg 0x273 val 0xF9
    ad9361_spi_writem: reg 0x272 val 0x0
    ad9361_spi_writem: reg 0x271 val 0x7A
    ad9361_spi_writem: reg 0x74 val 0x0
    ad9361_spi_writem: reg 0x73 val 0x0
    ad9361_spi_writem: reg 0x76 val 0x1
    ad9361_spi_writem: reg 0x75 val 0x67
    ad9361 spi1.0: ad9361_probe : AD936x Rev 0 successfully initialized
    cf_axi_dds 79024000.cf-ad9361-dds-core-lpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x79024000 mapped to 0x(ptrval), probed DDS AD9361
    fpga_manager fpga0: Xilinx Zynq FPGA Manager registered
    NET: Registered protocol family 17
    lib80211: common routines for IEEE802.11 drivers
    Registering SWP/SWPB emulation handler
    Loading compiled-in X.509 certificates
    ad9361_spi_writem: reg 0x74 val 0x1
    ad9361_spi_writem: reg 0x73 val 0x67
    ad9361_spi_writem: reg 0x76 val 0x1
    ad9361_spi_writem: reg 0x75 val 0x67
    ad9361_spi_writem: reg 0x4A val 0x35
    ad9361_spi_writem: reg 0x49 val 0x5B
    ad9361_spi_writem: reg 0x48 val 0xE8
    SAMPL CLK: 25000000 tuning: RX
    0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
    0:# o o o o o o o o o o o o o o o
    1:# # # # # # # # # # # # # # # #
    ad9361_spi_writem: reg 0x4A val 0x35
    ad9361_spi_writem: reg 0x49 val 0x5B
    ad9361_spi_writem: reg 0x48 val 0xE8
    SAMPL CLK: 40000000 tuning: RX
    0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
    0:# o o o o o o o o o o o o o o o
    1:# # # # # # # # # # # # # # # #
    ad9361_spi_writem: reg 0x4A val 0x35
    ad9361_spi_writem: reg 0x49 val 0x5B
    ad9361_spi_writem: reg 0x48 val 0xE8
    SAMPL CLK: 61440000 tuning: RX
    0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
    0:# o o o o o o o o o o o o o o #
    1:# # # # # # # # # # # # # # # #
    SAMPL CLK: 61440000 tuning: RX
    0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
    0:# o o o o o o o O o o o o o o #
    1:# # # # # # # # # # # # # # # #
    ad9361_spi_writem: reg 0x4A val 0x35
    ad9361_spi_writem: reg 0x49 val 0x5B
    ad9361_spi_writem: reg 0x48 val 0xE8
    SAMPL CLK: 25000000 tuning: TX
    0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
    0:# # # # # # # # # # # # # # # #
    1:# o o o o o o o o o o o o o o o
    ad9361_spi_writem: reg 0x4A val 0x35
    ad9361_spi_writem: reg 0x49 val 0x5B
    ad9361_spi_writem: reg 0x48 val 0xE8
    SAMPL CLK: 40000000 tuning: TX
    0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
    0:# # # # # # # # # # # # # # # #
    1:# o o o o o o o o o o o o o o o
    ad9361_spi_writem: reg 0x4A val 0x35
    ad9361_spi_writem: reg 0x49 val 0x5B
    ad9361_spi_writem: reg 0x48 val 0xE8
    SAMPL CLK: 61440000 tuning: TX
    0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
    0:# # # # # # # # # # # # # # # #
    1:# o o o o o o o o o o o o o o #
    SAMPL CLK: 61440000 tuning: TX
    0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
    0:# # # # # # # # # # # # # # # #
    1:# o o o o o o o O o o o o o o #
    ad9361_spi_writem: reg 0x74 val 0x0
    ad9361_spi_writem: reg 0x73 val 0x0
    ad9361_spi_writem: reg 0x76 val 0x1
    ad9361_spi_writem: reg 0x75 val 0x67
    cf_axi_adc 79020000.cf-ad9361-lpc: ADI AIM (10.02.b) at 0x79020000 mapped to 0x(ptrval) probed ADC AD9364 as MASTER
    cfg80211: Loading compiled-in X.509 certificates for regulatory database
    cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
    platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
    cfg80211: failed to load regulatory.db
    Freeing unused kernel memory: 1024K
    Run /init as init process
    Starting syslogd: OK
    Starting klogd: OK
    Running sysctl: OK
    Saving random seed: random: dd: uninitialized urandom read (512 bytes read)
    OK
    Starting IIO Server Daemon

    Welcome to scat_z_AD
    scat_z login:

  • I'm alittle confused... is your system working now?

    -Travis

  • no, this is another BOOT.bin that I don't know what firmware is in, I just want to show that the problem is most likely in the firmware.

  • problem solved, the problem was in fsbl. Thank you.

  • Hello, I have encountered the same issue as you. The error doesn't occur in no-os, but it appears when using the Linux system with the latest hardware and code. I'm wondering if there might be an issue with the FSBL. I tried replacing it with the FSBL from Vitis, but it didn't have any effect.

Reply
  • Hello, I have encountered the same issue as you. The error doesn't occur in no-os, but it appears when using the Linux system with the latest hardware and code. I'm wondering if there might be an issue with the FSBL. I tried replacing it with the FSBL from Vitis, but it didn't have any effect.

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