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ad9361, digital tuning error on linux

Category: Hardware
Product Number: ad9361

A riddle from Jacques Fresco.
This error occurs. When I use NO-OS, there is no such error.
ad9361_spi_writem: reg 0x74 val 0x1
ad9361_spi_writem: reg 0x73 val 0x67
ad9361_spi_writem: reg 0x76 val 0x1
ad9361_spi_writem: reg 0x75 val 0x67
ad9361_spi_writem: reg 0x4A val 0x35
ad9361_spi_writem: reg 0x49 val 0x5B
ad9361_spi_writem: reg 0x48 val 0xE8
SAMPL CLK: 25000000 tuning: RX
0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:# # # # # # # # # # # # # # # #
1:# # # # # # # # # # # # # # # #
ad9361_spi_writem: reg 0x4A val 0x35
ad9361_spi_writem: reg 0x49 val 0x5B
ad9361_spi_writem: reg 0x48 val 0xE8
SAMPL CLK: 40000000 tuning: RX
0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:# # # # # # # # # # # # # # # #
1:# # # # # # # # # # # # # # # #
ad9361_spi_writem: reg 0x4A val 0x35
ad9361_spi_writem: reg 0x49 val 0x5B
ad9361_spi_writem: reg 0x48 val 0xE8
SAMPL CLK: 61440000 tuning: RX
0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:# # # # # # # # # # # # # # # #
1:# # # # # # # # # # # # # # # #
SAMPL CLK: 61440000 tuning: RX
0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:# # # # # # # # # # # # # # # #
1:# # # # # # # # # # # # # # # #
ad9361 spi2.0: ad9361_dig_tune_delay: Tuning RX FAILED!
ad9361_spi_writem: reg 0x74 val 0x0
ad9361_spi_writem: reg 0x73 val 0x28
ad9361_spi_writem: reg 0x76 val 0x0
ad9361_spi_writem: reg 0x75 val 0x28
cf_axi_adc: probe of 79020000.cf-ad9361-lpc failed with error -5

Here's a tree:

ptm@f889c000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0xf889c000 0x1000>;
clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
cpu = <&cpu0>;
out-ports {
port {
ptm0_out_port: endpoint {
remote-endpoint = <&funnel0_in_port0>;
};
};
};
};

ptm@f889d000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0xf889d000 0x1000>;
clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
cpu = <&cpu1>;
out-ports {
port {
ptm1_out_port: endpoint {
remote-endpoint = <&funnel0_in_port1>;
};
};
};
};
};
};
# 3 "zynq.dtsi" 2
/ {
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
aliases {
serial0 = &uart0;
spi0 = &qspi;
// spi1 = &axi_spi;
spi2 = &spi0;
};
memory {
device_type = "memory";
reg = <0x0 0x20000000>;
};
};

/ {
cpus {
cpu@0 {
operating-points = <800000 1000000 400000 1000000 200000 1000000>;
};
};
};
&gpio0 {
emio-gpio-width = <25>;
gpio-mask-high = <0x0>;
gpio-mask-low = <0x5600>;
};
&intc {
num_cpus = <2>;
num_interrupts = <96>;
};
&qspi {
is-dual = <0>;
num-cs = <0x1>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
status = "okay";
};
&sdhci0 {
status = "okay";
xlnx,has-cd = <0x1>;
xlnx,has-power = <0x0>;
xlnx,has-wp = <0x0>;
};
&spi0 {
is-decoded-cs = <0>;
num-cs = <0x3>;
status = "okay";
};
&uart0 {
cts-override ;
device_type = "serial";
port-number = <0>;
status = "okay";
};
&clkc {
fclk-enable = <0x3>;
ps-clk-frequency = <33333333>;
};
# 9 "zynq-antsdre200.dtsi" 2
# 1 "/home/vasiliy/scat_lib/zynq_timestamping/ant_device_tree/generate/include/dt-bindings/input/input.h" 1
# 13 "/home/vasiliy/scat_lib/zynq_timestamping/ant_device_tree/generate/include/dt-bindings/input/input.h"
# 1 "/home/vasiliy/scat_lib/zynq_timestamping/ant_device_tree/generate/include/dt-bindings/input/linux-event-codes.h" 1
# 14 "/home/vasiliy/scat_lib/zynq_timestamping/ant_device_tree/generate/include/dt-bindings/input/input.h" 2
# 10 "zynq-antsdre200.dtsi" 2
# 1 "/home/vasiliy/scat_lib/zynq_timestamping/ant_device_tree/generate/include/dt-bindings/gpio/gpio.h" 1
# 11 "zynq-antsdre200.dtsi" 2
# 1 "/home/vasiliy/scat_lib/zynq_timestamping/ant_device_tree/generate/include/dt-bindings/interrupt-controller/irq.h" 1
# 12 "zynq-antsdre200.dtsi" 2


# 1 "/home/vasiliy/scat_lib/zynq_timestamping/ant_device_tree/generate/include/dt-bindings/iio/adc/adi,ad9361.h" 1
# 15 "zynq-antsdre200.dtsi" 2

/ {
// model = "MicroPhase ANTSDR E200";
// memory {
// device_type = "memory";
// reg = <0x00000000 0x20000000>;
// };

// aliases {
// ethernet0 = &gem0;
// serial0 = &uart0;
// spi0 = &qspi;
// mmc0 = &sdhci0;
// };

// chosen {

// stdout-path = "/amba@0/uart@E0000000";
// };


clocks {
ad9361_clkin: clock@0 {
compatible = "fixed-clock";

clock-frequency = <40000000>;
clock-output-names = "ad9361_ext_refclk";
#clock-cells = <0>;
};
};

// ltc2630 {
// compatible = "microphase,ltc2630";
// status = "okay";
// ext_ref_locked = <&gpio0 68 1>;
// ext_ref_ispps = <&gpio0 69 0>;
// ref_sel = <&gpio0 70 0>;
// };


};


&sdhci0 {
status = "okay";
xlnx,has-cd = <0x0>;
xlnx,has-power = <0x0>;
xlnx,has-wp = <0x0>;
};

&watchdog0 {
status = "okay";
reset-on-timeout;
};

&uart0 {
status = "okay";
};
# 110 "zynq-antsdre200.dtsi"
&gem0 {
status = "okay";

phy-handle = <&phy0>;
phy-mode = "rgmii-rxid";
xlnx,has-mdio = <0x1>;
gmii2rgmii-phy-handle = <&gmii_to_rgmii_0>;

phy0: phy@1 {
compatible = "ethernet-phy-id011c.c916";
device_type = "ethernet-phy";
reg = <0x1>;

};

gmii_to_rgmii_0: gmiitorgmii@8 {
compatible = "xlnx,gmii-to-rgmii-1.0";
reg = <0x8>;
phy-handle = <&phy0>;
};

};

&qspi {
status = "okay";
is-dual = <0>;
num-cs = <1>;
primary_flash: ps7-qspi@0 {
#address-cells = <1>;
#size-cells = <1>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
compatible = "n25q256a", "n25q512a", "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <50000000>;
partition@qspi-fsbl-uboot {
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@qspi-uboot-env {
label = "qspi-uboot-env";
reg = <0x100000 0x20000>;
};
partition@qspi-nvmfs {
label = "qspi-nvmfs";
reg = <0x120000 0xE0000>;
};
partition@qspi-linux {
label = "qspi-linux";
reg = <0x200000 0x1E00000>;
};
};
};

&adc {
xlnx,channels {
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
};
};
};

/ {
fpga_axi: fpga-axi@0 {
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;

rx_dma: dma@7c400000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x7c400000 0x1000>;
#dma-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <0 57 4>;
clocks = <&clkc 16>;

adi,channels {
#size-cells = <0>;
#address-cells = <1>;

dma-channel@0 {
reg = <0>;
adi,source-bus-width = <32>;
adi,source-bus-type = <2>;
adi,destination-bus-width = <64>;
adi,destination-bus-type = <0>;
};
};
};

tx_dma: dma@7c420000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x7c420000 0x1000>;
#dma-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <0 56 4>;
clocks = <&clkc 16>;

adi,channels {
#size-cells = <0>;
#address-cells = <1>;

dma-channel@0 {
reg = <0>;
adi,source-bus-width = <64>;
adi,source-bus-type = <0>;
adi,destination-bus-width = <32>;
adi,destination-bus-type = <2>;
};
};
};

cf_ad9364_adc_core_0: cf-ad9361-lpc@79020000 {
compatible = "adi,axi-ad9361-6.00.a";
reg = <0x79020000 0x6000>;
dmas = <&rx_dma 0>;
dma-names = "rx";
spibus-connected = <&adc0_ad9361>;
adi,axi-decimation-core-available;
};

cf_ad9364_dac_core_0: cf-ad9361-dds-core-lpc@79024000 {
compatible = "adi,axi-ad9361-dds-6.00.a";
reg = <0x79024000 0x1000>;
clocks = <&adc0_ad9361 13>;
clock-names = "sampl_clk";
dmas = <&tx_dma 0>;
dma-names = "tx";
adi,axi-interpolation-core-available;
adi,axi-dds-default-scale = <0>;
};

mwipcore@43c00000 {
compatible = "mathworks,mwipcore-axi4lite-v1.00";
reg = <0x43c00000 0xffff>;
};
};
};

&spi0 {
status = "okay";

adc0_ad9361: ad9361-phy@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi,ad9361";

reg = <0>;

/* SPI Setup */
spi-cpha;
spi-max-frequency = <10000000>;

/* Clocks */
clocks = <&ad9361_clkin 0>;
clock-names = "ad9361_ext_refclk";
clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
#clock-cells = <1>;

// adi,debug-mode-enable;
/* Digital Interface Control */

/* adi,digital-interface-tune-skip-mode:
* 0 = TUNE RX&TX
* 1 = SKIP TX
* 2 = SKIP ALL
*/
adi,digital-interface-tune-skip-mode = <0>;

adi,pp-tx-swap-enable;
adi,pp-rx-swap-enable;
adi,rx-frame-pulse-mode-enable;
adi,lvds-mode-enable;
adi,lvds-bias-mV = <150>;
adi,lvds-rx-onchip-termination-enable;
adi,rx-data-delay = <4>;
adi,tx-fb-clock-delay = <7>;

//adi,fdd-rx-rate-2tx-enable;

adi,dcxo-coarse-and-fine-tune = <8 5920>;
//adi,xo-disable-use-ext-refclk-enable;

/* Mode Setup */

adi,2rx-2tx-mode-enable;
//adi,split-gain-table-mode-enable;

/* ENSM Mode */
adi,frequency-division-duplex-mode-enable;
//adi,ensm-enable-pin-pulse-mode-enable;
//adi,ensm-enable-txnrx-control-enable;


/* adi,rx-rf-port-input-select:
* 0 = (RX1A_N & RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced
* 1 = (RX1B_N & RX1B_P) and (RX2B_N & RX2B_P) enabled; balanced
* 2 = (RX1C_N & RX1C_P) and (RX2C_N & RX2C_P) enabled; balanced
*
* 3 = RX1A_N and RX2A_N enabled; unbalanced
* 4 = RX1A_P and RX2A_P enabled; unbalanced
* 5 = RX1B_N and RX2B_N enabled; unbalanced
* 6 = RX1B_P and RX2B_P enabled; unbalanced
* 7 = RX1C_N and RX2C_N enabled; unbalanced
* 8 = RX1C_P and RX2C_P enabled; unbalanced
*/

adi,rx-rf-port-input-select = <0>; /* (RX1A_N & RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced */

/* adi,tx-rf-port-input-select:
* 0 TX1A, TX2A
* 1 TX1B, TX2B
*/

adi,tx-rf-port-input-select = <0>; /* TX1A, TX2A */
//adi,update-tx-gain-in-alert-enable;
adi,tx-attenuation-mdB = <10000>;
adi,tx-lo-powerdown-managed-enable;

adi,rf-rx-bandwidth-hz = <18000000>;
adi,rf-tx-bandwidth-hz = <18000000>;
adi,rx-synthesizer-frequency-hz = /bits/ 64 <2400000000>;
adi,tx-synthesizer-frequency-hz = /bits/ 64 <2400000000>;

/* BBPLL ADC R2CLK R1CLK CLKRF RSAMPL */
adi,rx-path-clock-frequencies = <983040000 245760000 122880000 61440000 30720000 30720000>;
/* BBPLL DAC T2CLK T1CLK CLKTF TSAMPL */
adi,tx-path-clock-frequencies = <983040000 122880000 122880000 61440000 30720000 30720000>;

/* Gain Control */

//adi,gaintable-name = "ad9361_std_gaintable";

/* adi,gc-rx[1|2]-mode:
* 0 = RF_GAIN_MGC
* 1 = RF_GAIN_FASTATTACK_AGC
* 2 = RF_GAIN_SLOWATTACK_AGC
* 3 = RF_GAIN_HYBRID_AGC
*/

adi,gc-rx1-mode = <2>;
adi,gc-rx2-mode = <2>;
adi,gc-adc-ovr-sample-size = <4>; /* sum 4 samples */
adi,gc-adc-small-overload-thresh = <47>; /* sum of squares */
adi,gc-adc-large-overload-thresh = <58>; /* sum of squares */
adi,gc-lmt-overload-high-thresh = <800>; /* mV */
adi,gc-lmt-overload-low-thresh = <704>; /* mV */
adi,gc-dec-pow-measurement-duration = <8192>; /* 0..524288 Samples */
adi,gc-low-power-thresh = <24>; /* 0..-64 dBFS vals are set pos */
//adi,gc-dig-gain-enable;
//adi,gc-max-dig-gain = <15>;

/* Manual Gain Control Setup */

//adi,mgc-rx1-ctrl-inp-enable; /* uncomment to use ctrl inputs */
//adi,mgc-rx2-ctrl-inp-enable; /* uncomment to use ctrl inputs */
adi,mgc-inc-gain-step = <2>;
adi,mgc-dec-gain-step = <2>;

/* adi,mgc-split-table-ctrl-inp-gain-mode:
* (relevant if adi,split-gain-table-mode-enable is set)
* 0 = AGC determine this
* 1 = only in LPF
* 2 = only in LMT
*/

adi,mgc-split-table-ctrl-inp-gain-mode = <0>;

/* Automatic Gain Control Setup */

adi,agc-attack-delay-extra-margin-us= <1>; /* us */
adi,agc-outer-thresh-high = <5>; /* -dBFS */
adi,agc-outer-thresh-high-dec-steps = <2>; /* 0..15 */
adi,agc-inner-thresh-high = <10>; /* -dBFS */
adi,agc-inner-thresh-high-dec-steps = <1>; /* 0..7 */
adi,agc-inner-thresh-low = <12>; /* -dBFS */
adi,agc-inner-thresh-low-inc-steps = <1>; /* 0..7 */
adi,agc-outer-thresh-low = <18>; /* -dBFS */
adi,agc-outer-thresh-low-inc-steps = <2>; /* 0..15 */

adi,agc-adc-small-overload-exceed-counter = <10>; /* 0..15 */
adi,agc-adc-large-overload-exceed-counter = <10>; /* 0..15 */
adi,agc-adc-large-overload-inc-steps = <2>; /* 0..15 */
//adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable;
adi,agc-lmt-overload-large-exceed-counter = <10>; /* 0..15 */
adi,agc-lmt-overload-small-exceed-counter = <10>; /* 0..15 */
adi,agc-lmt-overload-large-inc-steps = <2>; /* 0..7 */
//adi,agc-dig-saturation-exceed-counter = <3>; /* 0..15 */
//adi,agc-dig-gain-step-size = <4>; /* 1..8 */

//adi,agc-sync-for-gain-counter-enable;
adi,agc-gain-update-interval-us = <1000>; /* 1ms */
//adi,agc-immed-gain-change-if-large-adc-overload-enable;
//adi,agc-immed-gain-change-if-large-lmt-overload-enable;

/* Fast AGC */

adi,fagc-dec-pow-measurement-duration = <64>; /* 64 Samples */
//adi,fagc-allow-agc-gain-increase-enable;
adi,fagc-lp-thresh-increment-steps = <1>;
adi,fagc-lp-thresh-increment-time = <5>;

adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <8>;
adi,fagc-final-overrange-count = <3>;
//adi,fagc-gain-increase-after-gain-lock-enable;
adi,fagc-gain-index-type-after-exit-rx-mode = <0>;
adi,fagc-lmt-final-settling-steps = <1>;
adi,fagc-lock-level = <10>;
adi,fagc-lock-level-gain-increase-upper-limit = <5>;
adi,fagc-lock-level-lmt-gain-increase-enable;

adi,fagc-lpf-final-settling-steps = <1>;
adi,fagc-optimized-gain-offset = <5>;
adi,fagc-power-measurement-duration-in-state5 = <64>;
adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <10>;
adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable;
adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0>;
adi,fagc-rst-gla-large-adc-overload-enable;
adi,fagc-rst-gla-large-lmt-overload-enable;
adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <10>;
adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable;
adi,fagc-state-wait-time-ns = <260>;
adi,fagc-use-last-lock-level-for-set-gain-enable;

/* RSSI */

/* adi,rssi-restart-mode:
* 0 = AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN,
* 1 = EN_AGC_PIN_IS_PULLED_HIGH,
* 2 = ENTERS_RX_MODE,
* 3 = GAIN_CHANGE_OCCURS,
* 4 = SPI_WRITE_TO_REGISTER,
* 5 = GAIN_CHANGE_OCCURS_OR_EN_AGC_PIN_PULLED_HIGH,
*/
adi,rssi-restart-mode = <3>;
//adi,rssi-unit-is-rx-samples-enable;
adi,rssi-delay = <1>; /* 1us */
adi,rssi-wait = <1>; /* 1us */
adi,rssi-duration = <1000>; /* 1ms */

//test
adi,lvds-invert1-control = <0xFF>;
adi,lvds-invert2-control = <0x0F>;
adi,aux-adc-decimation = <256>;
adi,aux-adc-rate = <40000000>;
adi,dc-offset-count-high-range = <0x28>;
adi,dc-offset-count-low-range = <0x32>;

/* Control Outputs */
adi,ctrl-outs-index = <0>;
adi,ctrl-outs-enable-mask = <0xFF>;

/* AuxADC Temp Sense Control */

adi,temp-sense-measurement-interval-ms = <1000>;
adi,temp-sense-offset-signed = <0xCE>;
adi,temp-sense-periodic-measurement-enable;

/* AuxDAC Control */

adi,aux-dac-manual-mode-enable;

adi,aux-dac1-default-value-mV = <0>;
//adi,aux-dac1-active-in-rx-enable;
//adi,aux-dac1-active-in-tx-enable;
//adi,aux-dac1-active-in-alert-enable;
adi,aux-dac1-rx-delay-us = <0>;
adi,aux-dac1-tx-delay-us = <0>;

adi,aux-dac2-default-value-mV = <0>;
//adi,aux-dac2-active-in-rx-enable;
//adi,aux-dac2-active-in-tx-enable;
//adi,aux-dac2-active-in-alert-enable;
adi,aux-dac2-rx-delay-us = <0>;
adi,aux-dac2-tx-delay-us = <0>;

adi,delay-rx-data = <0>;
adi,rx-data-clock-delay = <0>;
adi,tx-data-delay = <0>;


// en_agc-gpios = <&gpio0 122 0>;
sync-gpios = <&gpio0 99 0>;
reset-gpios = <&gpio0 54 0>;
enable-gpios = <&gpio0 55 0>;
txnrx-gpios = <&gpio0 56 0>;
};
};
# 11 "zynq-antsdre200.dts" 2
# 24 "zynq-antsdre200.dts"



Change q.
[edited by: Novas228 at 11:19 AM (GMT -4) on 24 May 2023]
Parents Reply Children
  • They are very similar but the constraints pinout will be different.

    -Travis

  • Constraints, I change them myself. Therefore, I have to change the pins in any project.

  • What do you see as the problem most of all, the incompatibility of the kernel(axi_ad9361) with drivers and device_tree?

  • The HDL and drivers are verified together at release points, but not across releases. So its only luck if they work across different branches. My most likely guess of the issues you are having are related to the interface configuration. Especially if you are moving from a CMOS to an LVDS design on your own.

    -Travis

  • Thanks, I'll think about it, but do not forget that in no-os everything works as it should for me.

  • Yes but configuration is different between Linux and No-OS. So even if it works in No-OS doesn't mean you configured Linux correctly.

    -Travis

  • I did as you said but got the same results.

    Linux log:
    ...
    ad9361 spi0.0: ad9361_probe : AD936x Rev 0 successfully initialized
    cf_axi_dds 79024000.cf-ad9361-dds-core-lpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x79024000 mapped to 0x(ptrval), probed DDS AD9361
    axi_sysid 45000000.axi-sysid-0: AXI System ID core version (1.01.a) found
    axi_sysid 45000000.axi-sysid-0: [fmcomms2] on [zc706] git branch <hdl_2021_r2> git <d0336c0f6ff88061d906621c11b616145f96358e> clean [2023-05-31 06:28:30] UTC
    fpga_manager fpga0: Xilinx Zynq FPGA Manager registered
    usbcore: registered new interface driver snd-usb-audio
    NET: Registered protocol family 10
    Segment Routing with IPv6
    sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
    NET: Registered protocol family 17
    NET: Registered protocol family 36
    Key type dns_resolver registered
    Registering SWP/SWPB emulation handler
    of-fpga-region fpga-full: FPGA Region probed
    SAMPL CLK: 61440000 tuning: RX
    0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
    0:# # # # # # # # # # # # # # # #
    1:# # # # # # # # # # # # # # # #
    ad9361 spi0.0: ad9361_dig_tune_delay: Tuning RX FAILED!
    cf_axi_adc: probe of 79020000.cf-ad9361-lpc failed with error -5
    input: gpio_keys as /devices/soc0/gpio_keys/input/input0
    of_cfs_init
    of_cfs_init: OK
    ...

    No-os log:
    cf-ad9361-lpc: Successfully initialized (122875976 Hz)
    SAMPL CLK: 25000000 tuning: RX
    0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
    0:# # o o o o o o o o o o o o o o
    1:# # # # # # # # # # # # # # # #
    SAMPL CLK: 40000000 tuning: RX
    0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
    0:# # o o o o o o o o # # # # # #
    1:# # # # # # # # # # # # # # # #
    SAMPL CLK: 61440000 tuning: RX
    0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
    0:# # o o o # # # # # # # # # # #
    1:# # # # # # # # # # # # # # # #
    SAMPL CLK: 61440000 tuning: RX
    0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
    0:# # o O o # # # # # # # # # # #
    1:# # # # # # # # # # # # # # # #
    SAMPL CLK: 25000000 tuning: TX
    0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
    0:# # # # # # # # # # # # # # # #
    1:# # o o o o o o o o o o o o o o
    SAMPL CLK: 40000000 tuning: TX
    0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
    0:# # # # # # # # # # # # # # # #
    1:# # o o o o o o o # # # # # # #
    SAMPL CLK: 61440000 tuning: TX
    0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
    0:# # # # # # # # # # # # # # # #
    1:# # o o o # # # # # # # # # # #
    SAMPL CLK: 61440000 tuning: TX
    0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
    0:# # # # # # # # # # # # # # # #
    1:# # o O o # # # # # # # # # # #
    ad9361_init : AD936x Rev 2 successfully initialized
    cf-ad9361-dds-core-lpc: Successfully initialized (122875976 Hz)
    DMA_EXAMPLE: address=0x13c030 samples=65536 channels=4 bits=16
    Done.
    (I noticed one oddity when I start no-os, my board is flashed only on the second attempt.)

    Changes(hdl, origin/hdl_2021_r2, project fmcomms2/zc706):
    -delete hdmi, gpio_bd, spdif, i2c, tdd_sync, gpio_muxout_tx, gpio_muxout_rx, spi_udc;
    -ddr(i have 4096 mbit ddr);
    -uart1 to uart0;
    -constr(use my, they work).

    Linux(branch 'origin/2021_R2'):
    config: zynq_xcomm_adv7511_defconfig.


    device_tree: zynq-zc706-adv7511-ad9361-fmcomms2-3.dtbdevice_tree is missing modules that are removed in hdl.

    
    
    
    
    // SPDX-License-Identifier: GPL-2.0
    /*
     * Analog Devices AD-FMCOMMS2-EBZ/AD-FMCOMMS3-EBZ
     * https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz
     * https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms3-ebz
     *
     * hdl_project: <fmcomms2/zc706>
     * board_revision: <>
     *
     * Copyright (C) 2014-2019 Analog Devices Inc.
     */
    /dts-v1/;
    
    #include "zynq-zc706.dtsi"
    #include "zynq-zc706-adv7511.dtsi"
    
    // &i2c_mux {
    // 	fmc_i2c: i2c@6 {
    // 		#size-cells = <0>;
    // 		#address-cells = <1>;
    // 		reg = <6>;
    // 	};
    // };
    
    &fpga_axi  {
    	rx_dma: dma@7c400000 {
    		compatible = "adi,axi-dmac-1.00.a";
    		reg = <0x7c400000 0x1000>;
    		#dma-cells = <1>;
    		interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
    		clocks = <&clkc 16>;
    
    		adi,channels {
    			#size-cells = <0>;
    			#address-cells = <1>;
    
    			dma-channel@0 {
    				reg = <0>;
    				adi,source-bus-width = <64>;
    				adi,source-bus-type = <2>;
    				adi,destination-bus-width = <64>;
    				adi,destination-bus-type = <0>;
    			};
    		};
    	};
    
    	tx_dma: dma@7c420000 {
    		compatible = "adi,axi-dmac-1.00.a";
    		reg = <0x7c420000 0x1000>;
    		#dma-cells = <1>;
    		interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
    		clocks = <&clkc 16>;
    
    		adi,channels {
    			#size-cells = <0>;
    			#address-cells = <1>;
    
    			dma-channel@0 {
    				reg = <0>;
    				adi,source-bus-width = <64>;
    				adi,source-bus-type = <0>;
    				adi,destination-bus-width = <64>;
    				adi,destination-bus-type = <2>;
    			};
    		};
    	};
    
    	cf_ad9361_adc_core_0: cf-ad9361-lpc@79020000 {
    		compatible = "adi,axi-ad9361-6.00.a";
    		reg = <0x79020000 0x6000>;
    		dmas = <&rx_dma 0>;
    		dma-names = "rx";
    
    		spibus-connected = <&adc0_ad9361>;
    	};
    
    	cf_ad9361_dac_core_0: cf-ad9361-dds-core-lpc@79024000 {
    		compatible = "adi,axi-ad9361-dds-6.00.a";
    		reg = <0x79024000 0x1000>;
    		clocks = <&adc0_ad9361 13>;
    		clock-names = "sampl_clk";
    		dmas = <&tx_dma 0>;
    		dma-names = "tx";
    	};
    
    	mwipcore@43c00000 {
    		compatible = "mathworks,mwipcore-axi4lite-v1.00";
    		reg = <0x43C00000 0xffff>;
    	};
    };
    
    &spi0 {
    	status = "okay";
    };
    
    // &spi1 {
    // 	status = "okay";
    // };
    
    #define fmc_spi spi0
    // #define pmod_spi spi1
    
    #include "adi-fmcomms2.dtsi"
    #include "adi-fmcomms3-up-down-converter.dtsi"
    
    &adc0_ad9361 {
    	en_agc-gpios = <&gpio0 98 0>;
    	sync-gpios = <&gpio0 99 0>;
    	reset-gpios = <&gpio0 100 0>; /* Previously 83 */
    	enable-gpios = <&gpio0 101 0>;
    	txnrx-gpios = <&gpio0 102 0>;
    };
    
    // &lo_pll0_rx_adf4351 {
    // 	gpios = <&gpio0 103 0>;
    // };
    
    // &lo_pll0_tx_adf4351 {
    // 	gpios = <&gpio0 104 0>;
    // };
    
    
    
    
    / {
    	clocks {
    		ad9361_clkin: clock@0 {
    			compatible = "fixed-clock";
    
    			clock-frequency = <40000000>;
    			clock-output-names = "ad9361_ext_refclk";
    			#clock-cells = <0>;
    		};
    	};
    };
    
    &fmc_spi {
    	adc0_ad9361: ad9361-phy@0 {
    		compatible = "adi,ad9361";
    		reg = <0>;
    
    		/* SPI Setup */
    		spi-cpha;
    		// spi-max-frequency = <10000000>;
    
    		/* Clocks */
    		clocks = <&ad9361_clkin 0>;
    		clock-names = "ad9361_ext_refclk";
    		clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
    		#clock-cells = <1>;
    
    		//adi,debug-mode-enable;
    		/* Digital Interface Control */
    
    		 /* adi,digital-interface-tune-skip-mode:
    		  * 0 = TUNE RX&TX
    		  * 1 = SKIP TX
    		  * 2 = SKIP ALL
    		  */
    		adi,digital-interface-tune-skip-mode = <0>;
    
    		adi,pp-tx-swap-enable;
    		adi,pp-rx-swap-enable;
    		adi,rx-frame-pulse-mode-enable;
    		adi,lvds-mode-enable;
    		adi,lvds-bias-mV = <150>;
    		adi,lvds-rx-onchip-termination-enable;
    		adi,rx-data-delay = <4>;
    		adi,tx-fb-clock-delay = <7>;
    
    		//adi,fdd-rx-rate-2tx-enable;
    
    		adi,dcxo-coarse-and-fine-tune = <8 5920>;
    		//adi,xo-disable-use-ext-refclk-enable;
    
    		/* Mode Setup */
    
    		adi,2rx-2tx-mode-enable;
    		//adi,split-gain-table-mode-enable;
    
    		/* ENSM Mode */
    		adi,frequency-division-duplex-mode-enable;
    		//adi,ensm-enable-pin-pulse-mode-enable;
    		//adi,ensm-enable-txnrx-control-enable;
    
    
    		/* adi,rx-rf-port-input-select:
    		 * 0 = (RX1A_N &  RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced
    		 * 1 = (RX1B_N &  RX1B_P) and (RX2B_N & RX2B_P) enabled; balanced
    		 * 2 = (RX1C_N &  RX1C_P) and (RX2C_N & RX2C_P) enabled; balanced
    		 *
    		 * 3 = RX1A_N and RX2A_N enabled; unbalanced
    		 * 4 = RX1A_P and RX2A_P enabled; unbalanced
    		 * 5 = RX1B_N and RX2B_N enabled; unbalanced
    		 * 6 = RX1B_P and RX2B_P enabled; unbalanced
    		 * 7 = RX1C_N and RX2C_N enabled; unbalanced
    		 * 8 = RX1C_P and RX2C_P enabled; unbalanced
    		 */
    
    		adi,rx-rf-port-input-select = <0>; /* (RX1A_N &  RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced */
    
    		/* adi,tx-rf-port-input-select:
    		 * 0	TX1A, TX2A
    		 * 1	TX1B, TX2B
    		 */
    
    		adi,tx-rf-port-input-select = <0>; /* TX1A, TX2A */
    		//adi,update-tx-gain-in-alert-enable;
    		adi,tx-attenuation-mdB = <10000>;
    		adi,tx-lo-powerdown-managed-enable;
    
    		adi,rf-rx-bandwidth-hz = <18000000>;
    		adi,rf-tx-bandwidth-hz = <18000000>;
    		adi,rx-synthesizer-frequency-hz = /bits/ 64 <2400000000>;
    		adi,tx-synthesizer-frequency-hz = /bits/ 64 <2450000000>;
    
    		/*				BBPLL     ADC        R2CLK     R1CLK    CLKRF    RSAMPL  */
    		adi,rx-path-clock-frequencies = <983040000 245760000 122880000 61440000 30720000 30720000>;
    		/*				BBPLL     DAC        T2CLK     T1CLK    CLKTF    TSAMPL  */
    		adi,tx-path-clock-frequencies = <983040000 122880000 122880000 61440000 30720000 30720000>;
    
    		/* Gain Control */
    
    		//adi,gaintable-name = "ad9361_std_gaintable";
    
    		/* adi,gc-rx[1|2]-mode:
    		 * 0 = RF_GAIN_MGC
    		 * 1 = RF_GAIN_FASTATTACK_AGC
    		 * 2 = RF_GAIN_SLOWATTACK_AGC
    		 * 3 = RF_GAIN_HYBRID_AGC
    		 */
    
    		adi,gc-rx1-mode = <2>;
    		adi,gc-rx2-mode = <2>;
    		adi,gc-adc-ovr-sample-size = <4>; /* sum 4 samples */
    		adi,gc-adc-small-overload-thresh = <47>; /* sum of squares */
    		adi,gc-adc-large-overload-thresh = <58>; /* sum of squares */
    		adi,gc-lmt-overload-high-thresh = <800>; /* mV */
    		adi,gc-lmt-overload-low-thresh = <704>; /* mV */
    		adi,gc-dec-pow-measurement-duration = <8192>; /* 0..524288 Samples */
    		adi,gc-low-power-thresh = <24>; /* 0..-64 dBFS vals are set pos */
    		//adi,gc-dig-gain-enable;
    		//adi,gc-max-dig-gain = <15>;
    
    		/* Manual Gain Control Setup */
    
    		//adi,mgc-rx1-ctrl-inp-enable; /* uncomment to use ctrl inputs */
    		//adi,mgc-rx2-ctrl-inp-enable; /* uncomment to use ctrl inputs */
    		adi,mgc-inc-gain-step = <2>;
    		adi,mgc-dec-gain-step = <2>;
    
    		/* adi,mgc-split-table-ctrl-inp-gain-mode:
    		 * (relevant if adi,split-gain-table-mode-enable is set)
    		 * 0 = AGC determine this
    		 * 1 = only in LPF
    		 * 2 = only in LMT
    		 */
    
    		adi,mgc-split-table-ctrl-inp-gain-mode = <0>;
    
    		/* Automatic Gain Control Setup */
    
    		adi,agc-attack-delay-extra-margin-us= <1>; /* us */
    		adi,agc-outer-thresh-high = <5>; /* -dBFS */
    		adi,agc-outer-thresh-high-dec-steps = <2>; /* 0..15 */
    		adi,agc-inner-thresh-high = <10>; /* -dBFS */
    		adi,agc-inner-thresh-high-dec-steps = <1>; /* 0..7 */
    		adi,agc-inner-thresh-low = <12>; /* -dBFS */
    		adi,agc-inner-thresh-low-inc-steps = <1>; /* 0..7 */
    		adi,agc-outer-thresh-low = <18>; /* -dBFS */
    		adi,agc-outer-thresh-low-inc-steps = <2>; /* 0..15 */
    
    		adi,agc-adc-small-overload-exceed-counter = <10>; /* 0..15 */
    		adi,agc-adc-large-overload-exceed-counter = <10>; /* 0..15 */
    		adi,agc-adc-large-overload-inc-steps = <2>; /* 0..15 */
    		//adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable;
    		adi,agc-lmt-overload-large-exceed-counter = <10>; /* 0..15 */
    		adi,agc-lmt-overload-small-exceed-counter = <10>; /* 0..15 */
    		adi,agc-lmt-overload-large-inc-steps = <2>; /* 0..7 */
    		//adi,agc-dig-saturation-exceed-counter = <3>; /* 0..15 */
    		//adi,agc-dig-gain-step-size = <4>; /* 1..8 */
    
    		//adi,agc-sync-for-gain-counter-enable;
    		adi,agc-gain-update-interval-us = <1000>;  /* 1ms */
    		//adi,agc-immed-gain-change-if-large-adc-overload-enable;
    		//adi,agc-immed-gain-change-if-large-lmt-overload-enable;
    
    		/* Fast AGC */
    
    		adi,fagc-dec-pow-measurement-duration = <64>; /* 64 Samples */
                    //adi,fagc-allow-agc-gain-increase-enable;
                    adi,fagc-lp-thresh-increment-steps = <1>;
                    adi,fagc-lp-thresh-increment-time = <5>;
    
                    adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <8>;
                    adi,fagc-final-overrange-count = <3>;
                    //adi,fagc-gain-increase-after-gain-lock-enable;
                    adi,fagc-gain-index-type-after-exit-rx-mode = <0>;
                    adi,fagc-lmt-final-settling-steps = <1>;
                    adi,fagc-lock-level = <10>;
                    adi,fagc-lock-level-gain-increase-upper-limit = <5>;
                    adi,fagc-lock-level-lmt-gain-increase-enable;
    
                    adi,fagc-lpf-final-settling-steps = <1>;
                    adi,fagc-optimized-gain-offset = <5>;
                    adi,fagc-power-measurement-duration-in-state5 = <64>;
                    adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
                    adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <10>;
                    adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable;
                    adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0>;
                    adi,fagc-rst-gla-large-adc-overload-enable;
                    adi,fagc-rst-gla-large-lmt-overload-enable;
                    adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <10>;
                    adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable;
                    adi,fagc-state-wait-time-ns = <260>;
                    adi,fagc-use-last-lock-level-for-set-gain-enable;
    
    		/* RSSI */
    
    		/* adi,rssi-restart-mode:
    		 * 0 = AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN,
    		 * 1 = EN_AGC_PIN_IS_PULLED_HIGH,
    		 * 2 = ENTERS_RX_MODE,
    		 * 3 = GAIN_CHANGE_OCCURS,
    		 * 4 = SPI_WRITE_TO_REGISTER,
    		 * 5 = GAIN_CHANGE_OCCURS_OR_EN_AGC_PIN_PULLED_HIGH,
    		 */
    		adi,rssi-restart-mode = <3>;
    		//adi,rssi-unit-is-rx-samples-enable;
    		adi,rssi-delay = <1>; /* 1us */
    		adi,rssi-wait = <1>; /* 1us */
    		adi,rssi-duration = <1000>; /* 1ms */
    
    		/* Control Outputs */
    		adi,ctrl-outs-index = <0>;
    		adi,ctrl-outs-enable-mask = <0xFF>;
    
    		/* AuxADC Temp Sense Control */
    
    		adi,temp-sense-measurement-interval-ms = <1000>;
    		adi,temp-sense-offset-signed = <0xCE>;
    		adi,temp-sense-periodic-measurement-enable;
    
    		/* AuxDAC Control */
    
    		adi,aux-dac-manual-mode-enable;
    
    		adi,aux-dac1-default-value-mV = <0>;
    		//adi,aux-dac1-active-in-rx-enable;
    		//adi,aux-dac1-active-in-tx-enable;
    		//adi,aux-dac1-active-in-alert-enable;
    		adi,aux-dac1-rx-delay-us = <0>;
    		adi,aux-dac1-tx-delay-us = <0>;
    
    		adi,aux-dac2-default-value-mV = <0>;
    		//adi,aux-dac2-active-in-rx-enable;
    		//adi,aux-dac2-active-in-tx-enable;
    		//adi,aux-dac2-active-in-alert-enable;
    		adi,aux-dac2-rx-delay-us = <0>;
    		adi,aux-dac2-tx-delay-us = <0>;
    	};
    };
    
    // &fmc_i2c {
    // 	ad7291@2f {
    // 		compatible = "adi,ad7291";
    // 		reg = <0x2f>;
    // 	};
    
    // 	eeprom@50 {
    // 		compatible = "at24,24c02";
    // 		reg = <0x50>;
    // 	};
    // };
    
    
    
    
    
    
    
    #include "zynq-7000.dtsi"
    
    / {
    	interrupt-parent = <&intc>;
    
    	aliases: aliases {
    		ethernet0 = &gem0;
    		serial0 = &uart0;
    	};
    };
    
    &gem0 {
    	status = "okay";
    };
    
    &clkc {
    	ps-clk-frequency = <33333333>;
    };
    
    // &usb0 {
    // 	status = "okay";
    // 	dr_mode = "host"; /* This breaks OTG mode */
    // };
    
    &uart0 {
    	status = "okay";
    };
    
    &sdhci0 {
    	status = "okay";
    };
    
    
    
    
    
    
    
    
    
    #include "zynq.dtsi"
    
    #include <dt-bindings/interrupt-controller/irq.h>
    
    / {
    	model = "Xilinx Zynq ZC706";
    	memory {
    		device_type = "memory";
    		reg = <0x00000000 0x20000000>;
    	};
    
    	 chosen {
    	  bootargs = "earlycon";
    	  stdout-path = "serial0:115200n8";
    	 };
    
    	leds {
    		compatible = "gpio-leds";
    		ds8 {
    			label = "ds12:green";
    			gpios = <&gpio0 61 0>;
    		};
    
    		ds9 {
    			label = "ds15:green";
    			gpios = <&gpio0 62 0>;
    		};
    
    		ds10 {
    			label = "ds16:green";
    			gpios = <&gpio0 63 0>;
    		};
    
    		ds35 {
    			label = "ds17:green";
    			gpios = <&gpio0 64 0>;
    		};
    	};
    
    	gpio_keys {
    		compatible = "gpio-keys";
    		#address-cells = <1>;
    		#size-cells = <0>;
    		autorepeat;
    
    		sw7 {
    			label = "Left";
    			linux,code = <105>; // Left
    			gpios = <&gpio0 58 0>;
    		};
    
    		sw8 {
    			label = "Right";
    			linux,code = <106>; // Right
    			gpios = <&gpio0 60 0>;
    		};
    
    		sw9 {
    			label = "Select";
    			linux,code = <28>; // Enter
    			gpios = <&gpio0 59 0>;
    		};
    	};
    };
    
    &gem0 {
    	phy-handle = <&phy0>;
    	phy-mode = "rgmii-id";
    
    	phy0: phy@7 {
    		device_type = "ethernet-phy";
    		reg = <0x7>;
    	};
    };
    
    // &usb0 {
    // 	xlnx,phy-reset-gpio = <&gpio0 7 0>;
    // };
    
    &qspi {
    	status = "okay";
    	is-dual = <1>;
    	num-cs = <1>;
    	primary_flash: ps7-qspi@0 {
    		#address-cells = <1>;
    		#size-cells = <1>;
    		spi-tx-bus-width = <4>;
    		spi-rx-bus-width = <4>;
    		compatible = "n25q128a11";
    		reg = <0x0>;
    		// spi-max-frequency = <50000000>;
    		// partition@0 {
    		// 	label = "boot";
    		// 	reg = <0x00000000 0x00500000>;
    		// };
    		// partition@500000 {
    		// 	label = "bootenv";
    		// 	reg = <0x00500000 0x00020000>;
    		// };
    		// partition@520000 {
    		// 	label = "config";
    		// 	reg = <0x00520000 0x00020000>;
    		// };
    		// partition@540000 {
    		// 	label = "image";
    		// 	reg = <0x00540000 0x00a80000>;
    		// };
    		// partition@fc0000 {
    		// 	label = "spare";
    		// 	reg = <0x00fc0000 0x00000000>;
    		// };
    	};
    };
    
    
    
    #include <dt-bindings/interrupt-controller/irq.h>
    
    / {
    	fpga_axi: fpga-axi@0 {
    		compatible = "simple-bus";
    		#address-cells = <0x1>;
    		#size-cells = <0x1>;
    		ranges;
    
    		// i2c@41600000 {
    		// 	compatible = "xlnx,axi-iic-1.02.a", "xlnx,xps-iic-2.00.a";
    		// 	reg = <0x41600000 0x10000>;
    		// 	interrupt-parent = <&intc>;
    		// 	interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
    		// 	clocks = <&clkc 15>;
    		// 	clock-names = "pclk";
    
    		// 	#address-cells = <1>;
    		// 	#size-cells = <0>;
    
    		// 	i2c_mux: i2cswitch@74 {
    		// 		compatible = "nxp,pca9548";
    		// 		#address-cells = <1>;
    		// 		#size-cells = <0>;
    		// 		reg = <0x74>;
    
    		// 		i2c@0 {
    		// 			#address-cells = <1>;
    		// 			#size-cells = <0>;
    		// 			reg = <0>;
    		// 			osc@5d {
    		// 				compatible = "si570";
    		// 				temperature-stability = <50>;
    		// 				reg = <0x5d>;
    		// 				factory-fout = <156250000>;
    		// 				initial-fout = <148500000>;
    		// 			};
    		// 		};
    
    		// 		i2c@1 {
    		// 		    #address-cells = <1>;
    		// 		    #size-cells = <0>;
    		// 		    reg = <1>;
    
    		// 		    adv7511: adv7511@39 {
    		// 				compatible = "adi,adv7511";
    		// 				reg = <0x39>, <0x3f>;
    		// 				reg-names = "primary", "edid";
    
    		// 				adi,input-depth = <8>;
    		// 				adi,input-colorspace = "rgb";
    		// 				adi,input-clock = "1x";
    		// 				adi,clock-delay = <0>;
    
    		// 				#sound-dai-cells = <1>;
    
    		// 				ports {
    		// 					#address-cells = <1>;
    		// 					#size-cells = <0>;
    
    		// 					port@0 {
    		// 						reg = <0>;
    		// 						adv7511_in: endpoint {
    		// 							remote-endpoint = <&axi_hdmi_out>;
    		// 						};
    		// 					};
    
    		// 					port@1 {
    		// 						reg = <1>;
    		// 					};
    		// 				};
    		// 		    };
    		// 		};
    
    		// 		i2c@2 {
    		// 			#address-cells = <1>;
    		// 			#size-cells = <0>;
    		// 			reg = <2>;
    		// 			eeprom@54 {
    		// 				compatible = "at,24c08";
    		// 				reg = <0x54>;
    		// 			};
    		// 		};
    
    		// 		i2c@3 {
    		// 			#address-cells = <1>;
    		// 			#size-cells = <0>;
    		// 			reg = <3>;
    		// 			gpio@21 {
    		// 				compatible = "ti,tca6416";
    		// 				reg = <0x21>;
    		// 				gpio-controller;
    		// 				#gpio-cells = <2>;
    		// 			};
    		// 		};
    
    		// 		i2c@4 {
    		// 			#address-cells = <1>;
    		// 			#size-cells = <0>;
    		// 			reg = <4>;
    		// 			rtc@51 {
    		// 				compatible = "nxp,pcf8563";
    		// 				reg = <0x51>;
    		// 			};
    		// 		};
    		// 	};
    		// };
    
    		// hdmi_dma: dma@43000000 {
    		// 	compatible = "adi,axi-dmac-1.00.a";
    		// 	reg = <0x43000000 0x1000>;
    		// 	#dma-cells = <1>;
    		// 	interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
    		// 	clocks = <&clkc 16>;
    
    		// 	adi,channels {
    		// 		#size-cells = <0>;
    		// 		#address-cells = <1>;
    
    		// 		dma-channel@0 {
    		// 			reg = <0>;
    		// 			adi,source-bus-width = <64>;
    		// 			adi,source-bus-type = <0>;
    		// 			adi,destination-bus-width = <64>;
    		// 			adi,destination-bus-type = <1>;
    		// 		};
    		// 	};
    		// };
    
    		// hdmi_clock: axi-clkgen@79000000 {
    		// 	compatible = "adi,axi-clkgen-2.00.a";
    		// 	reg = <0x79000000 0x10000>;
    		// 	#clock-cells = <0>;
    		// 	clocks = <&clkc 15>, <&clkc 16>;
    		// 	clock-names = "s_axi_aclk", "clkin1";
    		// };
    
    		// axi_hdmi@70e00000 {
    		// 	compatible = "adi,axi-hdmi-tx-1.00.a";
    		// 	reg = <0x70e00000 0x10000>;
    		// 	dmas = <&hdmi_dma 0>;
    		// 	dma-names = "video";
    		// 	clocks = <&hdmi_clock>;
    		// 	adi,is-rgb;
    
    		// 	port {
    		// 		axi_hdmi_out: endpoint {
    		// 			remote-endpoint = <&adv7511_in>;
    		// 		};
    		// 	};
    		// };
    
    		// axi_spdif_tx_0: axi-spdif-tx@75c00000 {
    		// 	compatible = "adi,axi-spdif-tx-1.00.a";
    		// 	reg = <0x75c00000 0x1000>;
    		// 	dmas = <&dmac_s 0>;
    		// 	dma-names = "tx";
    		// 	clocks = <&clkc 15>, <&audio_clock>;
    		// 	clock-names = "axi", "ref";
    
    		// 	#sound-dai-cells = <0>;
    		// };
    
    		axi_sysid_0: axi-sysid-0@45000000 {
    			compatible = "adi,axi-sysid-1.00.a";
    			reg = <0x45000000 0x10000>;
    		};
    
    	};
    
    	// audio_clock: audio_clock {
    	// 	compatible = "fixed-clock";
    	// 	#clock-cells = <0>;
    	// 	clock-frequency = <12288000>;
    	// };
    
    	// adv7511_hdmi_snd {
    	// 	compatible = "simple-audio-card";
    	// 	simple-audio-card,name = "HDMI monitor";
    	// 	simple-audio-card,widgets =
    	// 		"Speaker", "Speaker";
    	// 	simple-audio-card,routing =
    	// 		"Speaker", "TX";
    
    	// 	simple-audio-card,dai-link@0 {
    	// 		format = "spdif";
    	// 		cpu {
    	// 			sound-dai = <&axi_spdif_tx_0>;
    	// 			frame-master;
    	// 			bitclock-master;
    	// 		};
    	// 		codec {
    	// 			sound-dai = <&adv7511 1>;
    	// 		};
    	// 	};
    	// };
    };
    
    
    
    /*
     * FMCOMMS3 optional Up/Down Converter PMOD
     */
    / {
    	clocks {
    		adf4351_clkin: clock@1 {
    			compatible = "fixed-clock";
    
    			clock-frequency = <25000000>;
    			clock-output-names = "refclk";
    			#clock-cells = <0>;
    		};
    	};
    };
    
    // &pmod_spi {
    // 		lo_pll0_tx_adf4351: adf4351-udc-tx-pmod@0 {
    // 			compatible = "adi,adf4351";
    // 			reg = <0>;
    
    // 			spi-max-frequency = <10000000>;
    
    // 			clocks = <&adf4351_clkin>;
    // 			clock-names = "clkin";
    
    // 			adi,channel-spacing = <1000000>;
    // 			adi,power-up-frequency = <370000000>;
    // 			adi,phase-detector-polarity-positive-enable;
    // 			adi,charge-pump-current = <2500>;
    // 			adi,output-power = <3>;
    // 			adi,mute-till-lock-enable;
    // 			adi,muxout-select = <6>;
    // 		};
    
    // 		lo_pll0_rx_adf4351: adf4351-udc-rx-pmod@1 {
    // 			compatible = "adi,adf4351";
    // 			reg = <1>;
    
    // 			spi-max-frequency = <10000000>;
    
    // 			clocks = <&adf4351_clkin>;
    // 			clock-names = "clkin";
    
    // 			adi,channel-spacing = <1000000>;
    // 			adi,power-up-frequency = <340000000>;
    // 			adi,phase-detector-polarity-positive-enable;
    // 			adi,charge-pump-current = <2500>;
    // 			adi,output-power = <3>;
    // 			adi,mute-till-lock-enable;
    // 			adi,muxout-select = <6>;
    // 		};
    // };
    
    



  • Can you set adi,digital-interface-tune-skip to 2 then manually run a tune post boot and post results here: Digital Interface Timing Verification [Analog Devices Wiki]

    At boot can you verify that RESETB is toggled as well.

    -Travis

  • Initially resetb didn't work for me, but I rebuilt the project on other gpios and it worked for me (for some reason, gpios > 40 don't work, although 64 are used in the project).
    As you can see in the log, I do not have device1, and nothing happens to device0.


    Log:

    Registering SWP/SWPB emulation handler
    of-fpga-region fpga-full: FPGA Region probed
    cf_axi_adc 79020000.cf-ad9361-lpc: ADI AIM (10.02.b) at 0x79020000 mapped to 0x(ptrval) probed ADC AD9361 as MASTER
    input: gpio_keys as /devices/soc0/gpio_keys/input/input0
    of_cfs_init
    of_cfs_init: OK
    ALSA device list:
      No soundcards found.
    RAMDISK: gzip image found at block 0
    using deprecated initrd support, will be removed in 2021.
    EXT4-fs (ram0): mounting ext2 file system using the ext4 subsystem
    EXT4-fs (ram0): mounted filesystem without journal. Opts: (null)
    VFS: Mounted root (ext2 filesystem) on device 1:0.
    Starting rcS...
    ++ Mounting filesystem
    mount: mounting /dev/mmcblk0p1 on /mnt failed: Invalid argument
    mount: mounting /dev/mmcblk0 on /mnt failed: Invalid argument
    ++ Setting up mdev
    /etc/init.d/rcS: line 12: can't create /proc/sys/kernel/hotplug: nonexistent directory
    ++ Starting telnet daemon
    ++ Starting http daemon
    ++ Starting ftp daemon
    ++ Starting ssh daemon
    random: sshd: uninitialized urandom read (32 bytes read)
    rcS Complete
    zynq> mount -t debugfs none /sys/kernel/debug
    zynq> cd /sys/kernel/debug/
    zynq> ls
    adi_axi_data_offload  dmaengine             pinctrl
    asoc                  dri                   pmbus
    bdi                   f8003000.dmac         pwm
    block                 fault_around_bytes    regmap
    cec                   gpio                  regulator
    clear_warn_once       hid                   sleep_time
    clk                   iio                   suspend_stats
    device_component      memblock              usb
    devices_deferred      mmc0                  wakeup_sources
    dma_buf               mtd
    zynq> cd iio/
    zynq> cd iio\:device
    iio:device0/  iio:device2/  iio:device3/
    zynq> cd iio\:device0
    zynq> dmesg -n7
    zynq> echo 0 3 > digital_tune
    zynq> echo 1 3 > digital_tune
    zynq>

  • can provide the full dmesg?

    -Travis