A riddle from Jacques Fresco.
This error occurs. When I use NO-OS, there is no such error.
ad9361_spi_writem: reg 0x74 val 0x1
ad9361_spi_writem: reg 0x73 val 0x67
ad9361_spi_writem: reg 0x76 val 0x1
ad9361_spi_writem: reg 0x75 val 0x67
ad9361_spi_writem: reg 0x4A val 0x35
ad9361_spi_writem: reg 0x49 val 0x5B
ad9361_spi_writem: reg 0x48 val 0xE8
SAMPL CLK: 25000000 tuning: RX
0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:# # # # # # # # # # # # # # # #
1:# # # # # # # # # # # # # # # #
ad9361_spi_writem: reg 0x4A val 0x35
ad9361_spi_writem: reg 0x49 val 0x5B
ad9361_spi_writem: reg 0x48 val 0xE8
SAMPL CLK: 40000000 tuning: RX
0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:# # # # # # # # # # # # # # # #
1:# # # # # # # # # # # # # # # #
ad9361_spi_writem: reg 0x4A val 0x35
ad9361_spi_writem: reg 0x49 val 0x5B
ad9361_spi_writem: reg 0x48 val 0xE8
SAMPL CLK: 61440000 tuning: RX
0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:# # # # # # # # # # # # # # # #
1:# # # # # # # # # # # # # # # #
SAMPL CLK: 61440000 tuning: RX
0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:# # # # # # # # # # # # # # # #
1:# # # # # # # # # # # # # # # #
ad9361 spi2.0: ad9361_dig_tune_delay: Tuning RX FAILED!
ad9361_spi_writem: reg 0x74 val 0x0
ad9361_spi_writem: reg 0x73 val 0x28
ad9361_spi_writem: reg 0x76 val 0x0
ad9361_spi_writem: reg 0x75 val 0x28
cf_axi_adc: probe of 79020000.cf-ad9361-lpc failed with error -5
Here's a tree:
ptm@f889c000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0xf889c000 0x1000>;
clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
cpu = <&cpu0>;
out-ports {
port {
ptm0_out_port: endpoint {
remote-endpoint = <&funnel0_in_port0>;
};
};
};
};
ptm@f889d000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0xf889d000 0x1000>;
clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
cpu = <&cpu1>;
out-ports {
port {
ptm1_out_port: endpoint {
remote-endpoint = <&funnel0_in_port1>;
};
};
};
};
};
};
# 3 "zynq.dtsi" 2
/ {
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
aliases {
serial0 = &uart0;
spi0 = &qspi;
// spi1 = &axi_spi;
spi2 = &spi0;
};
memory {
device_type = "memory";
reg = <0x0 0x20000000>;
};
};
/ {
cpus {
cpu@0 {
operating-points = <800000 1000000 400000 1000000 200000 1000000>;
};
};
};
&gpio0 {
emio-gpio-width = <25>;
gpio-mask-high = <0x0>;
gpio-mask-low = <0x5600>;
};
&intc {
num_cpus = <2>;
num_interrupts = <96>;
};
&qspi {
is-dual = <0>;
num-cs = <0x1>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
status = "okay";
};
&sdhci0 {
status = "okay";
xlnx,has-cd = <0x1>;
xlnx,has-power = <0x0>;
xlnx,has-wp = <0x0>;
};
&spi0 {
is-decoded-cs = <0>;
num-cs = <0x3>;
status = "okay";
};
&uart0 {
cts-override ;
device_type = "serial";
port-number = <0>;
status = "okay";
};
&clkc {
fclk-enable = <0x3>;
ps-clk-frequency = <33333333>;
};
# 9 "zynq-antsdre200.dtsi" 2
# 1 "/home/vasiliy/scat_lib/zynq_timestamping/ant_device_tree/generate/include/dt-bindings/input/input.h" 1
# 13 "/home/vasiliy/scat_lib/zynq_timestamping/ant_device_tree/generate/include/dt-bindings/input/input.h"
# 1 "/home/vasiliy/scat_lib/zynq_timestamping/ant_device_tree/generate/include/dt-bindings/input/linux-event-codes.h" 1
# 14 "/home/vasiliy/scat_lib/zynq_timestamping/ant_device_tree/generate/include/dt-bindings/input/input.h" 2
# 10 "zynq-antsdre200.dtsi" 2
# 1 "/home/vasiliy/scat_lib/zynq_timestamping/ant_device_tree/generate/include/dt-bindings/gpio/gpio.h" 1
# 11 "zynq-antsdre200.dtsi" 2
# 1 "/home/vasiliy/scat_lib/zynq_timestamping/ant_device_tree/generate/include/dt-bindings/interrupt-controller/irq.h" 1
# 12 "zynq-antsdre200.dtsi" 2
# 1 "/home/vasiliy/scat_lib/zynq_timestamping/ant_device_tree/generate/include/dt-bindings/iio/adc/adi,ad9361.h" 1
# 15 "zynq-antsdre200.dtsi" 2
/ {
// model = "MicroPhase ANTSDR E200";
// memory {
// device_type = "memory";
// reg = <0x00000000 0x20000000>;
// };
// aliases {
// ethernet0 = &gem0;
// serial0 = &uart0;
// spi0 = &qspi;
// mmc0 = &sdhci0;
// };
// chosen {
// stdout-path = "/amba@0/uart@E0000000";
// };
clocks {
ad9361_clkin: clock@0 {
compatible = "fixed-clock";
clock-frequency = <40000000>;
clock-output-names = "ad9361_ext_refclk";
#clock-cells = <0>;
};
};
// ltc2630 {
// compatible = "microphase,ltc2630";
// status = "okay";
// ext_ref_locked = <&gpio0 68 1>;
// ext_ref_ispps = <&gpio0 69 0>;
// ref_sel = <&gpio0 70 0>;
// };
};
&sdhci0 {
status = "okay";
xlnx,has-cd = <0x0>;
xlnx,has-power = <0x0>;
xlnx,has-wp = <0x0>;
};
&watchdog0 {
status = "okay";
reset-on-timeout;
};
&uart0 {
status = "okay";
};
# 110 "zynq-antsdre200.dtsi"
&gem0 {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-rxid";
xlnx,has-mdio = <0x1>;
gmii2rgmii-phy-handle = <&gmii_to_rgmii_0>;
phy0: phy@1 {
compatible = "ethernet-phy-id011c.c916";
device_type = "ethernet-phy";
reg = <0x1>;
};
gmii_to_rgmii_0: gmiitorgmii@8 {
compatible = "xlnx,gmii-to-rgmii-1.0";
reg = <0x8>;
phy-handle = <&phy0>;
};
};
&qspi {
status = "okay";
is-dual = <0>;
num-cs = <1>;
primary_flash: ps7-qspi@0 {
#address-cells = <1>;
#size-cells = <1>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
compatible = "n25q256a", "n25q512a", "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <50000000>;
partition@qspi-fsbl-uboot {
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@qspi-uboot-env {
label = "qspi-uboot-env";
reg = <0x100000 0x20000>;
};
partition@qspi-nvmfs {
label = "qspi-nvmfs";
reg = <0x120000 0xE0000>;
};
partition@qspi-linux {
label = "qspi-linux";
reg = <0x200000 0x1E00000>;
};
};
};
&adc {
xlnx,channels {
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
};
};
};
/ {
fpga_axi: fpga-axi@0 {
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
rx_dma: dma@7c400000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x7c400000 0x1000>;
#dma-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <0 57 4>;
clocks = <&clkc 16>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-width = <32>;
adi,source-bus-type = <2>;
adi,destination-bus-width = <64>;
adi,destination-bus-type = <0>;
};
};
};
tx_dma: dma@7c420000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x7c420000 0x1000>;
#dma-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <0 56 4>;
clocks = <&clkc 16>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-width = <64>;
adi,source-bus-type = <0>;
adi,destination-bus-width = <32>;
adi,destination-bus-type = <2>;
};
};
};
cf_ad9364_adc_core_0: cf-ad9361-lpc@79020000 {
compatible = "adi,axi-ad9361-6.00.a";
reg = <0x79020000 0x6000>;
dmas = <&rx_dma 0>;
dma-names = "rx";
spibus-connected = <&adc0_ad9361>;
adi,axi-decimation-core-available;
};
cf_ad9364_dac_core_0: cf-ad9361-dds-core-lpc@79024000 {
compatible = "adi,axi-ad9361-dds-6.00.a";
reg = <0x79024000 0x1000>;
clocks = <&adc0_ad9361 13>;
clock-names = "sampl_clk";
dmas = <&tx_dma 0>;
dma-names = "tx";
adi,axi-interpolation-core-available;
adi,axi-dds-default-scale = <0>;
};
mwipcore@43c00000 {
compatible = "mathworks,mwipcore-axi4lite-v1.00";
reg = <0x43c00000 0xffff>;
};
};
};
&spi0 {
status = "okay";
adc0_ad9361: ad9361-phy@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi,ad9361";
reg = <0>;
/* SPI Setup */
spi-cpha;
spi-max-frequency = <10000000>;
/* Clocks */
clocks = <&ad9361_clkin 0>;
clock-names = "ad9361_ext_refclk";
clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
#clock-cells = <1>;
// adi,debug-mode-enable;
/* Digital Interface Control */
/* adi,digital-interface-tune-skip-mode:
* 0 = TUNE RX&TX
* 1 = SKIP TX
* 2 = SKIP ALL
*/
adi,digital-interface-tune-skip-mode = <0>;
adi,pp-tx-swap-enable;
adi,pp-rx-swap-enable;
adi,rx-frame-pulse-mode-enable;
adi,lvds-mode-enable;
adi,lvds-bias-mV = <150>;
adi,lvds-rx-onchip-termination-enable;
adi,rx-data-delay = <4>;
adi,tx-fb-clock-delay = <7>;
//adi,fdd-rx-rate-2tx-enable;
adi,dcxo-coarse-and-fine-tune = <8 5920>;
//adi,xo-disable-use-ext-refclk-enable;
/* Mode Setup */
adi,2rx-2tx-mode-enable;
//adi,split-gain-table-mode-enable;
/* ENSM Mode */
adi,frequency-division-duplex-mode-enable;
//adi,ensm-enable-pin-pulse-mode-enable;
//adi,ensm-enable-txnrx-control-enable;
/* adi,rx-rf-port-input-select:
* 0 = (RX1A_N & RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced
* 1 = (RX1B_N & RX1B_P) and (RX2B_N & RX2B_P) enabled; balanced
* 2 = (RX1C_N & RX1C_P) and (RX2C_N & RX2C_P) enabled; balanced
*
* 3 = RX1A_N and RX2A_N enabled; unbalanced
* 4 = RX1A_P and RX2A_P enabled; unbalanced
* 5 = RX1B_N and RX2B_N enabled; unbalanced
* 6 = RX1B_P and RX2B_P enabled; unbalanced
* 7 = RX1C_N and RX2C_N enabled; unbalanced
* 8 = RX1C_P and RX2C_P enabled; unbalanced
*/
adi,rx-rf-port-input-select = <0>; /* (RX1A_N & RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced */
/* adi,tx-rf-port-input-select:
* 0 TX1A, TX2A
* 1 TX1B, TX2B
*/
adi,tx-rf-port-input-select = <0>; /* TX1A, TX2A */
//adi,update-tx-gain-in-alert-enable;
adi,tx-attenuation-mdB = <10000>;
adi,tx-lo-powerdown-managed-enable;
adi,rf-rx-bandwidth-hz = <18000000>;
adi,rf-tx-bandwidth-hz = <18000000>;
adi,rx-synthesizer-frequency-hz = /bits/ 64 <2400000000>;
adi,tx-synthesizer-frequency-hz = /bits/ 64 <2400000000>;
/* BBPLL ADC R2CLK R1CLK CLKRF RSAMPL */
adi,rx-path-clock-frequencies = <983040000 245760000 122880000 61440000 30720000 30720000>;
/* BBPLL DAC T2CLK T1CLK CLKTF TSAMPL */
adi,tx-path-clock-frequencies = <983040000 122880000 122880000 61440000 30720000 30720000>;
/* Gain Control */
//adi,gaintable-name = "ad9361_std_gaintable";
/* adi,gc-rx[1|2]-mode:
* 0 = RF_GAIN_MGC
* 1 = RF_GAIN_FASTATTACK_AGC
* 2 = RF_GAIN_SLOWATTACK_AGC
* 3 = RF_GAIN_HYBRID_AGC
*/
adi,gc-rx1-mode = <2>;
adi,gc-rx2-mode = <2>;
adi,gc-adc-ovr-sample-size = <4>; /* sum 4 samples */
adi,gc-adc-small-overload-thresh = <47>; /* sum of squares */
adi,gc-adc-large-overload-thresh = <58>; /* sum of squares */
adi,gc-lmt-overload-high-thresh = <800>; /* mV */
adi,gc-lmt-overload-low-thresh = <704>; /* mV */
adi,gc-dec-pow-measurement-duration = <8192>; /* 0..524288 Samples */
adi,gc-low-power-thresh = <24>; /* 0..-64 dBFS vals are set pos */
//adi,gc-dig-gain-enable;
//adi,gc-max-dig-gain = <15>;
/* Manual Gain Control Setup */
//adi,mgc-rx1-ctrl-inp-enable; /* uncomment to use ctrl inputs */
//adi,mgc-rx2-ctrl-inp-enable; /* uncomment to use ctrl inputs */
adi,mgc-inc-gain-step = <2>;
adi,mgc-dec-gain-step = <2>;
/* adi,mgc-split-table-ctrl-inp-gain-mode:
* (relevant if adi,split-gain-table-mode-enable is set)
* 0 = AGC determine this
* 1 = only in LPF
* 2 = only in LMT
*/
adi,mgc-split-table-ctrl-inp-gain-mode = <0>;
/* Automatic Gain Control Setup */
adi,agc-attack-delay-extra-margin-us= <1>; /* us */
adi,agc-outer-thresh-high = <5>; /* -dBFS */
adi,agc-outer-thresh-high-dec-steps = <2>; /* 0..15 */
adi,agc-inner-thresh-high = <10>; /* -dBFS */
adi,agc-inner-thresh-high-dec-steps = <1>; /* 0..7 */
adi,agc-inner-thresh-low = <12>; /* -dBFS */
adi,agc-inner-thresh-low-inc-steps = <1>; /* 0..7 */
adi,agc-outer-thresh-low = <18>; /* -dBFS */
adi,agc-outer-thresh-low-inc-steps = <2>; /* 0..15 */
adi,agc-adc-small-overload-exceed-counter = <10>; /* 0..15 */
adi,agc-adc-large-overload-exceed-counter = <10>; /* 0..15 */
adi,agc-adc-large-overload-inc-steps = <2>; /* 0..15 */
//adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable;
adi,agc-lmt-overload-large-exceed-counter = <10>; /* 0..15 */
adi,agc-lmt-overload-small-exceed-counter = <10>; /* 0..15 */
adi,agc-lmt-overload-large-inc-steps = <2>; /* 0..7 */
//adi,agc-dig-saturation-exceed-counter = <3>; /* 0..15 */
//adi,agc-dig-gain-step-size = <4>; /* 1..8 */
//adi,agc-sync-for-gain-counter-enable;
adi,agc-gain-update-interval-us = <1000>; /* 1ms */
//adi,agc-immed-gain-change-if-large-adc-overload-enable;
//adi,agc-immed-gain-change-if-large-lmt-overload-enable;
/* Fast AGC */
adi,fagc-dec-pow-measurement-duration = <64>; /* 64 Samples */
//adi,fagc-allow-agc-gain-increase-enable;
adi,fagc-lp-thresh-increment-steps = <1>;
adi,fagc-lp-thresh-increment-time = <5>;
adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <8>;
adi,fagc-final-overrange-count = <3>;
//adi,fagc-gain-increase-after-gain-lock-enable;
adi,fagc-gain-index-type-after-exit-rx-mode = <0>;
adi,fagc-lmt-final-settling-steps = <1>;
adi,fagc-lock-level = <10>;
adi,fagc-lock-level-gain-increase-upper-limit = <5>;
adi,fagc-lock-level-lmt-gain-increase-enable;
adi,fagc-lpf-final-settling-steps = <1>;
adi,fagc-optimized-gain-offset = <5>;
adi,fagc-power-measurement-duration-in-state5 = <64>;
adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <10>;
adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable;
adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0>;
adi,fagc-rst-gla-large-adc-overload-enable;
adi,fagc-rst-gla-large-lmt-overload-enable;
adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <10>;
adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable;
adi,fagc-state-wait-time-ns = <260>;
adi,fagc-use-last-lock-level-for-set-gain-enable;
/* RSSI */
/* adi,rssi-restart-mode:
* 0 = AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN,
* 1 = EN_AGC_PIN_IS_PULLED_HIGH,
* 2 = ENTERS_RX_MODE,
* 3 = GAIN_CHANGE_OCCURS,
* 4 = SPI_WRITE_TO_REGISTER,
* 5 = GAIN_CHANGE_OCCURS_OR_EN_AGC_PIN_PULLED_HIGH,
*/
adi,rssi-restart-mode = <3>;
//adi,rssi-unit-is-rx-samples-enable;
adi,rssi-delay = <1>; /* 1us */
adi,rssi-wait = <1>; /* 1us */
adi,rssi-duration = <1000>; /* 1ms */
//test
adi,lvds-invert1-control = <0xFF>;
adi,lvds-invert2-control = <0x0F>;
adi,aux-adc-decimation = <256>;
adi,aux-adc-rate = <40000000>;
adi,dc-offset-count-high-range = <0x28>;
adi,dc-offset-count-low-range = <0x32>;
/* Control Outputs */
adi,ctrl-outs-index = <0>;
adi,ctrl-outs-enable-mask = <0xFF>;
/* AuxADC Temp Sense Control */
adi,temp-sense-measurement-interval-ms = <1000>;
adi,temp-sense-offset-signed = <0xCE>;
adi,temp-sense-periodic-measurement-enable;
/* AuxDAC Control */
adi,aux-dac-manual-mode-enable;
adi,aux-dac1-default-value-mV = <0>;
//adi,aux-dac1-active-in-rx-enable;
//adi,aux-dac1-active-in-tx-enable;
//adi,aux-dac1-active-in-alert-enable;
adi,aux-dac1-rx-delay-us = <0>;
adi,aux-dac1-tx-delay-us = <0>;
adi,aux-dac2-default-value-mV = <0>;
//adi,aux-dac2-active-in-rx-enable;
//adi,aux-dac2-active-in-tx-enable;
//adi,aux-dac2-active-in-alert-enable;
adi,aux-dac2-rx-delay-us = <0>;
adi,aux-dac2-tx-delay-us = <0>;
adi,delay-rx-data = <0>;
adi,rx-data-clock-delay = <0>;
adi,tx-data-delay = <0>;
// en_agc-gpios = <&gpio0 122 0>;
sync-gpios = <&gpio0 99 0>;
reset-gpios = <&gpio0 54 0>;
enable-gpios = <&gpio0 55 0>;
txnrx-gpios = <&gpio0 56 0>;
};
};
# 11 "zynq-antsdre200.dts" 2
# 24 "zynq-antsdre200.dts"
Change q.
[edited by: Novas228 at 11:19 AM (GMT -4) on 24 May 2023]
