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Hardware validation for ADRV9009 transceiver chip

Category: Hardware
Product Number: ADRV9009-ZU11EG
Software Version: 2018.2

Hello!

Currently working on a design that utilizes both the ad9528 clock generator and adrv9009 tranceiver IC's. As the hardware verification is still in progress, a complete FPGA target for the adrv9009 is still in development. Currently have been able to develop and complete a device tree to load the ad9528 driver and have used spidev as a compatible for peeks/pokes to it's register map throughout the debugging process. Recently have been attempting to do the same for the adrv9009 to check hardware connections are made properly and that the device is powered, but unable to find a register map to validate against.

Are there any recommendations using spidev or a similar method to communicate and check the status of the adrv9009 transceiver over the SPI interface without having a complete adrv9009 device tree to load the driver? Looking for something simple to read the PROD_ID register or similar, if possible.

Thank you,

Stephen

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  • Hello,

    If you want adrv9009 as a minimal spi device you will need to modify the driver, more exactly in the probe function keep only the basic functionality (debufs_reg_access I think is what you are looking for validation of the communication with the device) and just register it as an iio device. This might not be that straightforward taking into account that this chip is pretty complex.

    The linux drivers are usually designed to provide full or most of the functionalities a specific part supports.

    Regards,

    Antoniu

Reply
  • Hello,

    If you want adrv9009 as a minimal spi device you will need to modify the driver, more exactly in the probe function keep only the basic functionality (debufs_reg_access I think is what you are looking for validation of the communication with the device) and just register it as an iio device. This might not be that straightforward taking into account that this chip is pretty complex.

    The linux drivers are usually designed to provide full or most of the functionalities a specific part supports.

    Regards,

    Antoniu

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