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JESD eyescan lane errors for AD9695 testing

Category: Software


I want to evaluate my ad9695 eval board's jesd link performance, so I used your ad9695 fmc reference design but changed from subclass 1 to subclass 0 since there's only a single device.

Then I launched your jesd eyescan application and tested the jesd link. I'm wondering why there're so many errors in the lane status, since I used your reference design so there should be no problem!

The errors actually keep accumulating, the picture I show here is the result after about 10 mins connection.

Please tell me what could be the causing of this, thanks!

Parents Reply
  • Hi Michael,

    Sorry to bother you again. I'd like to ask you a simple question regarding this jesd eyescan application.

    So in the reference design, we have a jesd rx in the fpga side, and a tx in the ad9695 converter side. Does this software only evaluate the functionality of the rx side, or it evaluates both the tx&rx?