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JESD eyescan lane errors for AD9695 testing

Category: Software

Hi,

I want to evaluate my ad9695 eval board's jesd link performance, so I used your ad9695 fmc reference design but changed from subclass 1 to subclass 0 since there's only a single device.

Then I launched your jesd eyescan application and tested the jesd link. I'm wondering why there're so many errors in the lane status, since I used your reference design so there should be no problem!

The errors actually keep accumulating, the picture I show here is the result after about 10 mins connection.

Please tell me what could be the causing of this, thanks!

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  • It looks like the AD9695 devicetree is still using the deprecated/old link bring-up infrastructure.

    (not using the jesd204-fsm) so I think this devicetree needs some updates.

    But I think this should not be the problem here.

    I'm wondering is your 1300MHz converter clock and the 325MHz link clock frequency locked?

    Both signal generators using the same 10MHz reference?

    -Michael 

  • Hi Michael,

    Thanks for the quick reply.

    I see, do you have the updated devicetree file that I can use? (Or some similar devicetrees for my reference?)

    Since we currently do not have an equipment that be able to provide clocks with the same reference signal, we were using two signal generators to provide the sampling clock and the reference clock. But in the log file it says that the PLL is locked, and in IIO-Oscilloscope the data waveform looks pretty ok.

    So can I just ignore these errors and say that our jesd rx link is correctly functioned? thanks.

  • The devicetree is not the problem. It was just a side note...

    The errors will disappear once you frequency lock both clocks.

    The EYE may look correctly, but these lane errors will likely be visible in the RF spectrum.

    -Michael   

  • Hi Michael,

    Got it, thanks for the explanation!

  • Hi Michael,

    Sorry to bother you again. I'd like to ask you a simple question regarding this jesd eyescan application.

    So in the reference design, we have a jesd rx in the fpga side, and a tx in the ad9695 converter side. Does this software only evaluate the functionality of the rx side, or it evaluates both the tx&rx?

    Thanks!

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  • Hi Michael,

    Sorry to bother you again. I'd like to ask you a simple question regarding this jesd eyescan application.

    So in the reference design, we have a jesd rx in the fpga side, and a tx in the ad9695 converter side. Does this software only evaluate the functionality of the rx side, or it evaluates both the tx&rx?

    Thanks!

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