JESD eyescan lane errors for AD9695 testing

It looks like the AD9695 devicetree is still using the deprecated/old link bring-up infrastructure.

(not using the jesd204-fsm) so I think this devicetree needs some updates.

But I think this should not be the problem here.

I'm wondering is your 1300MHz converter clock and the 325MHz link clock frequency locked?

Both signal generators using the same 10MHz reference?

-Michael 

Hi Michael,

Thanks for the quick reply.

I see, do you have the updated devicetree file that I can use? (Or some similar devicetrees for my reference?)

Since we currently do not have an equipment that be able to provide clocks with the same reference signal, we were using two signal generators to provide the sampling clock and the reference clock. But in the log file it says that the PLL is locked, and in IIO-Oscilloscope the data waveform looks pretty ok.

So can I just ignore these errors and say that our jesd rx link is correctly functioned? thanks.

The devicetree is not the problem. It was just a side note...

The errors will disappear once you frequency lock both clocks.

The EYE may look correctly, but these lane errors will likely be visible in the RF spectrum.

-Michael   

Hi Michael,

Got it, thanks for the explanation!

Hi Michael,

Sorry to bother you again. I'd like to ask you a simple question regarding this jesd eyescan application.

So in the reference design, we have a jesd rx in the fpga side, and a tx in the ad9695 converter side. Does this software only evaluate the functionality of the rx side, or it evaluates both the tx&rx?

Thanks!

Eye Scan can be only implemented on the JESD204 receiver side.

If you have a DAC type device and the JESD204 link direction is reversed, then the DA data converter needs to support that.

Our latest generation of data converters do have a similar JESD204B/C Receiver PHY Eye Scan feature.

If you are interested more, take a look at the "AD9081/AD9082 System Development User Guide UG-1578" 

-Michael

Hi Michael,

I got it, thanks again!