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changing sample rates in AD9695_FMC example

Category: Software
Product Number: ad9695-625
Software Version: kupier master
  • setup
    • kupier Linux
      • ad9695 Boot.bin, devicetree, zynqmp common ...
      • zcu102 with ad9695-625
    • hardware setup, and software settings, per ad9695_fmc example wiki documentation

when I boot this I can talk to the SPI and see the iio interface but I don't get any data when using iio_scope, obviously because the device is overclocked.

to change the clocks I used/calculated the relationships to the lane rate and selected a mid range lane rate for the 625MSPS board. I verified the synchrona can output these frequencies:

  • SYSREF: 1.5625 MHZ (Lane Rate/256)
  • REFCLK: 100MHz (Lane Rate/40)
  • DEVICECLK: 100MHz (Lane Rate/40)
  • ADCCLK: 400MHz (Lane Rate/10)
  • JESD204B Lane Rate: 4Gbps

I searched the decompiled device tree and found entries matching the old clock numbers in these locations:

phandle originals  value decimal alias
X22 ADC_SYSREF 4D7C6D 5078125 clk 2 and spi
X40 DEV_CLK 135F1B40 325000000 clk 1
setting in spi interface ADCCLK 4D7C6D00 1300000000 spi sample rate

I changed these to the new clock frequencies accordingly

I went through the HDL documentation and scrips to change the JESD transceiver clocks to reflect these new values

when this didnt work I also changed the constraints files clock rates system clock period to 10ns and spi1.0 clock rate to 130ns (though I changed the spi clock after failure)

all of this leads to a failure to set up the spi interface. I have attached original vs new: tcl scripts, device trees, and system boot text. can anyone tell me what Im missing or what Im doing wrong?

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