Hi everyone!
I am trying to get my AD364 clock select line to use the onboard 40MHz clock For some reason, using the latest Kuiper build, the clock is not selected by default. The FPGA output pin reads 0.7~ V and so Q6 is not grounding out the AD772 for the right path. I only noticed this because I was getting horrific phase noise, if you can even call it that, but was still roughly on the right frequency for my LO.
Presently, I am investigating whether it's a broken pin, or something else, and so I am driving the GPIO line directly from the FPGA design.
Question: what's the right way to have Linux drive this pin from the start? Is there a device tree entry that could work, or is that just a no-mans-land of driver support at this point for the z7020 version? Some of the other articles touch on this for the z7035, but I see nothing specific to the z7020.
I'd really like to avoid this sort of spaghetti, and so I am considering just hand-editing the HDL to get an output of a similar nature, but this was just expedient.
