Reload bitstream in Zc706 on the fly from ARM

Question

We are developing a custom design on Zc706 EVM using AD9680. I'd like to reload FPGA bitstreams on the fly from the ARM. But when I switch bitstreams the interface to the AD9680 no longer works. Inside /sys/bus/platform/drivers Xilinx Watchdog axi-jesd204-tx i2c-gpio reset_zynq ad73311 axi-pulse-capture i2c-mux-gpmux rotary-encoder ad7606 axi-spdif iio_gen_mux sdhci-arasan ad_adc axi_adxcvr iio_interrupt_trigger snd-soc-dummy adau7002 axi_fan_control_driver imx_usb soc-audio adau7118 axi_fmcadc5_sync jesd204_top_device spi-engine adi,axi-pwmgen axi_jesd204b_gt leds-gpio ssm2305 adi-axi-clkgen axi_jesd204b_v51 lt3651-charger syscon adi_axi_data_offload axi_sysid ltc2952-poweroff tegra-udc adi_iio_fakedev cdns-i2c m2k_dac uio_dmem_genirq admc_adc cdns-spi m2k_fabric uio_pdrv_genirq admc_ctrl cdns-wdt m2k_logic_analyzer usb_phy_generic admc_speed cf_axi_adc macb usbmisc_imx adp5520-backlight cf_axi_dds mathworks_generic_of xadc adp5520-gpio cf_axi_tdd mmio-mux xhci-hcd adp5520-keys chipidea-usb2 msm_hsusb xiic-i2c adp5520-led ci_hdrc mwipcore xilinx-axipmon alarmtimer cpuidle-zynq of_adjustable_clk xilinx-udc armv7-pmu dma-axi-dmac of_fixed_clk xilinx_spi asoc-simple-card dwc2 of_fixed_factor_clk xuartps asoc-simple-card-adrv936x-box dwc3 one-bit-adc-dac zynq-gpio axi-adc-trigger dwc3-of-simple physmap-flash zynq-ocm axi-framebuffer fb_seps525 poweroff-gpio zynq-pinctrl axi-hdmi gpio-clk poweroff-restart zynq-qspi axi-hdmi-rx gpio-keys pwrseq_emmc zynq_fpga_manager axi-i2s gpio-mux pwrseq_simple axi-intr-monitor hdmi-audio-codec reg-dummy axi-jesd204-rx hmc425a reg-fixed-voltage Inside /sys/bus/platform/devices 200.rstc 79000000.axi-clkgen e000d000.spi f8f00600.timer 40400000.dma 7c400000.rx-dmac e0100000.mmc f8f02000.cache-controller 41600000.i2c Fixed MDIO bus.0 f8000000.slcr fixedregulator 43000000.dma adv7511_hdmi_snd f8001000.timer fpga-axi@0 43c00000.ipRegLogic amba_pl f8002000.timer fpga-full 44a10000.ad_ip_jesd204_tpl_adc axi f8005000.watchdog gpio_keys 44a10000.axi-ad9680-hpc ci_hdrc.0 f8006000.memory-controller hdmi-audio-codec.0.auto 44a50000.axi-adxcvr-rx cpuidle-zynq.0 f8007000.devcfg leds 44aa0000.axi-jesd204-rx e0001000.serial f8007100.adc reg-dummy 45000000.axi-sysid-0 e0002000.usb f800c000.ocmc replicator 700.pinctrl e0006000.spi f800d000.efuse snd-soc-dummy 70e00000.axi_hdmi e000a000.gpio f8891000.pmu 75c00000.axi-spdif-tx e000b000.ethernet f8f00200.timer Refering to the post "Resetting" AD9361 from software? We tried unbinding cf_axi_adc and axi_jesd204_rx devices and then load the second bitstream. But when axi_jesd204_rx is unbinded the following error occurs Unable to handle kernel NULL pointer dereference at virtual address 000001dci-jesd204-rx /sys/bus/platform/drivers/axi-jesd204-rx/i pgd = 19ba2da9ect:/sys/bus/platform/drivers/axi-jesd204-rx# echo 44aa0000.axi-jesd204-rx /sys/bus/platform/drivers/axi-jesd204-rx/uni [000001dc] *pgd=00000000 Internal error: Oops: 5 [#1] PREEMPT SMP ARM Modules linked in: uio_pdrv_genirq CPU: 0 PID: 517 Comm: sh Tainted: G O 5.10.0-xilinx-v2021.1 #1 Hardware name: Xilinx Zynq Platform PC is at jesd204_fsm_stop+0x0/0x3c LR is at axi_jesd204_rx_remove+0x18/0x8c pc : [] lr : [] psr: a0070013 sp : c22a9e60 ip : c240a080 fp : 00000000 r10: 00000000 r9 : 00000051 r8 : c190f454 r7 : c14b48cc r6 : c190f410 r5 : c1916000 r4 : c2192f40 r3 : c08b1208 r2 : 00000000 r1 : ffffffff r0 : 00000000 Flags: NzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment none Control: 18c5387d Table: 026c404a DAC: 00000051 Process sh (pid: 517, stack limit = 0x6264f57d) Stack: (0xc22a9e60 to 0xc22aa000) 9e60: c1916010 c1916010 c190f410 c04c3080 c1916010 c14b48cc c190f410 c04c0c80 9e80: c1916010 c190f410 c1916054 c1916010 00000018 c04c1b90 c1437e48 c22bd800 9ea0: c14b48cc c04bf6dc 00000018 c2265a80 c22bd800 c22a9f78 c2265a90 c02d16c4 9ec0: 00000000 00000000 00000001 c2337480 00000000 005ab370 c22a8000 c22a9f78 9ee0: c02d15cc 00000018 00000000 c0240f90 ffffff9c a00f0013 c2330000 00000003 9f00: c22a8000 d11c7c25 0000000a c2393c00 00000000 c22a8000 00000001 c25c8b40 9f20: 0000000a c0254878 00000000 c25c8b40 0000000a ffffe000 c25c8b40 d11c7c25 9f40: c25c8b40 00000001 c22a8000 d11c7c25 0000000a c2337480 c2337480 c22a8000 9f60: 005ab370 00000000 00000000 00000004 00000000 c0241430 00000000 00000000 9f80: c2393c00 d11c7c25 00000000 00000018 005ab370 b6f0f320 00000004 c0100264 9fa0: c22a8000 c0100060 00000018 005ab370 00000001 005ab370 00000018 00000000 9fc0: 00000018 005ab370 b6f0f320 00000004 b6ea5c78 00000000 00586850 00000000 9fe0: 00000004 beaee9d8 b6e42ecf b6dcf196 40070030 00000001 00000000 00000000 [] (jesd204_fsm_stop) from [] (0xc14b48cc) Code: e58dc000 ebfffe7f e28dd014 e49df004 (e5d031dc) ---[ end trace a5a13dc559612ffc ]--- Please help us in reloading bitstream successfully after unbing the required devices.

mhennerich · Accepted Answer

Works for me - can you provide more information? Complete boot log, etc. 
 root@analog:~# resize
COLUMNS=203;
LINES=58;
export COLUMNS LINES;
root@analog:~# dmesg -n7
root@analog:~# echo 44aa0000.axi-jesd204-rx > /sys/bus/platform/drivers/axi-jesd204-rx/unbind 
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition opt_post_running_stage -> opt_post_running_stage
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition opt_post_running_stage -> link_running
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition link_running -> link_enable
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition link_enable -> clocks_enable
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition clocks_enable -> opt_setup_stage5
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition opt_setup_stage5 -> opt_setup_stage4
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition opt_setup_stage4 -> opt_setup_stage3
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition opt_setup_stage3 -> opt_setup_stage2
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition opt_setup_stage2 -> opt_setup_stage1
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition opt_setup_stage1 -> link_setup
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition link_setup -> clk_sync_stage3
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition clk_sync_stage3 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage1
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition clk_sync_stage1 -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition link_pre_setup -> link_supported
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition link_supported -> link_init
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition link_init -> device_init
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition device_init -> idle
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition device_init -> idle
root@analog:~# echo 44aa0000.axi-jesd204-rx > /sys/bus/platform/drivers/axi-jesd204-rx/bind 
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition idle -> idle
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition device_init -> link_init
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition link_pre_setup -> clk_sync_stage1
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition clk_sync_stage1 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage3
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition clk_sync_stage3 -> link_setup
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition link_setup -> opt_setup_stage1
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition opt_setup_stage1 -> opt_setup_stage2
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition opt_setup_stage2 -> opt_setup_stage3
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition opt_setup_stage3 -> opt_setup_stage4
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition opt_setup_stage4 -> opt_setup_stage5
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition opt_setup_stage5 -> clocks_enable
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition clocks_enable -> link_enable
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition link_enable -> link_running
jesd204: /axi/spi@e0006000/ad9680@2,jesd204:1,parent=spi0.2: JESD204[0:0] transition link_running -> opt_post_running_stage
axi-jesd204-rx 44aa0000.axi-jesd204-rx: AXI-JESD204-RX (1.07.a) at 0x44AA0000. Encoder 8b10b, width 4/4, lanes 4, jesd204-fsm.
root@analog:~# uname -a
Linux analog 5.10.0-98221-gd546169f6161 #7098 SMP PREEMPT Thu Jun 16 06:51:58 IST 2022 armv7l GNU/Linux
root@analog:~#)

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Reload bitstream in Zc706 on the fly from ARM