ADRV9002 driver hang on FH enable

jreigle on May 25, 2022

Thread Summary

The user is experiencing a driver hang when attempting to enable frequency hopping (FH) on the ADRV9002 with a custom board and Altera 5.4.84 kernel. The issue occurs during the 'adi_adrv9001_cals_InitCals_Run' function call, with errors indicating ARM memory is not accessible. The final answer suggests the problem is likely hardware-related, as the driver works with non-FH profiles and the issue is not reproducible on the ZCU102 eval board. The user is advised to check power supply lines and consider using a typical LTE profile for further testing.
AI Generated Content

Category: Software

Product Number: ADRV9002

Hello,

We are using the ADRV9002 with a custom board and are attempting to use the frequency hopping feature. The driver we are using is the one contained in the adrv9002 kernel branch - some very minor porting work was required to bring this into our local build and the driver is working well outside of frequency hopping.

TES 0.20.0 was used to generate a frequency hopping enabled profile. When the driver attempts to load with FH enabled, we see a delay of approximately 1 minute before the following messages are produced:

[ 72.254643] adrv9002 spi0.0: [ERROR]: Error number 3 (0x00000003), Recovery action -101.In file drivers/iio/adc/navassa/devices/adrv9001/public/src/adi_adrv9001_arm.c, in function adi_adrv9001_arm_CmdStatus_Wait, in line 678, variable name device.Error message ArmCmdStatusWait() failed due to thrown ARM error. ARM time out .
[ 72.297757] adrv9002 spi0.0: adrv9002_setup, 2861: failed with "ArmCmdStatusWait() failed due to thrown ARM error. ARM time out " (3)

[   75.111140] adrv9002 spi0.0: [ERROR]: Error number 1 (0x00000001), Recovery action -2.In file drivers/iio/adc/navassa/devices/adrv9001/public/src/adi_adrv9001_powermanagement.c, in function adi_adrv9001_powermanagement_Configure_Validate, in line 39, variable name readPattern.Error message ARM memory is not accessible. Check whether device clock and/or power is connected to the ADRV9001 board.
[   75.146262] adrv9002 spi0.0: [ERROR]: Error number 1 (0x00000001), Recovery action -2.In file drivers/iio/adc/navassa/devices/adrv9001/public/src/adi_adrv9001_powermanagement.c, in function adi_adrv9001_powermanagement_Configure, in line 70, variable name NULL.Error message ARM memory is not accessible. Check whether device clock and/or power is connected to the ADRV9001 board.
[   75.179999] adrv9002 spi0.0: adrv9002_power_mgmt_config, 2602: failed with "ARM memory is not accessible. Check whether device clock and/or power is connected to the ADRV9001 board" (1)
[   75.197890] cf_axi_adc: probe of ff220000.axi-adrv9002-rx-lpc failed with error -22

After this point the driver fails to attach and the device is non-operational. Some investigation has found the failure is occurring somewhere related to the 'adi_adrv9001_cals_InitCals_Run' function call. I understand that the FH tables are supposed to be provided via sysfs, however the driver doesn't load to this point so I am not sure what other steps are required other than providing the FH enabled profile.

Any guidance would be appreciated.

Thanks,

Justin

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ADIApproved

on Jun 1, 2022 5:15 AM
0
Hi,

Which linux branch are you using? Can you also share your profile so I can try and load it on my end?

- Nuno Sá
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jreigle on Jun 1, 2022 12:03 PM in reply to ADIApproved

Hi Nuno,

Thanks for the follow up. We are using the drivers located in this branch:
https://github.com/analogdevicesinc/linux/tree/adrv9002

Brought into our Altera 5.4.84 kernel.

Profile is attached:

Fullscreen test_profile_freq_hop.txt Download

{ "clocks": { "deviceClock_kHz": 38400, "clkPllVcoFreq_daHz": 384000000, "clkPllHsDiv": 0, "clkPllMode": 1, "clk1105Div": 2, "armClkDiv": 6, "armPowerSavingClkDiv": 1, "refClockOutEnable": true, "auxPllPower": 2, "clkPllPower": 2, "padRefClkDrv": 0, "extLo1OutFreq_kHz": 0, "extLo2OutFreq_kHz": 0, "rfPll1LoMode": 0, "rfPll2LoMode": 0, "ext1LoType": 0, "ext2LoType": 0, "rx1RfInputSel": 0, "rx2RfInputSel": 0, "extLo1Divider": 2, "extLo2Divider": 2, "rfPllPhaseSyncMode": 0, "rx1LoSelect": 2, "rx2LoSelect": 2, "tx1LoSelect": 1, "tx2LoSelect": 1, "rx1LoDivMode": 1, "rx2LoDivMode": 1, "tx1LoDivMode": 1, "tx2LoDivMode": 1, "loGen1Select": 1, "loGen2Select": 1 }, "rx": { "rxInitChannelMask": 195, "rxChannelCfg": [ { "profile": { "primarySigBandwidth_Hz": 20000000, "rxOutputRate_Hz": 40000000, "rxInterfaceSampleRate_Hz": 40000000, "rxOffsetLo_kHz": 490, "rxNcoEnable": true, "outputSignaling": 0, "filterOrder": 1, "filterOrderLp": 1, "hpAdcCorner": 20000000, "lpAdcCorner": 0, "adcClk_kHz": 960000, "rxCorner3dB_kHz": 10000, "rxCorner3dBLp_kHz": 10000, "tiaPower": 2, "tiaPowerLp": 2, "channelType": 1, "adcType": 1, "lpAdcCalMode": 0, "gainTableType": 0, "rxDpProfile": { "rxNbDecTop": { "scicBlk23En": 0, "scicBlk23DivFactor": 1, "scicBlk23LowRippleEn": 0, "decBy2Blk35En": 0, "decBy2Blk37En": 0, "decBy2Blk39En": 0, "decBy2Blk41En": 0, "decBy2Blk43En": 0, "decBy3Blk45En": 0, "decBy2Blk47En": 0 }, "rxWbDecTop": { "decBy2Blk25En": 0, "decBy2Blk27En": 0, "decBy2Blk29En": 0, "decBy2Blk31En": 0, "decBy2Blk33En": 0, "wbLpfBlk33p1En": 0 }, "rxDecTop": { "decBy3Blk15En": 0, "decBy2Hb3Blk17p1En": 1, "decBy2Hb4Blk17p2En": 0, "decBy2Hb5Blk19p1En": 1, "decBy2Hb6Blk19p2En": 0 }, "rxSincHBTop": { "sincGainMux": 1, "sincMux": 1, "hbMux": 4, "isGainCompEnabled": 0, "gainComp9GainI": [ 16384, 16384, 16384, 16384, 16384, 16384 ], "gainComp9GainQ": [ 0, 0, 0, 0, 0, 0 ] }, "rxNbDem": { "dpInFifo": { "dpInFifoEn": 0, "dpInFifoMode": 0, "dpInFifoTestDataSel": 0 }, "rxNbNco": { "rxNbNcoEn": 0, "rxNbNcoConfig": { "freq": 0, "sampleFreq": 0, "phase": 0, "realOut": 0 } }, "rxWbNbCompPFir": { "bankSel": 0, "rxWbNbCompPFirInMuxSel": 0, "rxWbNbCompPFirEn": 1 }, "resamp": { "rxResampEn": 0, "resampPhaseI": 0, "resampPhaseQ": 0 }, "gsOutMuxSel": 1, "rxOutSel": 0, "rxRoundMode": 0, "dpArmSel": 0 } }, "lnaConfig": { "externalLnaPresent": false, "gpioSourceSel": 0, "externalLnaPinSel": 0, "settlingDelay": 0, "numberLnaGainSteps": 0, "lnaGainSteps_mdB": [ 0, 0, 0, 0 ], "lnaDigitalGainDelay": 0, "minGainIndex": 0 }, "rxSsiConfig": { "ssiType": 2, "ssiDataFormatSel": 4, "numLaneSel": 1, "strobeType": 0, "lsbFirst": 0, "qFirst": 0, "txRefClockPin": 0, "lvdsIBitInversion": false, "lvdsQBitInversion": false, "lvdsStrobeBitInversion": false, "lvdsUseLsbIn12bitMode": 0, "lvdsRxClkInversionEn": false, "cmosDdrPosClkEn": false, "cmosClkInversionEn": false, "ddrEn": true, "rxMaskStrobeEn": false } } }, { "profile": { "primarySigBandwidth_Hz": 20000000, "rxOutputRate_Hz": 40000000, "rxInterfaceSampleRate_Hz": 40000000, "rxOffsetLo_kHz": 490, "rxNcoEnable": true, "outputSignaling": 0, "filterOrder": 1, "filterOrderLp": 1, "hpAdcCorner": 20000000, "lpAdcCorner": 0, "adcClk_kHz": 960000, "rxCorner3dB_kHz": 10000, "rxCorner3dBLp_kHz": 10000, "tiaPower": 2, "tiaPowerLp": 2, "channelType": 2, "adcType": 1, "lpAdcCalMode": 0, "gainTableType": 0, "rxDpProfile": { "rxNbDecTop": { "scicBlk23En": 0, "scicBlk23DivFactor": 1, "scicBlk23LowRippleEn": 0, "decBy2Blk35En": 0, "decBy2Blk37En": 0, "decBy2Blk39En": 0, "decBy2Blk41En": 0, "decBy2Blk43En": 0, "decBy3Blk45En": 0, "decBy2Blk47En": 0 }, "rxWbDecTop": { "decBy2Blk25En": 0, "decBy2Blk27En": 0, "decBy2Blk29En": 0, "decBy2Blk31En": 0, "decBy2Blk33En": 0, "wbLpfBlk33p1En": 0 }, "rxDecTop": { "decBy3Blk15En": 0, "decBy2Hb3Blk17p1En": 1, "decBy2Hb4Blk17p2En": 0, "decBy2Hb5Blk19p1En": 1, "decBy2Hb6Blk19p2En": 0 }, "rxSincHBTop": { "sincGainMux": 1, "sincMux": 1, "hbMux": 4, "isGainCompEnabled": 0, "gainComp9GainI": [ 16384, 16384, 16384, 16384, 16384, 16384 ], "gainComp9GainQ": [ 0, 0, 0, 0, 0, 0 ] }, "rxNbDem": { "dpInFifo": { "dpInFifoEn": 0, "dpInFifoMode": 0, "dpInFifoTestDataSel": 0 }, "rxNbNco": { "rxNbNcoEn": 0, "rxNbNcoConfig": { "freq": 0, "sampleFreq": 0, "phase": 0, "realOut": 0 } }, "rxWbNbCompPFir": { "bankSel": 2, "rxWbNbCompPFirInMuxSel": 0, "rxWbNbCompPFirEn": 1 }, "resamp": { "rxResampEn": 0, "resampPhaseI": 0, "resampPhaseQ": 0 }, "gsOutMuxSel": 1, "rxOutSel": 0, "rxRoundMode": 0, "dpArmSel": 0 } }, "lnaConfig": { "externalLnaPresent": false, "gpioSourceSel": 0, "externalLnaPinSel": 0, "settlingDelay": 0, "numberLnaGainSteps": 0, "lnaGainSteps_mdB": [ 0, 0, 0, 0 ], "lnaDigitalGainDelay": 0, "minGainIndex": 0 }, "rxSsiConfig": { "ssiType": 2, "ssiDataFormatSel": 4, "numLaneSel": 1, "strobeType": 0, "lsbFirst": 0, "qFirst": 0, "txRefClockPin": 0, "lvdsIBitInversion": false, "lvdsQBitInversion": false, "lvdsStrobeBitInversion": false, "lvdsUseLsbIn12bitMode": 0, "lvdsRxClkInversionEn": false, "cmosDdrPosClkEn": false, "cmosClkInversionEn": false, "ddrEn": true, "rxMaskStrobeEn": false } } }, { "profile": { "primarySigBandwidth_Hz": 12500, "rxOutputRate_Hz": 0, "rxInterfaceSampleRate_Hz": 0, "rxOffsetLo_kHz": 0, "rxNcoEnable": false, "outputSignaling": 0, "filterOrder": 1, "filterOrderLp": 1, "hpAdcCorner": 0, "lpAdcCorner": 0, "adcClk_kHz": 0, "rxCorner3dB_kHz": 0, "rxCorner3dBLp_kHz": 0, "tiaPower": 2, "tiaPowerLp": 2, "channelType": 0, "adcType": 1, "lpAdcCalMode": 0, "gainTableType": 0, "rxDpProfile": { "rxNbDecTop": { "scicBlk23En": 0, "scicBlk23DivFactor": 0, "scicBlk23LowRippleEn": 0, "decBy2Blk35En": 0, "decBy2Blk37En": 0, "decBy2Blk39En": 0, "decBy2Blk41En": 0, "decBy2Blk43En": 0, "decBy3Blk45En": 0, "decBy2Blk47En": 0 }, "rxWbDecTop": { "decBy2Blk25En": 0, "decBy2Blk27En": 0, "decBy2Blk29En": 0, "decBy2Blk31En": 0, "decBy2Blk33En": 0, "wbLpfBlk33p1En": 0 }, "rxDecTop": { "decBy3Blk15En": 0, "decBy2Hb3Blk17p1En": 0, "decBy2Hb4Blk17p2En": 0, "decBy2Hb5Blk19p1En": 0, "decBy2Hb6Blk19p2En": 0 }, "rxSincHBTop": { "sincGainMux": 1, "sincMux": 0, "hbMux": 4, "isGainCompEnabled": 0, "gainComp9GainI": [ 16384, 16384, 16384, 16384, 16384, 16384 ], "gainComp9GainQ": [ 0, 0, 0, 0, 0, 0 ] }, "rxNbDem": { "dpInFifo": { "dpInFifoEn": 0, "dpInFifoMode": 0, "dpInFifoTestDataSel": 0 }, "rxNbNco": { "rxNbNcoEn": 0, "rxNbNcoConfig": { "freq": 0, "sampleFreq": 0, "phase": 0, "realOut": 0 } }, "rxWbNbCompPFir": { "bankSel": 0, "rxWbNbCompPFirInMuxSel": 0, "rxWbNbCompPFirEn": 0 }, "resamp": { "rxResampEn": 0, "resampPhaseI": 0, "resampPhaseQ": 0 }, "gsOutMuxSel": 1, "rxOutSel": 0, "rxRoundMode": 0, "dpArmSel": 0 } }, "lnaConfig": { "externalLnaPresent": false, "gpioSourceSel": 0, "externalLnaPinSel": 0, "settlingDelay": 0, "numberLnaGainSteps": 0, "lnaGainSteps_mdB": [ 0, 0, 0, 0 ], "lnaDigitalGainDelay": 0, "minGainIndex": 0 }, "rxSsiConfig": { "ssiType": 0, "ssiDataFormatSel": 0, "numLaneSel": 0, "strobeType": 0, "lsbFirst": 0, "qFirst": 0, "txRefClockPin": 0, "lvdsIBitInversion": false, "lvdsQBitInversion": false, "lvdsStrobeBitInversion": false, "lvdsUseLsbIn12bitMode": 0, "lvdsRxClkInversionEn": false, "cmosDdrPosClkEn": false, "cmosClkInversionEn": false, "ddrEn": false, "rxMaskStrobeEn": false } } }, { "profile": { "primarySigBandwidth_Hz": 12500, "rxOutputRate_Hz": 0, "rxInterfaceSampleRate_Hz": 0, "rxOffsetLo_kHz": 0, "rxNcoEnable": false, "outputSignaling": 0, "filterOrder": 1, "filterOrderLp": 1, "hpAdcCorner": 0, "lpAdcCorner": 0, "adcClk_kHz": 0, "rxCorner3dB_kHz": 0, "rxCorner3dBLp_kHz": 0, "tiaPower": 2, "tiaPowerLp": 2, "channelType": 0, "adcType": 1, "lpAdcCalMode": 0, "gainTableType": 0, "rxDpProfile": { "rxNbDecTop": { "scicBlk23En": 0, "scicBlk23DivFactor": 0, "scicBlk23LowRippleEn": 0, "decBy2Blk35En": 0, "decBy2Blk37En": 0, "decBy2Blk39En": 0, "decBy2Blk41En": 0, "decBy2Blk43En": 0, "decBy3Blk45En": 0, "decBy2Blk47En": 0 }, "rxWbDecTop": { "decBy2Blk25En": 0, "decBy2Blk27En": 0, "decBy2Blk29En": 0, "decBy2Blk31En": 0, "decBy2Blk33En": 0, "wbLpfBlk33p1En": 0 }, "rxDecTop": { "decBy3Blk15En": 0, "decBy2Hb3Blk17p1En": 0, "decBy2Hb4Blk17p2En": 0, "decBy2Hb5Blk19p1En": 0, "decBy2Hb6Blk19p2En": 0 }, "rxSincHBTop": { "sincGainMux": 1, "sincMux": 0, "hbMux": 4, "isGainCompEnabled": 0, "gainComp9GainI": [ 16384, 16384, 16384, 16384, 16384, 16384 ], "gainComp9GainQ": [ 0, 0, 0, 0, 0, 0 ] }, "rxNbDem": { "dpInFifo": { "dpInFifoEn": 0, "dpInFifoMode": 0, "dpInFifoTestDataSel": 0 }, "rxNbNco": { "rxNbNcoEn": 0, "rxNbNcoConfig": { "freq": 0, "sampleFreq": 0, "phase": 0, "realOut": 0 } }, "rxWbNbCompPFir": { "bankSel": 0, "rxWbNbCompPFirInMuxSel": 0, "rxWbNbCompPFirEn": 0 }, "resamp": { "rxResampEn": 0, "resampPhaseI": 0, "resampPhaseQ": 0 }, "gsOutMuxSel": 1, "rxOutSel": 0, "rxRoundMode": 0, "dpArmSel": 0 } }, "lnaConfig": { "externalLnaPresent": false, "gpioSourceSel": 0, "externalLnaPinSel": 0, "settlingDelay": 0, "numberLnaGainSteps": 0, "lnaGainSteps_mdB": [ 0, 0, 0, 0 ], "lnaDigitalGainDelay": 0, "minGainIndex": 0 }, "rxSsiConfig": { "ssiType": 0, "ssiDataFormatSel": 0, "numLaneSel": 0, "strobeType": 0, "lsbFirst": 0, "qFirst": 0, "txRefClockPin": 0, "lvdsIBitInversion": false, "lvdsQBitInversion": false, "lvdsStrobeBitInversion": false, "lvdsUseLsbIn12bitMode": 0, "lvdsRxClkInversionEn": false, "cmosDdrPosClkEn": false, "cmosClkInversionEn": false, "ddrEn": false, "rxMaskStrobeEn": false } } }, { "profile": { "primarySigBandwidth_Hz": 20000000, "rxOutputRate_Hz": 40000000, "rxInterfaceSampleRate_Hz": 40000000, "rxOffsetLo_kHz": 0, "rxNcoEnable": false, "outputSignaling": 0, "filterOrder": 1, "filterOrderLp": 1, "hpAdcCorner": 50000000, "lpAdcCorner": 0, "adcClk_kHz": 960000, "rxCorner3dB_kHz": 100000, "rxCorner3dBLp_kHz": 100000, "tiaPower": 2, "tiaPowerLp": 2, "channelType": 64, "adcType": 1, "lpAdcCalMode": 0, "gainTableType": 0, "rxDpProfile": { "rxNbDecTop": { "scicBlk23En": 0, "scicBlk23DivFactor": 1, "scicBlk23LowRippleEn": 0, "decBy2Blk35En": 0, "decBy2Blk37En": 0, "decBy2Blk39En": 0, "decBy2Blk41En": 0, "decBy2Blk43En": 0, "decBy3Blk45En": 0, "decBy2Blk47En": 0 }, "rxWbDecTop": { "decBy2Blk25En": 0, "decBy2Blk27En": 0, "decBy2Blk29En": 0, "decBy2Blk31En": 0, "decBy2Blk33En": 0, "wbLpfBlk33p1En": 0 }, "rxDecTop": { "decBy3Blk15En": 0, "decBy2Hb3Blk17p1En": 1, "decBy2Hb4Blk17p2En": 0, "decBy2Hb5Blk19p1En": 1, "decBy2Hb6Blk19p2En": 0 }, "rxSincHBTop": { "sincGainMux": 1, "sincMux": 1, "hbMux": 2, "isGainCompEnabled": 0, "gainComp9GainI": [ 16384, 16384, 16384, 16384, 16384, 16384 ], "gainComp9GainQ": [ 0, 0, 0, 0, 0, 0 ] }, "rxNbDem": { "dpInFifo": { "dpInFifoEn": 0, "dpInFifoMode": 0, "dpInFifoTestDataSel": 0 }, "rxNbNco": { "rxNbNcoEn": 0, "rxNbNcoConfig": { "freq": 0, "sampleFreq": 0, "phase": 0, "realOut": 0 } }, "rxWbNbCompPFir": { "bankSel": 1, "rxWbNbCompPFirInMuxSel": 0, "rxWbNbCompPFirEn": 0 }, "resamp": { "rxResampEn": 0, "resampPhaseI": 0, "resampPhaseQ": 0 }, "gsOutMuxSel": 1, "rxOutSel": 0, "rxRoundMode": 0, "dpArmSel": 0 } }, "lnaConfig": { "externalLnaPresent": false, "gpioSourceSel": 0, "externalLnaPinSel": 0, "settlingDelay": 0, "numberLnaGainSteps": 0, "lnaGainSteps_mdB": [ 0, 0, 0, 0 ], "lnaDigitalGainDelay": 0, "minGainIndex": 0 }, "rxSsiConfig": { "ssiType": 2, "ssiDataFormatSel": 4, "numLaneSel": 1, "strobeType": 0, "lsbFirst": 0, "qFirst": 0, "txRefClockPin": 0, "lvdsIBitInversion": false, "lvdsQBitInversion": false, "lvdsStrobeBitInversion": false, "lvdsUseLsbIn12bitMode": 0, "lvdsRxClkInversionEn": false, "cmosDdrPosClkEn": false, "cmosClkInversionEn": false, "ddrEn": true, "rxMaskStrobeEn": false } } }, { "profile": { "primarySigBandwidth_Hz": 20000000, "rxOutputRate_Hz": 40000000, "rxInterfaceSampleRate_Hz": 40000000, "rxOffsetLo_kHz": 0, "rxNcoEnable": false, "outputSignaling": 0, "filterOrder": 1, "filterOrderLp": 1, "hpAdcCorner": 50000000, "lpAdcCorner": 0, "adcClk_kHz": 960000, "rxCorner3dB_kHz": 100000, "rxCorner3dBLp_kHz": 100000, "tiaPower": 2, "tiaPowerLp": 2, "channelType": 128, "adcType": 1, "lpAdcCalMode": 0, "gainTableType": 0, "rxDpProfile": { "rxNbDecTop": { "scicBlk23En": 0, "scicBlk23DivFactor": 1, "scicBlk23LowRippleEn": 0, "decBy2Blk35En": 0, "decBy2Blk37En": 0, "decBy2Blk39En": 0, "decBy2Blk41En": 0, "decBy2Blk43En": 0, "decBy3Blk45En": 0, "decBy2Blk47En": 0 }, "rxWbDecTop": { "decBy2Blk25En": 0, "decBy2Blk27En": 0, "decBy2Blk29En": 0, "decBy2Blk31En": 0, "decBy2Blk33En": 0, "wbLpfBlk33p1En": 0 }, "rxDecTop": { "decBy3Blk15En": 0, "decBy2Hb3Blk17p1En": 1, "decBy2Hb4Blk17p2En": 0, "decBy2Hb5Blk19p1En": 1, "decBy2Hb6Blk19p2En": 0 }, "rxSincHBTop": { "sincGainMux": 1, "sincMux": 1, "hbMux": 2, "isGainCompEnabled": 0, "gainComp9GainI": [ 16384, 16384, 16384, 16384, 16384, 16384 ], "gainComp9GainQ": [ 0, 0, 0, 0, 0, 0 ] }, "rxNbDem": { "dpInFifo": { "dpInFifoEn": 0, "dpInFifoMode": 0, "dpInFifoTestDataSel": 0 }, "rxNbNco": { "rxNbNcoEn": 0, "rxNbNcoConfig": { "freq": 0, "sampleFreq": 0, "phase": 0, "realOut": 0 } }, "rxWbNbCompPFir": { "bankSel": 3, "rxWbNbCompPFirInMuxSel": 0, "rxWbNbCompPFirEn": 0 }, "resamp": { "rxResampEn": 0, "resampPhaseI": 0, "resampPhaseQ": 0 }, "gsOutMuxSel": 1, "rxOutSel": 0, "rxRoundMode": 0, "dpArmSel": 0 } }, "lnaConfig": { "externalLnaPresent": false, "gpioSourceSel": 0, "externalLnaPinSel": 0, "settlingDelay": 0, "numberLnaGainSteps": 0, "lnaGainSteps_mdB": [ 0, 0, 0, 0 ], "lnaDigitalGainDelay": 0, "minGainIndex": 0 }, "rxSsiConfig": { "ssiType": 2, "ssiDataFormatSel": 4, "numLaneSel": 1, "strobeType": 0, "lsbFirst": 0, "qFirst": 0, "txRefClockPin": 0, "lvdsIBitInversion": false, "lvdsQBitInversion": false, "lvdsStrobeBitInversion": false, "lvdsUseLsbIn12bitMode": 0, "lvdsRxClkInversionEn": false, "cmosDdrPosClkEn": false, "cmosClkInversionEn": false, "ddrEn": true, "rxMaskStrobeEn": false } } }, { "profile": { "primarySigBandwidth_Hz": 12500, "rxOutputRate_Hz": 0, "rxInterfaceSampleRate_Hz": 0, "rxOffsetLo_kHz": 0, "rxNcoEnable": false, "outputSignaling": 0, "filterOrder": 1, "filterOrderLp": 1, "hpAdcCorner": 0, "lpAdcCorner": 0, "adcClk_kHz": 0, "rxCorner3dB_kHz": 0, "rxCorner3dBLp_kHz": 0, "tiaPower": 2, "tiaPowerLp": 2, "channelType": 0, "adcType": 1, "lpAdcCalMode": 0, "gainTableType": 0, "rxDpProfile": { "rxNbDecTop": { "scicBlk23En": 0, "scicBlk23DivFactor": 0, "scicBlk23LowRippleEn": 0, "decBy2Blk35En": 0, "decBy2Blk37En": 0, "decBy2Blk39En": 0, "decBy2Blk41En": 0, "decBy2Blk43En": 0, "decBy3Blk45En": 0, "decBy2Blk47En": 0 }, "rxWbDecTop": { "decBy2Blk25En": 0, "decBy2Blk27En": 0, "decBy2Blk29En": 0, "decBy2Blk31En": 0, "decBy2Blk33En": 0, "wbLpfBlk33p1En": 0 }, "rxDecTop": { "decBy3Blk15En": 0, "decBy2Hb3Blk17p1En": 0, "decBy2Hb4Blk17p2En": 0, "decBy2Hb5Blk19p1En": 0, "decBy2Hb6Blk19p2En": 0 }, "rxSincHBTop": { "sincGainMux": 1, "sincMux": 0, "hbMux": 4, "isGainCompEnabled": 0, "gainComp9GainI": [ 16384, 16384, 16384, 16384, 16384, 16384 ], "gainComp9GainQ": [ 0, 0, 0, 0, 0, 0 ] }, "rxNbDem": { "dpInFifo": { "dpInFifoEn": 0, "dpInFifoMode": 0, "dpInFifoTestDataSel": 0 }, "rxNbNco": { "rxNbNcoEn": 0, "rxNbNcoConfig": { "freq": 0, "sampleFreq": 0, "phase": 0, "realOut": 0 } }, "rxWbNbCompPFir": { "bankSel": 0, "rxWbNbCompPFirInMuxSel": 0, "rxWbNbCompPFirEn": 0 }, "resamp": { "rxResampEn": 0, "resampPhaseI": 0, "resampPhaseQ": 0 }, "gsOutMuxSel": 1, "rxOutSel": 0, "rxRoundMode": 0, "dpArmSel": 0 } }, "lnaConfig": { "externalLnaPresent": false, "gpioSourceSel": 0, "externalLnaPinSel": 0, "settlingDelay": 0, "numberLnaGainSteps": 0, "lnaGainSteps_mdB": [ 0, 0, 0, 0 ], "lnaDigitalGainDelay": 0, "minGainIndex": 0 }, "rxSsiConfig": { "ssiType": 0, "ssiDataFormatSel": 0, "numLaneSel": 0, "strobeType": 0, "lsbFirst": 0, "qFirst": 0, "txRefClockPin": 0, "lvdsIBitInversion": false, "lvdsQBitInversion": false, "lvdsStrobeBitInversion": false, "lvdsUseLsbIn12bitMode": 0, "lvdsRxClkInversionEn": false, "cmosDdrPosClkEn": false, "cmosClkInversionEn": false, "ddrEn": false, "rxMaskStrobeEn": false } } }, { "profile": { "primarySigBandwidth_Hz": 12500, "rxOutputRate_Hz": 0, "rxInterfaceSampleRate_Hz": 0, "rxOffsetLo_kHz": 0, "rxNcoEnable": false, "outputSignaling": 0, "filterOrder": 1, "filterOrderLp": 1, "hpAdcCorner": 0, "lpAdcCorner": 0, "adcClk_kHz": 0, "rxCorner3dB_kHz": 0, "rxCorner3dBLp_kHz": 0, "tiaPower": 2, "tiaPowerLp": 2, "channelType": 0, "adcType": 1, "lpAdcCalMode": 0, "gainTableType": 0, "rxDpProfile": { "rxNbDecTop": { "scicBlk23En": 0, "scicBlk23DivFactor": 0, "scicBlk23LowRippleEn": 0, "decBy2Blk35En": 0, "decBy2Blk37En": 0, "decBy2Blk39En": 0, "decBy2Blk41En": 0, "decBy2Blk43En": 0, "decBy3Blk45En": 0, "decBy2Blk47En": 0 }, "rxWbDecTop": { "decBy2Blk25En": 0, "decBy2Blk27En": 0, "decBy2Blk29En": 0, "decBy2Blk31En": 0, "decBy2Blk33En": 0, "wbLpfBlk33p1En": 0 }, "rxDecTop": { "decBy3Blk15En": 0, "decBy2Hb3Blk17p1En": 0, "decBy2Hb4Blk17p2En": 0, "decBy2Hb5Blk19p1En": 0, "decBy2Hb6Blk19p2En": 0 }, "rxSincHBTop": { "sincGainMux": 1, "sincMux": 0, "hbMux": 4, "isGainCompEnabled": 0, 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"lvdsRxClkInversionEn": false, "cmosDdrPosClkEn": false, "cmosClkInversionEn": false, "ddrEn": false, "rxMaskStrobeEn": false } } } ] }, "tx": { "txInitChannelMask": 12, "txProfile": [ { "primarySigBandwidth_Hz": 20000000, "txInputRate_Hz": 40000000, "txInterfaceSampleRate_Hz": 40000000, "txOffsetLo_kHz": 0, "validDataDelay": 0, "txBbf3dBCorner_kHz": 50000, "outputSignaling": 0, "txPdBiasCurrent": 1, "txPdGainEnable": 0, "txPrePdRealPole_kHz": 1000000, "txPostPdRealPole_kHz": 530000, "txBbfPower": 2, "txExtLoopBackType": 0, "txExtLoopBackForInitCal": 0, "txPeakLoopBackPower": 0, "frequencyDeviation_Hz": 0, "txDpProfile": { "txPreProc": { "txPreProcSymbol0": 0, "txPreProcSymbol1": 0, "txPreProcSymbol2": 0, "txPreProcSymbol3": 0, "txPreProcSymMapDivFactor": 1, "txPreProcMode": 1, "txPreProcWbNbPfirIBankSel": 0, "txPreProcWbNbPfirQBankSel": 1 }, "txWbIntTop": { "txInterpBy2Blk30En": 0, "txInterpBy2Blk28En": 0, "txInterpBy2Blk26En": 0, "txInterpBy2Blk24En": 0, "txInterpBy2Blk22En": 0, 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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8388608, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] } ], "pfirRxMagLowTiaLowSRHp": [ { "numCoeff": 21, "coefficients": [ 3, -116, 500, -633, -520, 1609, 783, -3980, -1975, 11016, 19392, 11016, -1975, -3980, 783, 1609, -520, -633, 500, -116, 3 ] }, { "numCoeff": 21, "coefficients": [ 3, -116, 500, -633, -520, 1609, 783, -3980, -1975, 11016, 19392, 11016, -1975, -3980, 783, 1609, -520, -633, 500, -116, 3 ] } ], "pfirRxMagLowTiaHighSRHp": [ { "numCoeff": 21, "coefficients": [ -710, 40, 1726, 1906, -1470, -5751, -5663, 162, 7493, 12017, 13269, 12017, 7493, 162, -5663, -5751, -1470, 1906, 1726, 40, -710 ] }, { "numCoeff": 21, "coefficients": [ -710, 40, 1726, 1906, -1470, -5751, -5663, 162, 7493, 12017, 13269, 12017, 7493, 162, -5663, -5751, -1470, 1906, 1726, 40, -710 ] } ], "pfirRxMagHighTiaHighSRHp": [ { "numCoeff": 21, "coefficients": [ 4, 23, -176, 631, -1603, 3201, -5306, 7454, -8659, 5616, 30400, 5616, -8659, 7454, -5306, 3201, -1603, 631, -176, 23, 4 ] }, { "numCoeff": 21, "coefficients": [ 4, 23, -176, 631, -1603, 3201, -5306, 7454, -8659, 5616, 30400, 5616, -8659, 7454, -5306, 3201, -1603, 631, -176, 23, 4 ] } ], "pfirRxMagLowTiaLowSRLp": [ { "numCoeff": 21, "coefficients": [ 3, -116, 500, -633, -520, 1609, 783, -3979, -1974, 11016, 19389, 11016, -1974, -3979, 783, 1609, -520, -633, 500, -116, 3 ] }, { "numCoeff": 21, "coefficients": [ 3, -116, 500, -633, -520, 1609, 783, -3979, -1974, 11016, 19389, 11016, -1974, -3979, 783, 1609, -520, -633, 500, -116, 3 ] } ], "pfirRxMagLowTiaHighSRLp": [ { "numCoeff": 21, "coefficients": [ -710, 40, 1724, 1903, -1471, -5747, -5656, 167, 7492, 12010, 13259, 12010, 7492, 167, -5656, -5747, -1471, 1903, 1724, 40, -710 ] }, { "numCoeff": 21, "coefficients": [ -710, 40, 1724, 1903, -1471, -5747, -5656, 167, 7492, 12010, 13259, 12010, 7492, 167, -5656, -5747, -1471, 1903, 1724, 40, -710 ] } ], "pfirRxMagHighTiaHighSRLp": [ { "numCoeff": 21, "coefficients": [ 4, 22, -169, 612, -1558, 3118, -5180, 7306, -8549, 5683, 30195, 5683, -8549, 7306, -5180, 3118, -1558, 612, -169, 22, 4 ] }, { "numCoeff": 21, "coefficients": [ 4, 22, -169, 612, -1558, 3118, -5180, 7306, -8549, 5683, 30195, 5683, -8549, 7306, -5180, 3118, -1558, 612, -169, 22, 4 ] } ], "pfirTxMagComp1": { "numCoeff": 21, "coefficients": [ -4, 117, -588, 1843, -4319, 8109, -12389, 15089, -11070, 292, 38616, 292, -11070, 15089, -12389, 8109, -4319, 1843, -588, 117, -4 ] }, "pfirTxMagComp2": { "numCoeff": 21, "coefficients": [ -4, 117, -588, 1843, -4319, 8109, -12389, 15089, -11070, 292, 38616, 292, -11070, 15089, -12389, 8109, -4319, 1843, -588, 117, -4 ] }, "pfirTxMagCompNb": [ { "numCoeff": 13, "coefficients": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] }, { "numCoeff": 13, "coefficients": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] } ], "pfirRxMagCompNb": [ { "numCoeff": 13, "coefficients": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] }, { "numCoeff": 13, "coefficients": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] } ] } }

Thanks,

Justin

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on Jun 1, 2022 1:33 PM in reply to jreigle
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Hi Justin,

I see you are not using the master branch which most likely explains your issue. The profile you are generating is not compatible with the driver in that branch. Note that branch is way behind master (it was a dev branch; not really something to be used).

For TES 0.20, you need to use the driver in the master branch.

- Nuno Sá
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jreigle on Jun 1, 2022 2:11 PM in reply to ADIApproved
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Thank you, I will try this and report back if we're still experiencing issues.
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jreigle on Jun 2, 2022 4:39 PM in reply to ADIApproved
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Hi Nuno,

I have switched to using the tip of the master branch and am experiencing the same issue with identical error logs. The driver seems to work fine as long as we don't use a FH enabled profile.

Any ideas on what we can try?

Thanks,

Justin
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on Jun 3, 2022 2:42 AM in reply to jreigle
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Hi,

Not really... I'll have to try that profile on my end and see if the issue is reproducible.

- Nuno Sá
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on Jun 7, 2022 10:43 AM in reply to ADIApproved
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Hi,

So I gave your profile a test and I did not experienced your issue. I was able to, sometimes, load the profile. Note that I said sometimes because I did had issues related with interface tuning. Interface tuning is the last thing being done on the device setup.

So, apparently, we do have some issues for this profile but not really the ones you are experiencing... You are having problems even before reaching the tuning phase.

jreigle said:
After this point the driver fails to attach and the device is non-operational. Some investigation has found the failure is occurring somewhere related to the 'adi_adrv9001_cals_InitCals_Run' function call

Looking at the full log, it actually seems the issue is in adrv9002_power_mgmt_config() call and those errors might indicate that there might be some issue on your HW design that only pops up with FH enabled profiles. Could you confirm on your kernel boot log, which api version is being used?

Another thing (should not be related with your issue) is that you should generate a stream file in TES under file->generate stream image and load that before the profile. The process is identical to the profile loading but the IIO attribute name in this case is 'stream_config'.

- Nuno Sá
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jreigle on Jun 7, 2022 8:01 PM in reply to ADIApproved
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Hi Nuno,

Thanks for the details. In the working case, I see the following printouts in the driver initialization:
[ 19.086182] adrv9002 spi0.0: adrv9002-phy Rev 12.0, Firmware 0.240.48.8, Stream 0.7.9.0, API version: 48.49.2 successfully initialized
[ 19.118263] cf_axi_adc ff220000.axi-adrv9002-rx-lpc: ADI AIM (0.00.) at 0xFF220000 mapped to 0x29d3d165, probed ADC ADRV9002 as master

Do those versions look reasonable to you?

Do you have any thoughts on what HW design issues might be the culprit? My understanding is we only are using the reset line and SPI bus for sample data, I do not believe our HW design is aware that FH mode has been enabled.

We are loading the profile via /lib/firmware files, as well as the TES generated stream image. Since you also had issues using the profile I provided, is it possible for you to provide us a known working FH profile and stream image?

Thanks,

Justin
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on Jun 8, 2022 2:43 AM in reply to jreigle
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Hi,

Yes, this is the currently supported version...

jreigle said:
Do you have any thoughts on what HW design issues might be the culprit? My understanding is we only are using the reset line and SPI bus for sample data, I do not believe our HW design is aware that FH mode has been enabled

I'm also not an HW expert so my best guess is that when FH is enabled, there are more blocks/HW enabled/setted up in the chip which may be triggering some issue (maybe in the supply lines?), Saying this because the issue is not triggered with the default profiles...

jreigle said:
We are loading the profile via /lib/firmware files,

I see, I did my test loading the profiles using the IIO sysfs attribute... In theory, should not matter.

jreigle said:
Since you also had issues using the profile I provided, is it possible for you to provide us a known working FH profile and stream image?

As I said, I've had different issues than what you are experiencing but yes, you can try another profile. As I could see from the output rates in your profile, you are generating some custom profile. I would say to just use a typical LTE one with, let's say, 15.36 MSPS.

- Nuno Sá
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jreigle on Jun 8, 2022 7:11 PM in reply to ADIApproved
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Hi Nuno,

We tried using an LTE FH profile and stream image and experienced the exact failure as before. Does this help narrow down the potential problem?

Can you please provide us HDL reference design source code?

Thanks,

Justin
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jreigle on Jun 8, 2022 7:11 PM in reply to ADIApproved
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Hi Nuno,

We tried using an LTE FH profile and stream image and experienced the exact failure as before. Does this help narrow down the potential problem?

Can you please provide us HDL reference design source code?

Thanks,

Justin
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jreigle on Jun 8, 2022 7:17 PM in reply to jreigle
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Small note, we are testing this with a Navassa eval board, but with a different a different FPGA board, so I think the power supply/layout should be something supported.
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on Jun 9, 2022 6:29 AM in reply to jreigle
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Hi,

jreigle said:
We tried using an LTE FH profile and stream image and experienced the exact failure as before. Does this help narrow down the potential problem?

At this point, the issue really looks to be something else rather than the driver since I've tested FH with default LTE profiles...

jreigle said:
Can you please provide us HDL reference design source code?

This is also available under github:

https://github.com/analogdevicesinc/hdl/tree/master/projects/adrv9001

- Nuno Sá
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rmccourt on Jun 14, 2022 5:34 PM in reply to ADIApproved
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Hi Nuno -

Another question on this problem (I'm trying to give Justin a hand on this effort).

We're specifically using an Intel Arria 10 FPGA (not on the Intel SoC eval board, but a similar one) to interact with the ADRV9002 eval board.

We're using the LVDS interface and noted ADI ran into some pinout problems with the default Arria 10 eval board (and Xilinx ZC706 board), so those setups only support the CMOS interface. We saw the same issue, but built a translator board to let us plug in and remap the clocks to the right Arria 10 pins.

I'd suspect that you're running with the ZCU102 eval board as your reference platform. Is there anything you see in the code that might hint at some difference in the driver running on the Arria 10 that could be the issue? Do you have any Arria 10 setups available to check if the frequency hopping behavior is working on that platform?

Thanks -

-Ryan
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on Jun 15, 2022 4:43 AM in reply to rmccourt
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rmccourt said:
I'd suspect that you're running with the ZCU102 eval board as your reference platform

Yes, essential ZCU102 and Zed...

rmccourt said:
Is there anything you see in the code that might hint at some difference in the driver running on the Arria 10 that could be the issue?

Nope, the driver is more or less agnostic to this... The only major thing that it needs to be aware is in here. The divider will be different depending on the platform. And this should not really matter for the logs we are seeing in here... (It could be an issue in a later point when doing interface tuning).

rmccourt said:
Do you have any Arria 10 setups available to check if the frequency hopping behavior is working on that platform?

I personally don't have much experience or ever tested ADRV9002 with that platform. But I will ask a colleague to give this a try.

- Nuno Sá
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ADRV9002 driver hang on FH enable

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