I have a system consisting of three ADRV9009 devices (6 x RX and 6 x TX channels) all clocked by an HMC7044. All three devices interface to a Xilinx MPSOC FPGA. I am using ADI 2019_R2 branch within Petalinux 2019.1. I am building the MPSOC FPGA firmware using Vivado 2019.1.
This is working - I am able to achieve synchronous sampling across all 6 RX channels and I am able to transmit synchronously across all 6 TX channels. This is represented as SYSTEM A in the diagram below:
There is now a requirement to achieve synchronous sampling / synchronous transmission across two of these systems (seen as the addition of SYSTEM B in the diagram above). The combination of the two systems would have 12 x RX and 12 x TX channels.
To achieve synchronous sampling across the two systems, all we have access to is the RFSYNCIN/FIN of the HMC7044s. We also have access to an RFSYNCOUT/FOUT which could be used to daisy-chain from SYSTEM A HMC7044 to SYSTEM B HMC7044.
Within the ADI ADRV9009 JESD204B state machine framework, is it going to be possible to somehow synchronise these two systems?
If it is not possible within the current implementation, what would need to be modified or changed to the two systems to allow synchronous sampling / synchronous transmission across the two systems? In other words, what do we need to change in our implementation so that we can achieve synchronous sampling across two of our systems?
Looking forward to hearing what options are available.