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ADRV9009: Synchronising across separate systems

Category: Hardware
Product Number: ADRV9009
Software Version: 2019_R2

Hello

I have a system consisting of three ADRV9009 devices (6 x RX and 6 x TX channels) all clocked by an HMC7044. All three devices interface to a Xilinx MPSOC FPGA. I am using ADI 2019_R2 branch within Petalinux 2019.1. I am building the MPSOC FPGA firmware using Vivado 2019.1.

This is working - I am able to achieve synchronous sampling across all 6 RX channels and I am able to transmit synchronously across all 6 TX channels. This is represented as SYSTEM A in the diagram below:

There is now a requirement to achieve synchronous sampling / synchronous transmission across two of these systems (seen as the addition of SYSTEM B in the diagram above). The combination of the two systems would have 12 x RX and 12 x TX channels.

To achieve synchronous sampling across the two systems, all we have access to is the RFSYNCIN/FIN of the HMC7044s. We also have access to an RFSYNCOUT/FOUT which could be used to daisy-chain from SYSTEM A HMC7044 to SYSTEM B HMC7044.

Within the ADI ADRV9009 JESD204B state machine framework, is it going to be possible to somehow synchronise these two systems?

If it is not possible within the current implementation, what would need to be modified or changed to the two systems to allow synchronous sampling / synchronous transmission across the two systems? In other words, what do we need to change in our implementation so that we can achieve synchronous sampling across two of our systems?

Looking forward to hearing what options are available.

Thank you

Gavin

  • I have found the following from ADI:
    https://wiki.analog.com/resources/eval/user-guides/adrv9009-zu11eg/syncronization

    However, this scheme requires the use of some primary HMC7044 that provides the SYSCLK and SYSREF to the secondary HMC7044s in a clock tree. I also noticed that this scheme only uses the FIN of the secondary HMC7044s and does not use RFSYNC input. Instead, the primary HMC7044 drives the SYNC inputs of the secondary HMC7044s.

    Would the following be a viable option?

    This would have one primary HMC7044 which is responsible for synchronisation. The secondary HMC7044 would simply be configured in bypass mode. So there would be a phase shift between the 6 channels on the primary system and the 6 channels on the secondary system (introduced by the HMC7044 on the secondary system operating in bypass mode) but this should hopefully be constant between power cycles.

    What do you think? Is this a viable option? Is there device tree and device driver support for operating an HMC7044 in bypass mode?

    I am getting pressure to make this a reality so any input would be greatly appreciated.

  • Hi,

    As noted on the wiki page we support both reference and clock distribution with the drivers and framework. 

    The additional clock chip we use in this clock tree will effectively eliminate this delay. But I think what you're considering should work with some deterministic delay. You may want to check on the: 

     Clock and Timing 

     Forum as well.

    -Michael

  • Hello Michael

    So I have implemented this and have finally been able to test it on hardware. So far the results are looking promising. I can see a fixed offset when the ADRV9009 DAC input starts accepting data between the primary system and the secondary system. As you stated, my daisy chain solution results in a fixed offset because of the delays introduced by the secondary HMC7044. This offset is repeatable between power cycles so that is good.

    I am using the following ADI script to complete the JESD synchronisation process on the two systems:
    iio_jesd204_fsm_sync

    I have discovered that I cannot set the center frequency of the ADRV9009s until after this script (iio_jesd204_fsm_sync) has run. I understand that even though the systems have booted up, they are not 'ready' until after the script has run.

    Now I am wandering about the RF synchronisation. If I only set the center frequency of the primary and secondary ADRV9009s after the script has run, surely the RF outputs go out of phase again because they are being set at different times on the two systems? 

    Is there a way that I can restart the JESD synchronisation after I have configured the primary and secondary ADRV9009 center frequency so that they are RF phase aligned too?

    The procedure would be something like this:

    1) Boot the two systems.

    2) Run the iio_jesd204_fsm_sync script so that the two systems are phase aligned.

    Now I can configure the ADRV9009s so...

    3) Set the RF center frequency of the primary ADRV9009 and the RF center frequency of the secondary ADVR9009.

    4) Restart the synchronsation so that both the JESD and RF are synchronised.

    I hope my question is making sense.

    Thank you.

  • You can set the desired LO frequency using the debug attribute  adi,trx-pll-lo-frequency_hz this is how we do it in our python scripting.

    https://github.com/analogdevicesinc/pyadi-iio/blob/master/adi/adrv9009_zu11eg_multi.py#L367

    This way when the FSM starts it already used the desired LO.

    You can always restart the FSM using the jesd204_fsm_ctrl attribute on the TOP device. For your multi-topology setup you would use the script to ease this.

    -Michael