Looking at the fmcomms8 device tree using direct clocking (https://github.com/analogdevicesinc/linux/blob/master/arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-fmcomms8-jesd204-fsm-using-clockdist.dts) you can see the following comment at the top of the file:
#define REFCLK_DIV 4 /* 983.04 MHz via clkin1 / 4 = 245.76 MHz */ #define DEV_DIG_DELAY 5 /* used to be 15 -> now 5 */
When comparing these to the reference clock device tree values that they are overriding (adi,divider value of 12, adi,coarse-digital-delay of 15), I'm assuming that these new values were specifically chosen to support the 983.04 MHz case indicated in the comments. What I don't fully appreciate is the relationship between the divider and coarse digital delay values in this direct clocking configuration.
We configured a system to achieve 491.52 MHz direct clocking configuration by overriding the adi,divider value to 2 in our own system-user.dtsi file but we did NOT modify the adi,coarse-digital-delay value. Could this have fundamentally misconfigured the hmc7044 part in some way or caused unexpected performance? Should we have also modified adi,coarse-digital-delay? We are attempting to compare system performance differences that we have observed between the 983.04 MHz and 491.52 MHz cases and are trying to eliminate variables.