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How is the reference divider value and sample rate for the ADRV9009 RFPLL chosen?



		

			

									
						ahelak
					
							

			
				
									
											
							 		
		        	            							
			
			    	
			                    
                
				                on May 5, 2022 
				
			
			
		


				
		

		    		    
		    
		    		            		        
Category: Software

    		        		            		    
Product Number:  ADRV9009 

    		        		        		        
Software Version: master as of January 2022

    		    		    	
			
Hi, 

I have two short questions regarding the ADRV9009 RF PLL in the Synthesizer Configuration section of UG1295, as used in the fmcomms8 reference design. 



    

  1. In UG1295 Figure 59 the reference frequency to the RFPLL in that figure runs is a divided down copy of the REF_CLK_IN applied to the chip. Where can one find the divider value that is chosen, to understand what the final reference frequency is going into the PLL?    

      

    1. In the profile wizard, there is a device clock, and device clock divider. Is the device clock divider value from the profile automatically used in the scaling of REF_CLK_IN for all 3 PLLs (RFPLL, AUXPLL, and Digital Clock PLL)? 
      2. 

    2. If the RFPLL does not use the device clock divider value from the profile, is there an IIO attribute, device tree setting, or block of driver code you could point me to that contains this divider value? 
      3. 

    

    2. 

  2. In UG1295 Table 45, there are example REF_CLK and PLL Sample Rate values given. How is the PLL sample rate determined when not using one of the original examples, but rather the reference clock distribution example?

      

    1. Specifically, as an example, a system with a reference clock of 983.04 MHz as in the fmcomms8 zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-fmcomms8-jesd204-fsm-using-clockdist.dts example, but with a divider value of 6 such that the attached profile device clock of 163.84 is in use. 
      2. 

    2. Is the PLL sample rate equal to the device clock divided by the device clock divider value from the profile value, or is it more complicated? 
      3. 

    

    3. 



Thanks, 
Adam 

 




 


 

								


				
				
		

			
						
									
									
						
						
			
			
			
			
		


					

			





	










	

	

					



			


				
	









	
    
	

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                                 Analog Employees 
                                
                            
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                on May 6, 2022 8:39 AM
            
            
					
    
	
    

		
		
    
					
    Hi,
    

    1) As far as I can tell the CLK Scales shown in this block diagram are automatically calculated based on REF_CLK_IN aka. deviceClock_kHz.
    

    Please see here: https://github.com/analogdevicesinc/linux/blob/master/drivers/iio/adc/talise/talise.c#L2622
    

    1a) You can select a value here, but it is not reflected in the profile. It kind of mimics what the driver will do/handle automatically.
    

    1b) There is no such option since the API driver handles it internally.
    

    2) I don't think this is anyhow related. The reference vs. clock distribution in this example talks about the external clock tree and clock chips. What the ADRV9009 is concerned is only the REF_CLK_IN aka. deviceClock_kHz. The frequency provided by this external clock tree must match the value in the devicetree/profile.
    

    If you need more detailed insights into the ADRV9009 internal clocking, I would recommend to raise this here:
    

     Design Support ADRV9008-1/ADRV9008-2/ADRV9009 
    

    -Michael
    

    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
				
						
						
				
				
		
		
    
			
		
    
	
    

    

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													0
							
			
				
									
							        
            
                                    			
			                            
                        
                on May 6, 2022 12:55 PM
            
            
												
						in reply to mhennerich
					
									
    
	
    

		
		
    
					
    Hi Michael, 

    Great, thanks for the link to that portion of talise code. It looks like the driver tries to target 40-80 MHz for the PLL reference frequency, and adjusts dividers based on the device clock frequency in order to achieve it. 

    This would also be consistent with the reference clock and PLL sample rate columns of Table 45. 

    Appreciate the quick response, will reach out on that other forum if we have any additional questions. 

    Thanks, 
    Adam 
    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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