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fsm: sysref alignment error when sending additional sysref pulse

Category: Software
Product Number: adrv9009 - ad9528
Software Version: github-2019_R2 commit 17f4223f

I am using the evaluation board ADRV9009-W_PCBZ, which contains a adrv9009 and a ad9528 pll chip.

In my hdl I use the same sysref pulse provided by the ad9528, to align my own hdl logic. But this pulse is transmitted after the jesd204_fsm_ctrl procedure. Which will produce following alignment error:

If I don't send this sysref pulse, the miss alignment does not occur:

Is there an option that the fsm ignores the sysref pulses?

Thanks for the assistance.

Regards.

  • Hi,

    This sounds odd to me.

    We're also repurposing SYSREF to synchronize some transport layer cores, and we never run into SYSREF alignment issues with that. 

    Since a surplus SYSREF pulse or pulse drain will have exactly the same phase and frequency that previous invocations.

    How do you request this additional SYSREF?

    Do you change anything related to phase and frequency?

    -Michael  

  • writing 0x83 to register 0x403 of the ad9528

    I noticed that if I send 0x87 (4pulses) instead of 0x83 (1pulse),  the alignment error will not occur every time.

    I don't change anything else, just a clean boot. It could be be reproduced verry simply:

    root@some_user:/sys/kernel/debug/iio/iio:device1# echo 1 > /sys/bus/iio/devices/iio:device*/jesd204_fsm_ctrl
    root@some_user:/sys/kernel/debug/iio/iio:device1# grep "" /sys/bus/platform/devices/*jesd*/status
    /sys/bus/platform/devices/84a90000.axi-jesd204-tx/status:Link is enabled
    /sys/bus/platform/devices/84a90000.axi-jesd204-tx/status:Measured Link Clock: 240.025 MHz
    /sys/bus/platform/devices/84a90000.axi-jesd204-tx/status:Reported Link Clock: 240.000 MHz
    /sys/bus/platform/devices/84a90000.axi-jesd204-tx/status:Lane rate: 9600.000 MHz
    /sys/bus/platform/devices/84a90000.axi-jesd204-tx/status:Lane rate / 40: 240.000 MHz
    /sys/bus/platform/devices/84a90000.axi-jesd204-tx/status:LMFC rate: 7.500 MHz
    /sys/bus/platform/devices/84a90000.axi-jesd204-tx/status:SYNC~: deasserted
    /sys/bus/platform/devices/84a90000.axi-jesd204-tx/status:Link status: DATA
    /sys/bus/platform/devices/84a90000.axi-jesd204-tx/status:SYSREF captured: Yes
    /sys/bus/platform/devices/84a90000.axi-jesd204-tx/status:SYSREF alignment error: No
    /sys/bus/platform/devices/84aa0000.axi-jesd204-rx/status:Link is enabled
    /sys/bus/platform/devices/84aa0000.axi-jesd204-rx/status:Measured Link Clock: 240.025 MHz
    /sys/bus/platform/devices/84aa0000.axi-jesd204-rx/status:Reported Link Clock: 240.000 MHz
    /sys/bus/platform/devices/84aa0000.axi-jesd204-rx/status:Lane rate: 9600.000 MHz
    /sys/bus/platform/devices/84aa0000.axi-jesd204-rx/status:Lane rate / 40: 240.000 MHz
    /sys/bus/platform/devices/84aa0000.axi-jesd204-rx/status:LMFC rate: 7.500 MHz
    /sys/bus/platform/devices/84aa0000.axi-jesd204-rx/status:Link status: DATA
    /sys/bus/platform/devices/84aa0000.axi-jesd204-rx/status:SYSREF captured: Yes
    /sys/bus/platform/devices/84aa0000.axi-jesd204-rx/status:SYSREF alignment error: No
    /sys/bus/platform/devices/84ab0000.axi-jesd204-rx-os/status:Link is enabled
    /sys/bus/platform/devices/84ab0000.axi-jesd204-rx-os/status:Measured Link Clock: 240.025 MHz
    /sys/bus/platform/devices/84ab0000.axi-jesd204-rx-os/status:Reported Link Clock: 240.000 MHz
    /sys/bus/platform/devices/84ab0000.axi-jesd204-rx-os/status:Lane rate: 9600.000 MHz
    /sys/bus/platform/devices/84ab0000.axi-jesd204-rx-os/status:Lane rate / 40: 240.000 MHz
    /sys/bus/platform/devices/84ab0000.axi-jesd204-rx-os/status:LMFC rate: 7.500 MHz
    /sys/bus/platform/devices/84ab0000.axi-jesd204-rx-os/status:Link status: DATA
    /sys/bus/platform/devices/84ab0000.axi-jesd204-rx-os/status:SYSREF captured: Yes
    /sys/bus/platform/devices/84ab0000.axi-jesd204-rx-os/status:SYSREF alignment error: No
    root@some_user:/sys/kernel/debug/iio/iio:device1# echo 0x403 0x83 > direct_reg_access
    root@some_user:/sys/kernel/debug/iio/iio:device1# grep "" /sys/bus/platform/devices/*jesd*/status
    /sys/bus/platform/devices/84a90000.axi-jesd204-tx/status:Link is enabled
    /sys/bus/platform/devices/84a90000.axi-jesd204-tx/status:Measured Link Clock: 240.025 MHz
    /sys/bus/platform/devices/84a90000.axi-jesd204-tx/status:Reported Link Clock: 240.000 MHz
    /sys/bus/platform/devices/84a90000.axi-jesd204-tx/status:Lane rate: 9600.000 MHz
    /sys/bus/platform/devices/84a90000.axi-jesd204-tx/status:Lane rate / 40: 240.000 MHz
    /sys/bus/platform/devices/84a90000.axi-jesd204-tx/status:LMFC rate: 7.500 MHz
    /sys/bus/platform/devices/84a90000.axi-jesd204-tx/status:SYNC~: deasserted
    /sys/bus/platform/devices/84a90000.axi-jesd204-tx/status:Link status: DATA
    /sys/bus/platform/devices/84a90000.axi-jesd204-tx/status:SYSREF captured: Yes
    /sys/bus/platform/devices/84a90000.axi-jesd204-tx/status:SYSREF alignment error: Yes
    /sys/bus/platform/devices/84aa0000.axi-jesd204-rx/status:Link is enabled
    /sys/bus/platform/devices/84aa0000.axi-jesd204-rx/status:Measured Link Clock: 240.025 MHz
    /sys/bus/platform/devices/84aa0000.axi-jesd204-rx/status:Reported Link Clock: 240.000 MHz
    /sys/bus/platform/devices/84aa0000.axi-jesd204-rx/status:Lane rate: 9600.000 MHz
    /sys/bus/platform/devices/84aa0000.axi-jesd204-rx/status:Lane rate / 40: 240.000 MHz
    /sys/bus/platform/devices/84aa0000.axi-jesd204-rx/status:LMFC rate: 7.500 MHz
    /sys/bus/platform/devices/84aa0000.axi-jesd204-rx/status:Link status: DATA
    /sys/bus/platform/devices/84aa0000.axi-jesd204-rx/status:SYSREF captured: Yes
    /sys/bus/platform/devices/84aa0000.axi-jesd204-rx/status:SYSREF alignment error: Yes
    /sys/bus/platform/devices/84ab0000.axi-jesd204-rx-os/status:Link is enabled
    /sys/bus/platform/devices/84ab0000.axi-jesd204-rx-os/status:Measured Link Clock: 240.025 MHz
    /sys/bus/platform/devices/84ab0000.axi-jesd204-rx-os/status:Reported Link Clock: 240.000 MHz
    /sys/bus/platform/devices/84ab0000.axi-jesd204-rx-os/status:Lane rate: 9600.000 MHz
    /sys/bus/platform/devices/84ab0000.axi-jesd204-rx-os/status:Lane rate / 40: 240.000 MHz
    /sys/bus/platform/devices/84ab0000.axi-jesd204-rx-os/status:LMFC rate: 7.500 MHz
    /sys/bus/platform/devices/84ab0000.axi-jesd204-rx-os/status:Link status: DATA
    /sys/bus/platform/devices/84ab0000.axi-jesd204-rx-os/status:SYSREF captured: Yes
    /sys/bus/platform/devices/84ab0000.axi-jesd204-rx-os/status:SYSREF alignment error: Yes

  • Can you read 0x403 before you write it?

    What does it say?

    #echo 0x403 > direct_reg_access

    #cat direct_reg_access

    -Michael

  • root@some_user:/sys/kernel/debug/iio/iio:device1# echo 0x403 > direct_reg_access
    root@some_user:/sys/kernel/debug/iio/iio:device1# cat direct_reg_access
    0x86

  • Is it possible that this has got something to do with the sysref rate (k-interval). I have set the k factor in the dtb to 480 (240MHz/480=500 Khz). But when if I boot my board it automaticly sets it to 16 (240MHz/480=15MHz), which is above the allowed sysref rate.

    I found that there are some new recent commits, I am still at "github-2019_R2 commit 17f4223f".  like iio: frequency: ad9528: jesd204-fsm add support for desired SYSREF · analogdevicesinc/linux@c588ee4 · GitHub

    I am not sure if I could simply sherry pick ad9528.c and ad9528.h , are there some dtb changes involved aswell?

  • I have added following lines into my dtb:

    adi,jesd204-desired-sysref-frequency-hz = <500000>;
    adi,jesd204-max-sysref-frequency-hz = <5000000>;

    And I have verified it on my oscilloscope, and it is 500 KHz instead of the 15 MHz.  

    But the miss alignment problem still exist.

  • Hi,

    SYSREF frequency must be a an integer multiple of the LMFC.

    This is what the jesd204-fsm tries to set.

    In some rare cases this might not be possible, but I don't expect this to be the case here.

    However when forcing the rate using adi,jesd204-desired-sysref-frequency-hz with an invalid rate this can become an issue.

    These SYSREF alignment errors can be seen when AC coupling SYSREF and using non-continuous SYSREF. But I guess you're using the FMC eval board where SYSREF is DC coupled?

    -Michael

  • The integer multiply is 15:

    • Sysref rate is 500 KHz
    • LMFC is 7.5 MHz

    I am indeed using the eval board ADRV9009-W_PCBZ, so the sysref is DC coupled.

  • Not sure if this is really necessary, but when the driver quests a SYSREF it follows the register write with an IO_UPDATE reg 0xf=1.

    Can you check if this makes a difference?

    -Michael

  • like this?

    # iio_reg adrv9009-phy 0xf 1