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AD9484 sample question


I'm using an ultrazed-eg setup with a custom ad9484 board connected. I'm using the ad9467 driver and using ad9517 for the clock. We have it setup and verified our clock is at 500Mhz for 500MS/s. I'm getting some interesting discontinuities in my samples. Even with a no signal connected or with a sine wave connected. We have verified that our signal going into the ADC for sampling looks good. This picture is what we are seeing through the IIO scope. We have output of adc setup as binary offset. Not sure if one of our LVDS lines is doing something funny but from our data we see on those lines they seem to be moving as expected. Could this be a clock sync issue in the fpga?

Fixed adc type
[edited by: dv3@2 at 1:39 PM (GMT -4) on 1 Apr 2022]