ADRV9002 + ZCU102 Profile Load

SethK said:

I'm trying to load a profile that I've created in TES (0.20.0), using iio-scope (0.14).
We've gone the Petalinux build route using the 2019_R2 branch on a ZCU102 system.

When loading a profile through iio-scope, i'm getting this error for any json profile i try and load:

The profile loading has changed a bit in the master branch of IIO-Scope. Can you try the latest artifact: iio-oscilloscope 1.0.641 - AppVeyor

SethK said:

I am able to load profiles through sysfs however, but had a couple questions on this.
For the default profile that comes with the meta-adi recipes, it appears that RX1 and TX1 can both be in the ensm 'rf_enabled' state.
We've tested this through iio-scope, and it appears you can transmit and receive at the same time.
When i load a different profile, RX1/TX1 and RX2/TX2 all start in the 'primed' state, and only one of RX or TX of each pair can be enabled at a given time.
(i.e. if you have RX1 in the rf_enabled state, TX1 refuses to also go into the rf_enabled state and vice versa).

If you try and write this state through sysfs (using out_voltage0_ensm_mode for example), you get a write error stating: 'write error: Operation not permitted'.

This is dependent on the profile itself. You can only transmit and receiver with a FDD (not TDD) profile. 

SethK said:

Ultimately we're trying to override the default profile at boot and would like similar system behavior to what the default ADI profile seems to have.

If you want to change the default boot profile you will need to change the profile built against: 

https://github.com/analogdevicesinc/linux/blob/2aa7ac113716f339ecfb57d5a9ea016d47cd7a46/drivers/iio/adc/navassa/adrv9002.c#L4650

Located in the firmware folder: linux/Navassa_CMOS_profile.json at master · analogdevicesinc/linux (github.com)

Otherwise add a profile load to your rc.local or similar init mechanism.

-Travis

Thanks for responding so quick Travis!
It looks like with the newer version of iio-scope, it is still failing to load a profile. Since we're able to do this through other means, its not a show stopper.

travisfcollins said:

This is dependent on the profile itself. You can only transmit and receiver with a FDD (not TDD) profile.

This is good to know- we're trying to get a data sample rate of 51.2MSPS, and this only appears to be achievable through TDD: Configuration #4. For the 'Custom' configuration setup, it looks like the sample rate and its derivatives fall within the dead zones for the PLL's. Is it possible to get a 51.2MSPS data rate with FDD mode?

travisfcollins said:

If you want to change the default boot profile you will need to change the profile built against

Yup, this is the approach we've been taking- we're patching that particular file in the kernel and that mechanism appears to be working.

Thanks again,
~Seth

SethK said:

For the 'Custom' configuration setup, it looks like the sample rate and its derivatives fall within the dead zones for the PLL's. Is it possible to get a 51.2MSPS data rate with FDD mode?

Post this question in the ADRV9001-ADRV9007 support. They might know over there the limitation. They will ask you to post the TES GUI screenshots of what you are trying to do.

-Travis