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Changing the VCXO 80 MHz ad9375

Thread Summary

The user is experiencing issues with the AD9375 JESD204 link when using a VCXO 80 MHz and the r2019_2 branch, encountering errors related to the CLKPLL VCO frequency exceeding the maximum limit with a VCO divider of 1.5. The final answer suggests disabling the TXQEC initialization calibration and ensuring the RX port is terminated with a 50ohm resistor during initialization. The user should also verify the device tree configuration, particularly the VCO divider settings, and ensure no input is present at the RX port during the init cals.
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Hi, I am trying to set up AD9375 to work with VCXO 80 MHz along with zc 706 using branch r2019_2. I generated a profile in the GUI 
with the appropriate settings, after that I made the settings in the device tree, I checked the frequency at the ad9528 output with
an oscilloscope. I noticed that there is a problem with the divisor adi,clocks-clk-pll-vco-div = <>;
in the filter generator <clkPllVcoDiv=1.5>, which corresponds to the value adi,clocks-clk-pll-vco-div = <1>. The following error appeared in the console on startup

ad9371 spi0.1: ad9371_probe : enter
axi_adxcvr 44a60000.axi-adxcvr-rx: AXI-ADXCVR-RX (17.01.a) using CPLL on GTX2 at 0x44A60000. Number of lanes: 2.
axi_adxcvr 44a50000.axi-adxcvr-rx-os: AXI-ADXCVR-RX (17.01.a) using CPLL on GTX2 at 0x44A50000. Number of lanes: 2.
axi_adxcvr 44a80000.axi-adxcvr-tx: AXI-ADXCVR-TX (17.01.a) using QPLL on GTX2 at 0x44A80000. Number of lanes: 4.
asoc-simple-card adv7511_hdmi_snd: spdif-hifi <-> 75c00000.axi-spdif-tx mapping ok
ad9371 spi0.1: ad9371_probe : enter
[drm] Cannot find any crtc or sizes
ERROR: 64: CLKPLL VCO frequency exceeded max(9.216Ghz) in VCO divider /1.5 case ()
ERROR: 64: CLKPLL VCO frequency exceeded max(9.216Ghz) in VCO divider /1.5 case ()
ad9371 spi0.1: CLKPLL VCO frequency exceeded max(9.216Ghz) in VCO divider /1.5 case ()
(64)
ERROR: 64: CLKPLL VCO frequency exceeded max(9.216Ghz) in VCO divider /1.5 case ()
ERROR: 64: CLKPLL VCO frequency exceeded max(9.216Ghz) in VCO divider /1.5 case ()
ad9371 spi0.1: CLKPLL VCO frequency exceeded max(9.216Ghz) in VCO divider /1.5 case ()
(64)
ad9371: probe of spi0.1 failed with error -14
input: gpio_keys as /devices/soc0/gpio_keys/input

there were topics on the forum where they referred to the fact that this divisor should be set
adi,clocks-clk-pll-vco-div = <3>.
but this solution did not work for me
dmesg | grep ad93
[ 2.251641] ad9371 spi0.1: ad9371_probe : enter
[ 2.410360] ad9371 spi0.1: ad9371_probe : enter
[ 2.597441] ad9371 spi0.1: ad9371_probe : enter
[ 6.083987] ad9371 spi0.1: calsDoneLifetime 0x47, calsDoneLastRun 0x47, calsMinimum 0x4F, initErrCal 0x3, initErrCode 0x1
[ 6.153609] ad9371 spi0.1: initCalsCompleted 0x47
[ 6.157223] ad9371 spi0.1: errorWord 0x2, statusWord 0x0
[ 6.161259] ad9371 spi0.1: ArmCmdStatusByte 0xE
[ 6.167995] ad9371 spi0.1: deframerStatus (0x60)
[ 6.178321] ad9371 spi0.1: ILAS mismatch: c7f8
[ 6.181451] ad9371 spi0.1: ILAS lanes per converter did not match
[ 6.186247] ad9371 spi0.1: ILAS scrambling did not match
[ 6.190242] ad9371 spi0.1: ILAS octets per frame did not match
[ 6.194777] ad9371 spi0.1: ILAS frames per multiframe did not match
[ 6.199729] ad9371 spi0.1: ILAS number of converters did not match
[ 6.204610] ad9371 spi0.1: ILAS sample resolution did not match
[ 6.209216] ad9371 spi0.1: ILAS control bits per sample did not match
[ 6.214357] ad9371 spi0.1: ILAS bits per sample did not match
[ 6.218790] ad9371 spi0.1: ILAS checksum did not match
[ 6.230145] ad9371 spi0.1: Device not in radioOff/IDLE state. Error in MYKONOS_enableTrackingCals()
[ 9.613840] ad9371 spi0.1: calsDoneLifetime 0x47, calsDoneLastRun 0x47, calsMinimum 0x4F, initErrCal 0x3, initErrCode 0x1
[ 9.683588] ad9371 spi0.1: initCalsCompleted 0x47
[ 9.687207] ad9371 spi0.1: errorWord 0x2, statusWord 0x0
[ 9.691240] ad9371 spi0.1: ArmCmdStatusByte 0xE
[ 9.697877] ad9371 spi0.1: deframerStatus (0x60)
[ 9.708182] ad9371 spi0.1: ILAS mismatch: c7f8
[ 9.711311] ad9371 spi0.1: ILAS lanes per converter did not match
[ 9.716107] ad9371 spi0.1: ILAS scrambling did not match
[ 9.720103] ad9371 spi0.1: ILAS octets per frame did not match
[ 9.724637] ad9371 spi0.1: ILAS frames per multiframe did not match
[ 9.729590] ad9371 spi0.1: ILAS number of converters did not match
[ 9.734471] ad9371 spi0.1: ILAS sample resolution did not match
[ 9.739077] ad9371 spi0.1: ILAS control bits per sample did not match
[ 9.744218] ad9371 spi0.1: ILAS bits per sample did not match
[ 9.748651] ad9371 spi0.1: ILAS checksum did not match
[ 9.760005] ad9371 spi0.1: Device not in radioOff/IDLE state. Error in MYKONOS_enableTrackingCals()
[ 9.768495] ad9371: probe of spi0.1 failed with error -14


____________________________________________________________________________________________________


what needs to be done to raise the JESD204 with this profile and VCXO 80 MHz, 
I have an idea that I can try to change the number of JESD lines in the HDL project (tx4/rx2/oRx2) to (tx2/rx1/oRx1),
switch from CPLL to QPLL I tried it didn't help...

<profile AD9371 version=0 name=Rx 20, IQrate 40.000>
 <clocks>
  <deviceClock_kHz=80000>
  <clkPllVcoFreq_kHz=9600000>
  <clkPllVcoDiv=1.5>
  <clkPllHsDiv=4>
 </clocks>

 <rx>
  <adcDiv=1>
  <rxFirDecimation=4>
  <rxDec5Decimation=5>
  <enHighRejDec5=1>
  <rhb1Decimation=2>
  <iqRate_kHz=40000>
  <rfBandwidth_Hz=20000000>
  <rxBbf3dBCorner_kHz=20000>

  <filter FIR gain=-6 num=72>
  -1
  -1
  0
  3
  5
  4
  0
  -7
  -9
  -4
  4
  6
  -7
  -28
  -32
  9
  92
  168
  147
  -30
  -324
  -562
  -507
  -17
  781
  1457
  1442
  382
  -1524
  -3406
  -4000
  -2241
  2096
  8083
  13870
  17424
  17424
  13870
  8083
  2096
  -2241
  -4000
  -3406
  -1524
  382
  1442
  1457
  781
  -17
  -507
  -562
  -324
  -30
  147
  168
  92
  9
  -32
  -28
  -7
  6
  4
  -4
  -9
  -7
  0
  4
  5
  3
  0
  -1
  -1
  </filter>

  <adc-profile num=16>
  460
  273
  182
  98
  1280
  112
  1505
  53
  1574
  25
  1069
  40
  48
  48
  31
  184
  </adc-profile>
 </rx>

 <obs>
  <adcDiv=1>
  <rxFirDecimation=2>
  <rxDec5Decimation=5>
  <enHighRejDec5=1>
  <rhb1Decimation=2>
  <iqRate_kHz=80000>
  <rfBandwidth_Hz=60000000>
  <rxBbf3dBCorner_kHz=30000>

  <filter FIR gain=0 num=72>
  0
  1
  -1
  -2
  2
  6
  -4
  -14
  5
  30
  -3
  -56
  -8
  93
  36
  -143
  -92
  202
  189
  -260
  -343
  301
  571
  -300
  -889
  216
  1320
  13
  -1905
  -508
  2731
  1576
  -4111
  -4817
  5434
  17585
  17585
  5434
  -4817
  -4111
  1576
  2731
  -508
  -1905
  13
  1320
  216
  -889
  -300
  571
  301
  -343
  -260
  189
  202
  -92
  -143
  36
  93
  -8
  -56
  -3
  30
  5
  -14
  -4
  6
  2
  -2
  -1
  1
  0
  </filter>

  <adc-profile num=16>
  459
  273
  182
  98
  1280
  115
  1506
  54
  1575
  25
  1069
  40
  48
  48
  31
  184
  </adc-profile>

  <lpbk-adc-profile num=16>
  460
  273
  182
  98
  1280
  112
  1505
  53
  1574
  25
  1069
  40
  48
  48
  31
  184
  </lpbk-adc-profile>
 </obs>

 <sniffer>
  <adcDiv=1>
  <rxFirDecimation=4>
  <rxDec5Decimation=5>
  <enHighRejDec5=1>
  <rhb1Decimation=2>
  <iqRate_kHz=40000>
  <rfBandwidth_Hz=20000000>
  <rxBbf3dBCorner_kHz=20000>

  <filter FIR gain=-6 num=72>
  -1
  -1
  0
  3
  5
  4
  0
  -7
  -9
  -4
  4
  6
  -7
  -28
  -32
  9
  92
  168
  147
  -30
  -324
  -562
  -507
  -17
  781
  1457
  1442
  382
  -1524
  -3406
  -4000
  -2241
  2096
  8083
  13870
  17424
  17424
  13870
  8083
  2096
  -2241
  -4000
  -3406
  -1524
  382
  1442
  1457
  781
  -17
  -507
  -562
  -324
  -30
  147
  168
  92
  9
  -32
  -28
  -7
  6
  4
  -4
  -9
  -7
  0
  4
  5
  3
  0
  -1
  -1
  </filter>

  <adc-profile num=16>
  460
  273
  182
  98
  1280
  112
  1505
  53
  1574
  25
  1069
  40
  48
  48
  31
  184
  </adc-profile>
 </sniffer>

 <tx>
  <dacDiv=2.5>
  <txFirInterpolation=2>
  <thb1Interpolation=2>
  <thb2Interpolation=2>
  <txInputHbInterpolation=1>
  <iqRate_kHz=80000>
  <primarySigBandwidth_Hz=20000000>
  <rfBandwidth_Hz=60000000>
  <txDac3dBCorner_kHz=92000>
  <txBbf3dBCorner_kHz=30000>

  <filter FIR gain=0 num=32>
  -42
  -49
  135
  153
  -313
  -386
  619
  819
  -1108
  -1646
  1799
  3288
  -2375
  -6142
  3518
  18087
  18087
  3518
  -6142
  -2375
  3288
  1799
  -1646
  -1108
  819
  619
  -386
  -313
  153
  135
  -49
  -42
  </filter>
 </tx>
</profile>