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Changing the VCXO 80 MHz ad9375

Hi, I am trying to set up AD9375 to work with VCXO 80 MHz along with zc 706 using branch r2019_2. I generated a profile in the GUI 
with the appropriate settings, after that I made the settings in the device tree, I checked the frequency at the ad9528 output with
an oscilloscope. I noticed that there is a problem with the divisor adi,clocks-clk-pll-vco-div = <>;
in the filter generator <clkPllVcoDiv=1.5>, which corresponds to the value adi,clocks-clk-pll-vco-div = <1>. The following error appeared in the console on startup

ad9371 spi0.1: ad9371_probe : enter
axi_adxcvr 44a60000.axi-adxcvr-rx: AXI-ADXCVR-RX (17.01.a) using CPLL on GTX2 at 0x44A60000. Number of lanes: 2.
axi_adxcvr 44a50000.axi-adxcvr-rx-os: AXI-ADXCVR-RX (17.01.a) using CPLL on GTX2 at 0x44A50000. Number of lanes: 2.
axi_adxcvr 44a80000.axi-adxcvr-tx: AXI-ADXCVR-TX (17.01.a) using QPLL on GTX2 at 0x44A80000. Number of lanes: 4.
asoc-simple-card adv7511_hdmi_snd: spdif-hifi <-> 75c00000.axi-spdif-tx mapping ok
ad9371 spi0.1: ad9371_probe : enter
[drm] Cannot find any crtc or sizes
ERROR: 64: CLKPLL VCO frequency exceeded max(9.216Ghz) in VCO divider /1.5 case ()
ERROR: 64: CLKPLL VCO frequency exceeded max(9.216Ghz) in VCO divider /1.5 case ()
ad9371 spi0.1: CLKPLL VCO frequency exceeded max(9.216Ghz) in VCO divider /1.5 case ()
(64)
ERROR: 64: CLKPLL VCO frequency exceeded max(9.216Ghz) in VCO divider /1.5 case ()
ERROR: 64: CLKPLL VCO frequency exceeded max(9.216Ghz) in VCO divider /1.5 case ()
ad9371 spi0.1: CLKPLL VCO frequency exceeded max(9.216Ghz) in VCO divider /1.5 case ()
(64)
ad9371: probe of spi0.1 failed with error -14
input: gpio_keys as /devices/soc0/gpio_keys/input

there were topics on the forum where they referred to the fact that this divisor should be set
adi,clocks-clk-pll-vco-div = <3>.
but this solution did not work for me
dmesg | grep ad93
[ 2.251641] ad9371 spi0.1: ad9371_probe : enter
[ 2.410360] ad9371 spi0.1: ad9371_probe : enter
[ 2.597441] ad9371 spi0.1: ad9371_probe : enter
[ 6.083987] ad9371 spi0.1: calsDoneLifetime 0x47, calsDoneLastRun 0x47, calsMinimum 0x4F, initErrCal 0x3, initErrCode 0x1
[ 6.153609] ad9371 spi0.1: initCalsCompleted 0x47
[ 6.157223] ad9371 spi0.1: errorWord 0x2, statusWord 0x0
[ 6.161259] ad9371 spi0.1: ArmCmdStatusByte 0xE
[ 6.167995] ad9371 spi0.1: deframerStatus (0x60)
[ 6.178321] ad9371 spi0.1: ILAS mismatch: c7f8
[ 6.181451] ad9371 spi0.1: ILAS lanes per converter did not match
[ 6.186247] ad9371 spi0.1: ILAS scrambling did not match
[ 6.190242] ad9371 spi0.1: ILAS octets per frame did not match
[ 6.194777] ad9371 spi0.1: ILAS frames per multiframe did not match
[ 6.199729] ad9371 spi0.1: ILAS number of converters did not match
[ 6.204610] ad9371 spi0.1: ILAS sample resolution did not match
[ 6.209216] ad9371 spi0.1: ILAS control bits per sample did not match
[ 6.214357] ad9371 spi0.1: ILAS bits per sample did not match
[ 6.218790] ad9371 spi0.1: ILAS checksum did not match
[ 6.230145] ad9371 spi0.1: Device not in radioOff/IDLE state. Error in MYKONOS_enableTrackingCals()
[ 9.613840] ad9371 spi0.1: calsDoneLifetime 0x47, calsDoneLastRun 0x47, calsMinimum 0x4F, initErrCal 0x3, initErrCode 0x1
[ 9.683588] ad9371 spi0.1: initCalsCompleted 0x47
[ 9.687207] ad9371 spi0.1: errorWord 0x2, statusWord 0x0
[ 9.691240] ad9371 spi0.1: ArmCmdStatusByte 0xE
[ 9.697877] ad9371 spi0.1: deframerStatus (0x60)
[ 9.708182] ad9371 spi0.1: ILAS mismatch: c7f8
[ 9.711311] ad9371 spi0.1: ILAS lanes per converter did not match
[ 9.716107] ad9371 spi0.1: ILAS scrambling did not match
[ 9.720103] ad9371 spi0.1: ILAS octets per frame did not match
[ 9.724637] ad9371 spi0.1: ILAS frames per multiframe did not match
[ 9.729590] ad9371 spi0.1: ILAS number of converters did not match
[ 9.734471] ad9371 spi0.1: ILAS sample resolution did not match
[ 9.739077] ad9371 spi0.1: ILAS control bits per sample did not match
[ 9.744218] ad9371 spi0.1: ILAS bits per sample did not match
[ 9.748651] ad9371 spi0.1: ILAS checksum did not match
[ 9.760005] ad9371 spi0.1: Device not in radioOff/IDLE state. Error in MYKONOS_enableTrackingCals()
[ 9.768495] ad9371: probe of spi0.1 failed with error -14


____________________________________________________________________________________________________


what needs to be done to raise the JESD204 with this profile and VCXO 80 MHz, 
I have an idea that I can try to change the number of JESD lines in the HDL project (tx4/rx2/oRx2) to (tx2/rx1/oRx1),
switch from CPLL to QPLL I tried it didn't help...

<profile AD9371 version=0 name=Rx 20, IQrate 40.000>
 <clocks>
  <deviceClock_kHz=80000>
  <clkPllVcoFreq_kHz=9600000>
  <clkPllVcoDiv=1.5>
  <clkPllHsDiv=4>
 </clocks>

 <rx>
  <adcDiv=1>
  <rxFirDecimation=4>
  <rxDec5Decimation=5>
  <enHighRejDec5=1>
  <rhb1Decimation=2>
  <iqRate_kHz=40000>
  <rfBandwidth_Hz=20000000>
  <rxBbf3dBCorner_kHz=20000>

  <filter FIR gain=-6 num=72>
  -1
  -1
  0
  3
  5
  4
  0
  -7
  -9
  -4
  4
  6
  -7
  -28
  -32
  9
  92
  168
  147
  -30
  -324
  -562
  -507
  -17
  781
  1457
  1442
  382
  -1524
  -3406
  -4000
  -2241
  2096
  8083
  13870
  17424
  17424
  13870
  8083
  2096
  -2241
  -4000
  -3406
  -1524
  382
  1442
  1457
  781
  -17
  -507
  -562
  -324
  -30
  147
  168
  92
  9
  -32
  -28
  -7
  6
  4
  -4
  -9
  -7
  0
  4
  5
  3
  0
  -1
  -1
  </filter>

  <adc-profile num=16>
  460
  273
  182
  98
  1280
  112
  1505
  53
  1574
  25
  1069
  40
  48
  48
  31
  184
  </adc-profile>
 </rx>

 <obs>
  <adcDiv=1>
  <rxFirDecimation=2>
  <rxDec5Decimation=5>
  <enHighRejDec5=1>
  <rhb1Decimation=2>
  <iqRate_kHz=80000>
  <rfBandwidth_Hz=60000000>
  <rxBbf3dBCorner_kHz=30000>

  <filter FIR gain=0 num=72>
  0
  1
  -1
  -2
  2
  6
  -4
  -14
  5
  30
  -3
  -56
  -8
  93
  36
  -143
  -92
  202
  189
  -260
  -343
  301
  571
  -300
  -889
  216
  1320
  13
  -1905
  -508
  2731
  1576
  -4111
  -4817
  5434
  17585
  17585
  5434
  -4817
  -4111
  1576
  2731
  -508
  -1905
  13
  1320
  216
  -889
  -300
  571
  301
  -343
  -260
  189
  202
  -92
  -143
  36
  93
  -8
  -56
  -3
  30
  5
  -14
  -4
  6
  2
  -2
  -1
  1
  0
  </filter>

  <adc-profile num=16>
  459
  273
  182
  98
  1280
  115
  1506
  54
  1575
  25
  1069
  40
  48
  48
  31
  184
  </adc-profile>

  <lpbk-adc-profile num=16>
  460
  273
  182
  98
  1280
  112
  1505
  53
  1574
  25
  1069
  40
  48
  48
  31
  184
  </lpbk-adc-profile>
 </obs>

 <sniffer>
  <adcDiv=1>
  <rxFirDecimation=4>
  <rxDec5Decimation=5>
  <enHighRejDec5=1>
  <rhb1Decimation=2>
  <iqRate_kHz=40000>
  <rfBandwidth_Hz=20000000>
  <rxBbf3dBCorner_kHz=20000>

  <filter FIR gain=-6 num=72>
  -1
  -1
  0
  3
  5
  4
  0
  -7
  -9
  -4
  4
  6
  -7
  -28
  -32
  9
  92
  168
  147
  -30
  -324
  -562
  -507
  -17
  781
  1457
  1442
  382
  -1524
  -3406
  -4000
  -2241
  2096
  8083
  13870
  17424
  17424
  13870
  8083
  2096
  -2241
  -4000
  -3406
  -1524
  382
  1442
  1457
  781
  -17
  -507
  -562
  -324
  -30
  147
  168
  92
  9
  -32
  -28
  -7
  6
  4
  -4
  -9
  -7
  0
  4
  5
  3
  0
  -1
  -1
  </filter>

  <adc-profile num=16>
  460
  273
  182
  98
  1280
  112
  1505
  53
  1574
  25
  1069
  40
  48
  48
  31
  184
  </adc-profile>
 </sniffer>

 <tx>
  <dacDiv=2.5>
  <txFirInterpolation=2>
  <thb1Interpolation=2>
  <thb2Interpolation=2>
  <txInputHbInterpolation=1>
  <iqRate_kHz=80000>
  <primarySigBandwidth_Hz=20000000>
  <rfBandwidth_Hz=60000000>
  <txDac3dBCorner_kHz=92000>
  <txBbf3dBCorner_kHz=30000>

  <filter FIR gain=0 num=32>
  -42
  -49
  135
  153
  -313
  -386
  619
  819
  -1108
  -1646
  1799
  3288
  -2375
  -6142
  3518
  18087
  18087
  3518
  -6142
  -2375
  3288
  1799
  -1646
  -1108
  819
  619
  -386
  -313
  153
  135
  -49
  -42
  </filter>
 </tx>
</profile>



Top Replies

  • /dts-v1/;
    
    / {
    	#address-cells = <0x1>;
    	#size-cells = <0x1>;
    	compatible = "xlnx,zynq-7000";
    	interrupt-parent = <0x1>;
    	model = "Xilinx Zynq ZC706";
    
    	cpus {
    		#address-cells = <0x1>;
    		#size-cells = <0x0>;
    
    		cpu@0 {
    			compatible = "arm,cortex-a9";
    			device_type = "cpu";
    			reg = <0x0>;
    			clocks = <0x2 0x3>;
    			clock-latency = <0x3e8>;
    			cpu0-supply = <0x3>;
    			operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;
    		};
    
    		cpu@1 {
    			compatible = "arm,cortex-a9";
    			device_type = "cpu";
    			reg = <0x1>;
    			clocks = <0x2 0x3>;
    		};
    	};
    
    	fpga-full {
    		compatible = "fpga-region";
    		fpga-mgr = <0x4>;
    		#address-cells = <0x1>;
    		#size-cells = <0x1>;
    		ranges;
    	};
    
    	pmu@f8891000 {
    		compatible = "arm,cortex-a9-pmu";
    		interrupts = <0x0 0x5 0x4 0x0 0x6 0x4>;
    		interrupt-parent = <0x1>;
    		reg = <0xf8891000 0x1000 0xf8893000 0x1000>;
    	};
    
    	fixedregulator {
    		compatible = "regulator-fixed";
    		regulator-name = "VCCPINT";
    		regulator-min-microvolt = <0xf4240>;
    		regulator-max-microvolt = <0xf4240>;
    		regulator-boot-on;
    		regulator-always-on;
    		phandle = <0x3>;
    	};
    
    	amba {
    		u-boot,dm-pre-reloc;
    		compatible = "simple-bus";
    		#address-cells = <0x1>;
    		#size-cells = <0x1>;
    		interrupt-parent = <0x1>;
    		ranges;
    
    		adc@f8007100 {
    			compatible = "xlnx,zynq-xadc-1.00.a";
    			reg = <0xf8007100 0x20>;
    			interrupts = <0x0 0x7 0x4>;
    			interrupt-parent = <0x1>;
    			clocks = <0x2 0xc>;
    		};
    
    		can@e0008000 {
    			compatible = "xlnx,zynq-can-1.0";
    			status = "disabled";
    			clocks = <0x2 0x13 0x2 0x24>;
    			clock-names = "can_clk", "pclk";
    			reg = <0xe0008000 0x1000>;
    			interrupts = <0x0 0x1c 0x4>;
    			interrupt-parent = <0x1>;
    			tx-fifo-depth = <0x40>;
    			rx-fifo-depth = <0x40>;
    		};
    
    		can@e0009000 {
    			compatible = "xlnx,zynq-can-1.0";
    			status = "disabled";
    			clocks = <0x2 0x14 0x2 0x25>;
    			clock-names = "can_clk", "pclk";
    			reg = <0xe0009000 0x1000>;
    			interrupts = <0x0 0x33 0x4>;
    			interrupt-parent = <0x1>;
    			tx-fifo-depth = <0x40>;
    			rx-fifo-depth = <0x40>;
    		};
    
    		gpio@e000a000 {
    			compatible = "xlnx,zynq-gpio-1.0";
    			#gpio-cells = <0x2>;
    			clocks = <0x2 0x2a>;
    			gpio-controller;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x14 0x4>;
    			reg = <0xe000a000 0x1000>;
    			phandle = <0x5>;
    		};
    
    		i2c@e0004000 {
    			compatible = "cdns,i2c-r1p10";
    			status = "disabled";
    			clocks = <0x2 0x26>;
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x19 0x4>;
    			reg = <0xe0004000 0x1000>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    		};
    
    		i2c@e0005000 {
    			compatible = "cdns,i2c-r1p10";
    			status = "disabled";
    			clocks = <0x2 0x27>;
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x30 0x4>;
    			reg = <0xe0005000 0x1000>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    		};
    
    		interrupt-controller@f8f01000 {
    			compatible = "arm,cortex-a9-gic";
    			#interrupt-cells = <0x3>;
    			interrupt-controller;
    			reg = <0xf8f01000 0x1000 0xf8f00100 0x100>;
    			phandle = <0x1>;
    		};
    
    		cache-controller@f8f02000 {
    			compatible = "arm,pl310-cache";
    			reg = <0xf8f02000 0x1000>;
    			interrupts = <0x0 0x2 0x4>;
    			arm,data-latency = <0x3 0x2 0x2>;
    			arm,tag-latency = <0x2 0x2 0x2>;
    			cache-unified;
    			cache-level = <0x2>;
    		};
    
    		memory-controller@f8006000 {
    			compatible = "xlnx,zynq-ddrc-a05";
    			reg = <0xf8006000 0x1000>;
    		};
    
    		ocmc@f800c000 {
    			compatible = "xlnx,zynq-ocmc-1.0";
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x3 0x4>;
    			reg = <0xf800c000 0x1000>;
    		};
    
    		serial@e0000000 {
    			compatible = "xlnx,xuartps", "cdns,uart-r1p8";
    			status = "disabled";
    			clocks = <0x2 0x17 0x2 0x28>;
    			clock-names = "uart_clk", "pclk";
    			reg = <0xe0000000 0x1000>;
    			interrupts = <0x0 0x1b 0x4>;
    		};
    
    		serial@e0001000 {
    			compatible = "xlnx,xuartps", "cdns,uart-r1p8";
    			status = "okay";
    			clocks = <0x2 0x18 0x2 0x29>;
    			clock-names = "uart_clk", "pclk";
    			reg = <0xe0001000 0x1000>;
    			interrupts = <0x0 0x32 0x4>;
    		};
    
    		spi@e0006000 {
    			compatible = "xlnx,zynq-spi-r1p6";
    			reg = <0xe0006000 0x1000>;
    			status = "okay";
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x1a 0x4>;
    			clocks = <0x2 0x19 0x2 0x22>;
    			clock-names = "ref_clk", "pclk";
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    
    			ad9528-1@0 {
    				compatible = "adi,ad9528";
    				reg = <0x0>;
    				#address-cells = <0x1>;
    				#size-cells = <0x0>;
    				spi-max-frequency = <0x989680>;
    				clock-output-names = "ad9528-1_out0", "ad9528-1_out1", "ad9528-1_out2", "ad9528-1_out3", "ad9528-1_out4", "ad9528-1_out5", "ad9528-1_out6", "ad9528-1_out7", "ad9528-1_out8", "ad9528-1_out9", "ad9528-1_out10", "ad9528-1_out11", "ad9528-1_out12", "ad9528-1_out13";
    				#clock-cells = <0x1>;
    				adi,vcxo-freq = <80000000>;
    				adi,refa-enable;
    				adi,refa-diff-rcv-enable;
    				adi,refa-r-div = <0x1>;
    				adi,osc-in-cmos-neg-inp-enable;
    				/*
    				//adi,pll1-feedback-div = <0x4>;
    
    				adi,pll1-charge-pump-current-nA = <0x1388>;
    				*/
    				adi,pll2-m1-frequency = <1280000000>;
    				/*
    				adi,pll2-vco-div-m1 = <0x3>;
    				adi,pll2-n2-div = <0xa>;
    				adi,pll2-r1-div = <0x1>;
    				*/
    				adi,pll2-charge-pump-current-nA = <0xc4888>;
    				adi,sysref-src = <0x2>;
    				adi,sysref-pattern-mode = <0x1>;
    				adi,sysref-k-div = <0x200>;
    				adi,sysref-request-enable;
    				adi,sysref-nshot-mode = <0x3>;
    				adi,sysref-request-trigger-mode = <0x0>;
    				adi,rpole2 = <0x0>;
    				adi,rzero = <0x7>;
    				adi,cpole1 = <0x2>;
    				adi,status-mon-pin0-function-select = <0x1>;
    				adi,status-mon-pin1-function-select = <0x7>;
    				reset-gpios = <0x5 0x71 0x0>;
    				phandle = <0x9>;
    
    				channel@13 {
    					reg = <0xd>;
    					adi,extended-name = "DEV_CLK";
    					adi,driver-mode = <0x0>;
    					adi,divider-phase = <0x0>;
    					adi,channel-divider = <16>;
    					adi,signal-source = <0x0>;
    				};
    
    				channel@1 {
    					reg = <0x1>;
    					adi,extended-name = "FMC_CLK";
    					adi,driver-mode = <0x0>;
    					adi,divider-phase = <0x0>;
    					adi,channel-divider = <16>;
    					adi,signal-source = <0x0>;
    				};
    
    				channel@12 {
    					reg = <0xc>;
    					adi,extended-name = "DEV_SYSREF";
    					adi,driver-mode = <0x0>;
    					adi,divider-phase = <0x0>;
    					adi,channel-divider = <16>;
    					adi,signal-source = <0x2>;
    				};
    
    				channel@3 {
    					reg = <0x3>;
    					adi,extended-name = "FMC_SYSREF";
    					adi,driver-mode = <0x0>;
    					adi,divider-phase = <0x0>;
    					adi,channel-divider = <16>;
    					adi,signal-source = <0x2>;
    				};
    			};
    
    			ad9371-phy@1 {
    				compatible = "adi,ad9375";
    				reg = <0x1>;
    				spi-max-frequency = <0x17d7840>;
    				clocks = <0x6 0x7 0x8 0x9 0xd 0x9 0x1 0x9 0xc 0x9 0x3>;
    				clock-names = "jesd_rx_clk", "jesd_tx_clk", "jesd_rx_os_clk", "dev_clk", "fmc_clk", "sysref_dev_clk", "sysref_fmc_clk";
    				clock-output-names = "rx_sampl_clk", "rx_os_sampl_clk", "tx_sampl_clk";
    				#clock-cells = <0x1>;
    				adi,clocks-clk-pll-vco-freq_khz = <9600000>;
    				adi,clocks-device-clock_khz = <80000>;
    				adi,clocks-clk-pll-hs-div = <4>;
    				adi,clocks-clk-pll-vco-div = <1>;
    				adi,jesd204-obs-framer-over-sample = <0x0>;
    
    				adi,rx-profile-adc-div = <1>;
    				adi,rx-profile-rx-fir-decimation = <4>;
    				adi,rx-profile-rx-dec5-decimation = <5>;				
    				adi,rx-profile-en-high-rej-dec5 = <1>;			
    				adi,rx-profile-rhb1-decimation = <2>;
    				adi,rx-profile-iq-rate_khz = <40000>;
    				adi,rx-profile-rf-bandwidth_hz = <20000000>;
    				adi,rx-profile-rx-bbf-3db-corner_khz = <20000>;
    				
    				adi,obs-settings-obs-rx-channels-enable = <3>; /* Disable Sniffer Profile */
    				
    				adi,rx-profile-rx-fir-gain_db = <(-6)>;
    				adi,rx-profile-rx-fir-num-fir-coefs = <72>;
    				adi,rx-profile-rx-fir-coefs = < (-1) (-1) (0) (3) (5) (4) (0) (-7) (-9) (-4) (4) (6) (-7) (-28) (-32) (9) (92) (168) (147) (-30) (-324) (-562) (-507) (-17) (781) (1457) (1442) (382) (-1524) (-3406) (-4000) (-2241) (2096) (8083) (13870) (17424) (17424) (13870) (8083) (2096) (-2241) (-4000) (-3406) (-1524) (382) (1442) (1457) (781) (-17) (-507) (-562) (-324) (-30) (147) (168) (92) (9) (-32) (-28) (-7) (6) (4) (-4) (-9) (-7) (0) (4) (5) (3) (0) (-1) (-1)>;
    				adi,rx-profile-custom-adc-profile = <(460) (273) (182) (98) (1280) (112) (1505) (53) (1574) (25) (1069) (40) (48) (48) (31) (184)>;
    				adi,obs-profile-adc-div = <1>;
    				adi,obs-profile-rx-fir-decimation = <2>;
    				adi,obs-profile-rx-dec5-decimation = <5>;
    				adi,obs-profile-en-high-rej-dec5 = <1>;
    				adi,obs-profile-rhb1-decimation = <2>;				
    				adi,obs-profile-iq-rate_khz = <80000>;
    				adi,obs-profile-rf-bandwidth_hz = <60000000>;
    				adi,obs-profile-rx-bbf-3db-corner_khz = <30000>;
    				
    				
    				adi,obs-profile-rx-fir-gain_db = <0>;
    				adi,obs-profile-rx-fir-num-fir-coefs = <72>;
    				adi,obs-profile-rx-fir-coefs = <(-1) (-1) (0) (3) (5) (4) (0) (-7) (-9) (-4) (4) (6) (-7) (-28) (-32) (9) (92) (168) (147) (-30) (-324) (-562) (-507) (-17) (781) (1457) (1442) (382) (-1524) (-3406) (-4000) (-2241) (2096) (8083) (13870) (17424) (17424) (13870) (8083) (2096) (-2241) (-4000) (-3406) (-1524) (382) (1442) (1457) (781) (-17) (-507) (-562) (-324) (-30) (147) (168) (92) (9) (-32) (-28) (-7) (6) (4) (-4) (-9) (-7) (0) (4) (5) (3) (0) (-1) (-1)>;
    				adi,obs-profile-custom-adc-profile = <(460) (273) (182) (98) (1280) (112) (1505) (53) (1574) (25) (1069) (40) (48) (48) (31) (184)>;
    				adi,obs-settings-custom-loopback-adc-profile = <(460) (273) (182) (98) (1280) (112) (1505) (53) (1574) (25) (1069) (40) (48) (48) (31) (184)>;
    				
    				adi,tx-profile-dac-div = <1>;
    				
    				adi,tx-profile-tx-fir-interpolation = <2>;
    				adi,tx-profile-thb1-interpolation = <2>;
    				adi,tx-profile-thb2-interpolation = <2>;
    				adi,tx-profile-tx-input-hb-interpolation = <1>;	
    				adi,tx-profile-iq-rate_khz = <80000>;	
    				adi,tx-profile-primary-sig-bandwidth_hz = <20000000>;	
    				adi,tx-profile-rf-bandwidth_hz = <60000000>;	
    				adi,tx-profile-tx-dac-3db-corner_khz = <92000>;				
    				adi,tx-profile-tx-bbf-3db-corner_khz = <30000>;
    	
    				
    				adi,tx-profile-tx-fir-gain_db = <0>;
    				adi,tx-profile-tx-fir-num-fir-coefs = <32>;
    				adi,tx-profile-tx-fir-coefs = <(-42) (-49) (135) (153) (-313) (-386) (619) (819) (-1108) (-1646) (1799) (3288) (-2375) (-6142) (3518) (18087) (18087) (3518) (-6142) (-2375) (3288) (1799) (-1646) (-1108) (819) (619) (-386) (-313) (153) (135) (-49) (-42)>;
    
    				adi,sniffer-profile-adc-div = <1>;
    				adi,sniffer-profile-en-high-rej-dec5 = <1>;
    				adi,sniffer-profile-iq-rate_khz = <40000>;
    				adi,sniffer-profile-rf-bandwidth_hz = <20000000>;
    				adi,sniffer-profile-rhb1-decimation = <2>;
    				adi,sniffer-profile-rx-bbf-3db-corner_khz = <20000>;
    				adi,sniffer-profile-rx-dec5-decimation = <5>;
    				adi,sniffer-profile-rx-fir-decimation = <4>;		
    				/*adi,sniffer-profile-custom-adc-profile
    				adi,sniffer-profile-rx-fir*/
    				
    				reset-gpios = <0x5 0x6a 0x0>;
    				test-gpios = <0x5 0x6b 0x0>;
    				sysref_req-gpios = <0x5 0x70 0x0>;
    				rx2_enable-gpios = <0x5 0x6c 0x0>;
    				rx1_enable-gpios = <0x5 0x6d 0x0>;
    				tx2_enable-gpios = <0x5 0x6e 0x0>;
    				tx1_enable-gpios = <0x5 0x6f 0x0>;
    				adi,dpd-damping = <0x5>;
    				adi,dpd-num-weights = <0x1>;
    				adi,dpd-model-version = <0x2>;
    				adi,dpd-high-power-model-update = <0x1>;
    				adi,dpd-model-prior-weight = <0x14>;
    				adi,dpd-robust-modeling = <0x0>;
    				adi,dpd-samples = <0x200>;
    				adi,dpd-outlier-threshold = <0x1000>;
    				adi,dpd-additional-delay-offset = <0x0>;
    				adi,dpd-path-delay-pn-seq-level = <0xff>;
    				adi,dpd-weights0-real = <0x40>;
    				adi,dpd-weights0-imag = <0x0>;
    				adi,dpd-weights1-real = <0x0>;
    				adi,dpd-weights1-imag = <0x0>;
    				adi,dpd-weights2-real = <0x0>;
    				adi,dpd-weights2-imag = <0x0>;
    				adi,clgc-tx1-desired-gain = <0xfffff830>;
    				adi,clgc-tx2-desired-gain = <0xfffff830>;
    				adi,clgc-tx1-atten-limit = <0x0>;
    				adi,clgc-tx2-atten-limit = <0x0>;
    				adi,clgc-tx1-control-ratio = <0x4b>;
    				adi,clgc-tx2-control-ratio = <0x4b>;
    				adi,clgc-allow-tx1-atten-updates = <0x1>;
    				adi,clgc-allow-tx2-atten-updates = <0x1>;
    				adi,clgc-additional-delay-offset = <0x0>;
    				adi,clgc-path-delay-pn-seq-level = <0xff>;
    				adi,clgc-tx1-rel-threshold = <0x258>;
    				adi,clgc-tx2-rel-threshold = <0x258>;
    				adi,clgc-tx1-rel-threshold-en = <0x0>;
    				adi,clgc-tx2-rel-threshold-en = <0x0>;
    				adi,vswr-additional-delay-offset = <0x0>;
    				adi,vswr-path-delay-pn-seq-level = <0xff>;
    				adi,vswr-tx1-vswr-switch-gpio3p3-pin = <0x0>;
    				adi,vswr-tx2-vswr-switch-gpio3p3-pin = <0x1>;
    				adi,vswr-tx1-vswr-switch-polarity = <0x0>;
    				adi,vswr-tx2-vswr-switch-polarity = <0x0>;
    				adi,vswr-tx1-vswr-switch-delay_us = <0x32>;
    				adi,vswr-tx2-vswr-switch-delay_us = <0x32>;
    				phandle = <0x13>;
    			};
    		};
    
    		spi@e0007000 {
    			compatible = "xlnx,zynq-spi-r1p6";
    			reg = <0xe0007000 0x1000>;
    			status = "disabled";
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x31 0x4>;
    			clocks = <0x2 0x1a 0x2 0x23>;
    			clock-names = "ref_clk", "pclk";
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    		};
    
    		spi@e000d000 {
    			clock-names = "ref_clk", "pclk";
    			clocks = <0x2 0xa 0x2 0x2b>;
    			compatible = "xlnx,zynq-qspi-1.0";
    			status = "okay";
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x13 0x4>;
    			reg = <0xe000d000 0x1000>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			is-dual = <0x1>;
    			num-cs = <0x1>;
    
    			ps7-qspi@0 {
    				#address-cells = <0x1>;
    				#size-cells = <0x1>;
    				spi-tx-bus-width = <0x1>;
    				spi-rx-bus-width = <0x4>;
    				compatible = "n25q128a11";
    				reg = <0x0>;
    				spi-max-frequency = <0x2faf080>;
    
    				partition@0 {
    					label = "boot";
    					reg = <0x0 0x500000>;
    				};
    
    				partition@500000 {
    					label = "bootenv";
    					reg = <0x500000 0x20000>;
    				};
    
    				partition@520000 {
    					label = "config";
    					reg = <0x520000 0x20000>;
    				};
    
    				partition@540000 {
    					label = "image";
    					reg = <0x540000 0xa80000>;
    				};
    
    				partition@fc0000 {
    					label = "spare";
    					reg = <0xfc0000 0x0>;
    				};
    			};
    		};
    
    		memory-controller@e000e000 {
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			status = "disabled";
    			clock-names = "memclk", "apb_pclk";
    			clocks = <0x2 0xb 0x2 0x2c>;
    			compatible = "arm,pl353-smc-r2p1", "arm,primecell";
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x12 0x4>;
    			ranges;
    			reg = <0xe000e000 0x1000>;
    
    			flash@e1000000 {
    				status = "disabled";
    				compatible = "arm,pl353-nand-r2p1";
    				reg = <0xe1000000 0x1000000>;
    				#address-cells = <0x1>;
    				#size-cells = <0x1>;
    			};
    
    			flash@e2000000 {
    				status = "disabled";
    				compatible = "cfi-flash";
    				reg = <0xe2000000 0x2000000>;
    				#address-cells = <0x1>;
    				#size-cells = <0x1>;
    			};
    		};
    
    		ethernet@e000b000 {
    			compatible = "cdns,zynq-gem", "cdns,gem";
    			reg = <0xe000b000 0x1000>;
    			status = "okay";
    			interrupts = <0x0 0x16 0x4>;
    			clocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>;
    			clock-names = "pclk", "hclk", "tx_clk";
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			phy-handle = <0xa>;
    			phy-mode = "rgmii-id";
    
    			phy@7 {
    				device_type = "ethernet-phy";
    				reg = <0x7>;
    				phandle = <0xa>;
    			};
    		};
    
    		ethernet@e000c000 {
    			compatible = "cdns,zynq-gem", "cdns,gem";
    			reg = <0xe000c000 0x1000>;
    			status = "disabled";
    			interrupts = <0x0 0x2d 0x4>;
    			clocks = <0x2 0x1f 0x2 0x1f 0x2 0xe>;
    			clock-names = "pclk", "hclk", "tx_clk";
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    		};
    
    		mmc@e0100000 {
    			compatible = "arasan,sdhci-8.9a";
    			status = "okay";
    			clock-names = "clk_xin", "clk_ahb";
    			clocks = <0x2 0x15 0x2 0x20>;
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x18 0x4>;
    			reg = <0xe0100000 0x1000>;
    		};
    
    		mmc@e0101000 {
    			compatible = "arasan,sdhci-8.9a";
    			status = "disabled";
    			clock-names = "clk_xin", "clk_ahb";
    			clocks = <0x2 0x16 0x2 0x21>;
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x2f 0x4>;
    			reg = <0xe0101000 0x1000>;
    		};
    
    		slcr@f8000000 {
    			u-boot,dm-pre-reloc;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
    			reg = <0xf8000000 0x1000>;
    			ranges;
    			phandle = <0xb>;
    
    			clkc@100 {
    				u-boot,dm-pre-reloc;
    				#clock-cells = <0x1>;
    				compatible = "xlnx,ps7-clkc";
    				fclk-enable = <0xf>;
    				clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb";
    				reg = <0x100 0x100>;
    				ps-clk-frequency = <0x1fca055>;
    				phandle = <0x2>;
    			};
    
    			rstc@200 {
    				compatible = "xlnx,zynq-reset";
    				reg = <0x200 0x48>;
    				#reset-cells = <0x1>;
    				syscon = <0xb>;
    			};
    
    			pinctrl@700 {
    				compatible = "xlnx,pinctrl-zynq";
    				reg = <0x700 0x200>;
    				syscon = <0xb>;
    			};
    		};
    
    		dmac@f8003000 {
    			compatible = "arm,pl330", "arm,primecell";
    			reg = <0xf8003000 0x1000>;
    			interrupt-parent = <0x1>;
    			interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7";
    			interrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>;
    			#dma-cells = <0x1>;
    			#dma-channels = <0x8>;
    			#dma-requests = <0x4>;
    			clocks = <0x2 0x1b>;
    			clock-names = "apb_pclk";
    			phandle = <0x10>;
    		};
    
    		devcfg@f8007000 {
    			compatible = "xlnx,zynq-devcfg-1.0";
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x8 0x4>;
    			reg = <0xf8007000 0x100>;
    			clocks = <0x2 0xc 0x2 0xf 0x2 0x10 0x2 0x11 0x2 0x12>;
    			clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
    			syscon = <0xb>;
    			phandle = <0x4>;
    		};
    
    		efuse@f800d000 {
    			compatible = "xlnx,zynq-efuse";
    			reg = <0xf800d000 0x20>;
    		};
    
    		timer@f8f00200 {
    			compatible = "arm,cortex-a9-global-timer";
    			reg = <0xf8f00200 0x20>;
    			interrupts = <0x1 0xb 0x301>;
    			interrupt-parent = <0x1>;
    			clocks = <0x2 0x4>;
    		};
    
    		timer@f8001000 {
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>;
    			compatible = "cdns,ttc";
    			clocks = <0x2 0x6>;
    			reg = <0xf8001000 0x1000>;
    		};
    
    		timer@f8002000 {
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>;
    			compatible = "cdns,ttc";
    			clocks = <0x2 0x6>;
    			reg = <0xf8002000 0x1000>;
    		};
    
    		timer@f8f00600 {
    			interrupt-parent = <0x1>;
    			interrupts = <0x1 0xd 0x301>;
    			compatible = "arm,cortex-a9-twd-timer";
    			reg = <0xf8f00600 0x20>;
    			clocks = <0x2 0x4>;
    		};
    
    		usb@e0002000 {
    			compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
    			status = "okay";
    			clocks = <0x2 0x1c>;
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x15 0x4>;
    			reg = <0xe0002000 0x1000>;
    			phy_type = "ulpi";
    			dr_mode = "host";
    			xlnx,phy-reset-gpio = <0x5 0x7 0x0>;
    		};
    
    		usb@e0003000 {
    			compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
    			status = "disabled";
    			clocks = <0x2 0x1d>;
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x2c 0x4>;
    			reg = <0xe0003000 0x1000>;
    			phy_type = "ulpi";
    		};
    
    		watchdog@f8005000 {
    			clocks = <0x2 0x2d>;
    			compatible = "cdns,wdt-r1p2";
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x9 0x1>;
    			reg = <0xf8005000 0x1000>;
    			timeout-sec = <0xa>;
    		};
    	};
    
    	aliases {
    		ethernet0 = "/amba/ethernet@e000b000";
    		serial0 = "/amba/serial@e0001000";
    	};
    
    	memory {
    		device_type = "memory";
    		reg = <0x0 0x40000000>;
    	};
    
    	chosen {
    		bootargs = "console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait";
    		stdout-path = "/amba@0/uart@E0001000";
    	};
    
    	leds {
    		compatible = "gpio-leds";
    
    		ds8 {
    			label = "ds12:green";
    			gpios = <0x5 0x3d 0x0>;
    		};
    
    		ds9 {
    			label = "ds15:green";
    			gpios = <0x5 0x3e 0x0>;
    		};
    
    		ds10 {
    			label = "ds16:green";
    			gpios = <0x5 0x3f 0x0>;
    		};
    
    		ds35 {
    			label = "ds17:green";
    			gpios = <0x5 0x40 0x0>;
    		};
    	};
    
    	gpio_keys {
    		compatible = "gpio-keys";
    		#address-cells = <0x1>;
    		#size-cells = <0x0>;
    		autorepeat;
    
    		sw7 {
    			label = "Left";
    			linux,code = <0x69>;
    			gpios = <0x5 0x3a 0x0>;
    		};
    
    		sw8 {
    			label = "Right";
    			linux,code = <0x6a>;
    			gpios = <0x5 0x3c 0x0>;
    		};
    
    		sw9 {
    			label = "Select";
    			linux,code = <0x1c>;
    			gpios = <0x5 0x3b 0x0>;
    		};
    	};
    
    	fpga-axi@0 {
    		compatible = "simple-bus";
    		#address-cells = <0x1>;
    		#size-cells = <0x1>;
    		ranges;
    
    		i2c@41600000 {
    			compatible = "xlnx,axi-iic-1.02.a", "xlnx,xps-iic-2.00.a";
    			reg = <0x41600000 0x10000>;
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x3a 0x4>;
    			clocks = <0x2 0xf>;
    			clock-names = "pclk";
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    
    			i2cswitch@74 {
    				compatible = "nxp,pca9548";
    				#address-cells = <0x1>;
    				#size-cells = <0x0>;
    				reg = <0x74>;
    
    				i2c@0 {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					reg = <0x0>;
    
    					osc@5d {
    						compatible = "si570";
    						temperature-stability = <0x32>;
    						reg = <0x5d>;
    						factory-fout = <0x9502f90>;
    						initial-fout = <0x8d9ee20>;
    					};
    				};
    
    				i2c@1 {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					reg = <0x1>;
    
    					adv7511 {
    						compatible = "adi,adv7511";
    						reg = <0x39 0x3f>;
    						reg-names = "primary", "edid";
    						adi,input-depth = <0x8>;
    						adi,input-colorspace = "rgb";
    						adi,input-clock = "1x";
    						adi,clock-delay = <0x0>;
    						#sound-dai-cells = <0x0>;
    						phandle = <0x1d>;
    
    						ports {
    							#address-cells = <0x1>;
    							#size-cells = <0x0>;
    
    							port@0 {
    								reg = <0x0>;
    
    								endpoint {
    									remote-endpoint = <0xc>;
    									phandle = <0xf>;
    								};
    							};
    
    							port@1 {
    								reg = <0x1>;
    							};
    						};
    					};
    				};
    
    				i2c@2 {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					reg = <0x2>;
    
    					eeprom@54 {
    						compatible = "at,24c08";
    						reg = <0x54>;
    					};
    				};
    
    				i2c@3 {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					reg = <0x3>;
    
    					gpio@21 {
    						compatible = "ti,tca6416";
    						reg = <0x21>;
    						gpio-controller;
    						#gpio-cells = <0x2>;
    					};
    				};
    
    				i2c@4 {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					reg = <0x4>;
    
    					rtc@51 {
    						compatible = "nxp,pcf8563";
    						reg = <0x51>;
    					};
    				};
    
    				i2c@5 {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					reg = <0x5>;
    
    					eeprom@50 {
    						compatible = "at24,24c02";
    						reg = <0x50>;
    					};
    
    					eeprom@54 {
    						compatible = "at24,24c02";
    						reg = <0x54>;
    					};
    
    					ad7291@2f {
    						compatible = "adi,ad7291";
    						reg = <0x2f>;
    					};
    				};
    			};
    		};
    
    		dma@43000000 {
    			compatible = "adi,axi-dmac-1.00.a";
    			reg = <0x43000000 0x10000>;
    			#dma-cells = <0x1>;
    			interrupts = <0x0 0x3b 0x4>;
    			clocks = <0x2 0x10>;
    			phandle = <0xd>;
    
    			adi,channels {
    				#size-cells = <0x0>;
    				#address-cells = <0x1>;
    
    				dma-channel@0 {
    					reg = <0x0>;
    					adi,source-bus-width = <0x40>;
    					adi,source-bus-type = <0x0>;
    					adi,destination-bus-width = <0x40>;
    					adi,destination-bus-type = <0x1>;
    				};
    			};
    		};
    
    		axi-clkgen@79000000 {
    			compatible = "adi,axi-clkgen-2.00.a";
    			reg = <0x79000000 0x10000>;
    			#clock-cells = <0x0>;
    			clocks = <0x2 0xf 0x2 0x10>;
    			clock-names = "s_axi_aclk", "clkin1";
    			phandle = <0xe>;
    		};
    
    		axi_hdmi@70e00000 {
    			compatible = "adi,axi-hdmi-tx-1.00.a";
    			reg = <0x70e00000 0x10000>;
    			dmas = <0xd 0x0>;
    			dma-names = "video";
    			clocks = <0xe>;
    			adi,is-rgb;
    
    			port {
    
    				endpoint {
    					remote-endpoint = <0xf>;
    					phandle = <0xc>;
    				};
    			};
    		};
    
    		axi-spdif-tx@75c00000 {
    			compatible = "adi,axi-spdif-tx-1.00.a";
    			reg = <0x75c00000 0x1000>;
    			dmas = <0x10 0x0>;
    			dma-names = "tx";
    			clocks = <0x2 0xf 0x11>;
    			clock-names = "axi", "ref";
    			#sound-dai-cells = <0x0>;
    			phandle = <0x1c>;
    		};
    
    		axi-sysid-0@45000000 {
    			compatible = "adi,axi-sysid-1.00.a";
    			reg = <0x45000000 0x10000>;
    		};
    
    		rx-dmac@7c400000 {
    			compatible = "adi,axi-dmac-1.00.a";
    			reg = <0x7c400000 0x10000>;
    			#dma-cells = <0x1>;
    			interrupts = <0x0 0x39 0x4>;
    			clocks = <0x2 0x10>;
    			phandle = <0x12>;
    
    			adi,channels {
    				#size-cells = <0x0>;
    				#address-cells = <0x1>;
    
    				dma-channel@0 {
    					reg = <0x0>;
    					adi,source-bus-width = <0x40>;
    					adi,source-bus-type = <0x2>;
    					adi,destination-bus-width = <0x40>;
    					adi,destination-bus-type = <0x0>;
    				};
    			};
    		};
    
    		rx-obs-dmac@7c440000 {
    			compatible = "adi,axi-dmac-1.00.a";
    			reg = <0x7c440000 0x10000>;
    			#dma-cells = <0x1>;
    			interrupts = <0x0 0x37 0x4>;
    			clocks = <0x2 0x10>;
    			phandle = <0x14>;
    
    			adi,channels {
    				#size-cells = <0x0>;
    				#address-cells = <0x1>;
    
    				dma-channel@0 {
    					reg = <0x0>;
    					adi,source-bus-width = <0x40>;
    					adi,source-bus-type = <0x2>;
    					adi,destination-bus-width = <0x40>;
    					adi,destination-bus-type = <0x0>;
    				};
    			};
    		};
    
    		tx-dmac@7c420000 {
    			compatible = "adi,axi-dmac-1.00.a";
    			reg = <0x7c420000 0x10000>;
    			#dma-cells = <0x1>;
    			interrupts = <0x0 0x38 0x4>;
    			clocks = <0x2 0x10>;
    			phandle = <0x15>;
    
    			adi,channels {
    				#size-cells = <0x0>;
    				#address-cells = <0x1>;
    
    				dma-channel@0 {
    					reg = <0x0>;
    					adi,source-bus-width = <0x40>;
    					adi,source-bus-type = <0x0>;
    					adi,destination-bus-width = <0x80>;
    					adi,destination-bus-type = <0x1>;
    				};
    			};
    		};
    
    		axi-ad9371-rx-hpc@44a00000 {
    			compatible = "adi,axi-ad9371-rx-1.0";
    			reg = <0x44a00000 0x8000>;
    			dmas = <0x12 0x0>;
    			dma-names = "rx";
    			spibus-connected = <0x13>;
    			adi,axi-decimation-core-available;
    			decimation-gpios = <0x5 0x73 0x0>;
    		};
    
    		axi-ad9371-rx-obs-hpc@44a08000 {
    			compatible = "adi,axi-ad9371-obs-1.0";
    			reg = <0x44a08000 0x1000>;
    			dmas = <0x14 0x0>;
    			dma-names = "rx";
    			clocks = <0x13 0x1>;
    			clock-names = "sampl_clk";
    		};
    
    		axi-ad9371-tx-hpc@44a04000 {
    			compatible = "adi,axi-ad9371-tx-1.0";
    			reg = <0x44a04000 0x4000>;
    			dmas = <0x15 0x0>;
    			dma-names = "tx";
    			clocks = <0x13 0x2>;
    			clock-names = "sampl_clk";
    			spibus-connected = <0x13>;
    			adi,axi-pl-fifo-enable;
    			adi,axi-interpolation-core-available;
    			interpolation-gpios = <0x5 0x74 0x0>;
    			plddrbypass-gpios = <0x5 0x72 0x0>;
    		};
    
    		axi-jesd204-rx@44aa0000 {
    			compatible = "adi,axi-jesd204-rx-1.0";
    			reg = <0x44aa0000 0x1000>;
    			interrupts = <0x0 0x36 0x4>;
    			clocks = <0x2 0x10 0x16 0x17 0x0>;
    			clock-names = "s_axi_aclk", "device_clk", "lane_clk";
    			#clock-cells = <0x0>;
    			clock-output-names = "jesd_rx_lane_clk";
    			adi,octets-per-frame = <0x4>;
    			adi,frames-per-multiframe = <0x20>;
    			phandle = <0x6>;
    		};
    
    		axi-jesd204-tx@44a90000 {
    			compatible = "adi,axi-jesd204-tx-1.0";
    			reg = <0x44a90000 0x1000>;
    			interrupts = <0x0 0x35 0x4>;
    			clocks = <0x2 0x10 0x18 0x19 0x0>;
    			clock-names = "s_axi_aclk", "device_clk", "lane_clk";
    			#clock-cells = <0x0>;
    			clock-output-names = "jesd_tx_lane_clk";
    			adi,octets-per-frame = <0x2>;
    			adi,frames-per-multiframe = <0x20>;
    			adi,converter-resolution = <0xe>;
    			adi,bits-per-sample = <0x10>;
    			adi,converters-per-device = <0x4>;
    			adi,control-bits-per-sample = <0x2>;
    			phandle = <0x7>;
    		};
    
    		axi-jesd204-rx@44ab0000 {
    			compatible = "adi,axi-jesd204-rx-1.0";
    			reg = <0x44ab0000 0x1000>;
    			interrupts = <0x0 0x34 0x4>;
    			clocks = <0x2 0x10 0x1a 0x1b 0x0>;
    			clock-names = "s_axi_aclk", "device_clk", "lane_clk";
    			#clock-cells = <0x0>;
    			clock-output-names = "jesd_rx_os_lane_clk";
    			adi,octets-per-frame = <0x2>;
    			adi,frames-per-multiframe = <0x20>;
    			phandle = <0x8>;
    		};
    
    		axi-clkgen@43c00000 {
    			compatible = "adi,axi-clkgen-2.00.a";
    			reg = <0x43c00000 0x10000>;
    			#clock-cells = <0x0>;
    			clocks = <0x2 0xf 0x9 0x1>;
    			clock-names = "s_axi_aclk", "clkin1";
    			clock-output-names = "axi_tx_clkgen";
    			phandle = <0x18>;
    		};
    
    		axi-clkgen@43c10000 {
    			compatible = "adi,axi-clkgen-2.00.a";
    			reg = <0x43c10000 0x10000>;
    			#clock-cells = <0x0>;
    			clocks = <0x2 0xf 0x9 0x1>;
    			clock-names = "s_axi_aclk", "clkin1";
    			clock-output-names = "axi_rx_clkgen";
    			phandle = <0x16>;
    		};
    
    		axi-clkgen@43c20000 {
    			compatible = "adi,axi-clkgen-2.00.a";
    			reg = <0x43c20000 0x10000>;
    			#clock-cells = <0x0>;
    			clocks = <0x2 0xf 0x9 0x1>;
    			clock-names = "s_axi_aclk", "clkin1";
    			clock-output-names = "axi_rx_os_clkgen";
    			phandle = <0x1a>;
    		};
    
    		axi-adxcvr-rx@44a60000 {
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			compatible = "adi,axi-adxcvr-1.0";
    			reg = <0x44a60000 0x1000>;
    			clocks = <0x9 0x1 0x16 0x0>;
    			clock-names = "conv", "div40";
    			#clock-cells = <0x1>;
    			clock-output-names = "rx_gt_clk", "rx_out_clk";
    			adi,sys-clk-select = <0x0>;
    			adi,out-clk-select = <0x3>;
    			adi,use-lpm-enable;
    			adi,use-cpll-enable;/**/
    			phandle = <0x17>;
    		};
    
    		axi-adxcvr-rx-os@44a50000 {
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			compatible = "adi,axi-adxcvr-1.0";
    			reg = <0x44a50000 0x1000>;
    			clocks = <0x9 0x1 0x1a>;
    			clock-names = "conv", "div40";
    			#clock-cells = <0x1>;
    			clock-output-names = "rx_os_gt_clk", "rx_os_out_clk";
    			adi,sys-clk-select = <0x0>;
    			adi,out-clk-select = <0x3>;
    			adi,use-lpm-enable;
    			phandle = <0x1b>;
    		};
    
    		axi-adxcvr-tx@44a80000 {
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			compatible = "adi,axi-adxcvr-1.0";
    			reg = <0x44a80000 0x1000>;
    			clocks = <0x9 0x1 0x18>;
    			clock-names = "conv", "div40";
    			#clock-cells = <0x1>;
    			clock-output-names = "tx_gt_clk", "tx_out_clk";
    			adi,sys-clk-select = <0x3>;
    			adi,out-clk-select = <0x3>;
    			/*adi,use-lpm-enable;*/			
    			phandle = <0x19>;
    		};
    	};
    
    	audio_clock {
    		compatible = "fixed-clock";
    		#clock-cells = <0x0>;
    		clock-frequency = <0xbb8000>;
    		phandle = <0x11>;
    	};
    
    	adv7511_hdmi_snd {
    		compatible = "simple-audio-card";
    		simple-audio-card,name = "HDMI monitor";
    		simple-audio-card,widgets = "Speaker", "Speaker";
    		simple-audio-card,routing = "Speaker", "TX";
    
    		simple-audio-card,dai-link@0 {
    			format = "spdif";
    
    			cpu {
    				sound-dai = <0x1c>;
    				frame-master;
    				bitclock-master;
    			};
    
    			codec {
    				sound-dai = <0x1d>;
    			};
    		};
    	};
    };
    

  • Can you disable TXQEC init cal and then check if you are able to pass the initialization? There is a bug with this profile, and you need to disable this cal to run the initialization successfully.

    Also make sure that there is no input going into the RX port while running the init cals. Terminate the RX port with a 50ohm and then run the initialization.

  • Can TXQEC initialization be disabled via the device tree or can it only be done by modifying the mykonos source code?
  • in ad9371.c 

    initCalMask = phy->init_cal_mask |= TX_BB_FILTER | ADC_TUNER | TIA_3DB_CORNER | DC_OFFSET |
    TX_ATTENUATION_DELAY | RX_GAIN_DELAY | FLASH_CAL |
    PATH_DELAY | LOOPBACK_RX_LO_DELAY | LOOPBACK_RX_RX_QEC_INIT |
    RX_LO_DELAY; 

    I don't see that the TX_QEC calibration flag is set
  • in ug-992 Rev. B | Page 73 i see TX_QEC_INIT it turns out it is disabled by default in git repo r2019_2?

    uint32_t initCalMask = TX_BB_FILTER | ADC_TUNER | TIA_3DB_CORNER | DC_OFFSET | TX_ATTENUATION_DELAY | RX_GAIN_DELAY | FLASH_CAL | PATH_DELAY | TX_LO_LEAKAGE_INTERNAL | TX_QEC_INIT | LOOPBACK_RX_LO_DELAY | LOOPBACK_RX_RX_QEC_INIT | RX_LO_DELAY | RX_QEC_INIT; 

  • Moving to Linux forum for comments on this