1.In AD9172 we are having trouble to generate tone of frequency 78.125MHz with DAC sampling rate as 1.25GHz and Lane rate as 3.125gbps in JESD Mode 0, Could you guide as how to configure the which register values.
Is NCO of Channelpath and Datapath is needed for tone generation and What data has to be provided in transport layer samples (like Sine wave data). we are using ad_ip_jesd204_tpl_dac_core for giving the dds input for the DAC.
while simulating we are seeing a sine wave of frequency 10MHz, which is given to the DAC SERDES input but we are not getting any analog output from the DAC channel.
2.We are working on Analog devices RF DAC AD-9172 which is connected to the Zynq-7000 series (XC7Z030ffg676) and it is configured through SPI interface, the input clock for the CLK_IN pin of DAC is
1.250 GHz. while reading the register 0x0C3 which is the DLL status register , we are getting value as "0x01" , so that the DLL is getting locked. but while reading the register 0x281 which is the SERDES PLL status register,
we are getting the value as 0x03 but the actual output should be 0x01, since the the 0th bit of the register is getting high the SERDES PLL is also getting locked.
3.We tried to configure it in both JESD Mode 0 and Mode 8 in Subclass-0 variant , and the internal PLL is disabled for the DAC, we are getting the above mentioned outputs for these configurations.
We are using Xilinx JESD-204B IP core which is sending K-characters after the SERDES PLL is locked and the SYNC_OUT pin of the DAC is going High.
Regards,
Saravanakumar.
