Dual Master AD9361 on the same board

We have created a board with 2 AD9361 and have it working with the normal slave/master like the FMCOMMS5.  Now we want to operate the system with 2 master AD9361s.  We have added the DMAs to the FPGA build and updated the dts file but the driver still loads the second AD9361 as a slave.  Below is the relevent parts of the dts file, am I missing something.  We are using 4.19 Linux driver.

Thanks

Toby

fragment@4 {
target = <&fpga_axi>;
__overlay__ {
interrupt-parent = <&gic>;
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges = <0 0 0 0xffffffff>;

rx_dma: dma@9c400000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x9c400000 0x10000>;
#dma-cells = <1>;
#clock-cells = <0>;
interrupts = <0 109 4>;
clocks = <&zynqmp_clk 71>;

adi,channels {
#size-cells = <0>;
#address-cells = <1>;

dma-channel@0 {
reg = <0>;
adi,source-bus-width = <64>;
adi,source-bus-type = <2>;
adi,destination-bus-width = <64>;
adi,destination-bus-type = <0>;
};
};
};
rx_dma1: dma@9c600000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x9c600000 0x10000>;
#dma-cells = <1>;
#clock-cells = <0>;
interrupts = <0 109 4>;
clocks = <&zynqmp_clk 71>;

adi,channels {
#size-cells = <0>;
#address-cells = <1>;

dma-channel@0 {
reg = <0>;
adi,source-bus-width = <64>;
adi,source-bus-type = <2>;
adi,destination-bus-width = <64>;
adi,destination-bus-type = <0>;
};
};
};

tx_dma: dma@9c420000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x9c420000 0x10000>;
#dma-cells = <1>;
#clock-cells = <0>;
interrupts = <0 108 4>;
clocks = <&zynqmp_clk 71>;

adi,channels {
#size-cells = <0>;
#address-cells = <1>;

dma-channel@0 {
reg = <0>;
adi,source-bus-width = <64>;
adi,source-bus-type = <0>;
adi,destination-bus-width = <64>;
adi,destination-bus-type = <2>;
};
};
};
tx_dma1: dma@9c620000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x9c620000 0x10000>;
#dma-cells = <1>;
#clock-cells = <0>;
interrupts = <0 108 4>;
clocks = <&zynqmp_clk 71>;

adi,channels {
#size-cells = <0>;
#address-cells = <1>;

dma-channel@0 {
reg = <0>;
adi,source-bus-width = <64>;
adi,source-bus-type = <0>;
adi,destination-bus-width = <64>;
adi,destination-bus-type = <2>;
};
};
};
/* Master HDL cores with DMA */
cf_ad9361_adc_core_0: cf-ad9361-A@99020000 {
compatible = "adi,axi-ad9361-6.00.a";
reg = <0x99020000 0x6000>;
dmas = <&rx_dma 0>;
dma-names = "rx";
spibus-connected = <&adc0_ad9361>;
};

cf_ad9361_dac_core_0: cf-ad9361-dds-core-A@99024000 {
compatible = "adi,axi-ad9361-dds-6.00.a";
reg = <0x99024000 0x1000>;
clocks = <&adc0_ad9361 13>;
clock-names = "sampl_clk";
dmas = <&tx_dma 0>;
dma-names = "tx";
};
/* Master 2 HDL cores */
cf_ad9361_adc_core1_0: cf-ad9361-B@99040000 {
compatible = "adi,axi-ad9361-6.00.a";
reg = <0x99040000 0x6000>;
dmas = <&rx_dma1 0>;
dma-names = "rx";
spibus-connected = <&adc1_ad9361>;
};

cf_ad9361_dac_core1_0: cf-ad9361-dds-core-B@99044000 {
compatible = "adi,axi-ad9361-dds-6.00.a";
reg = <0x99044000 0x1000>;
clocks = <&adc1_ad9361 13>;
clock-names = "sampl_clk";
dmas = <&tx_dma1 0>;
dma-names = "tx";
};

//Initialize first AD9361

adc0_ad9361: ad9361-phy-A@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi,ad9361";

.........

//Initialize second AD9361

adc1_ad9361: ad9361-phy-B@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi,ad9361";