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ad9375 + zc706

good afternoon, I use the standard configuration zc 706 adrv 9375 with a 122.88 MHz generator, first I load the GUI analog devices AD9371 / AD9375 Evaluation Software with GUI for Evaluation Board through it I load the new (filter designer) profile generated by me and check that everything works jesd works there are no errors, after that I take and transfer this profile to the Linux device tree compiled for analog devices 2019_1 or 2019_2, for some reason, when loading Linux on the jesd interface, errors appear with the profile checked in Evaluation Software with GUI?

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Booting Linux on physical CPU 0x0
Linux version 4.19.0 (mars@mars-pc) (gcc version 5.5.0 (Linaro GCC 5.5-2017.10)) #1 SMP PREEMPT Wed Dec 22 15:14:36 MSK 2021
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
OF: fdt: Machine model: Xilinx Zynq ZC706
OF: fdt: earlycon: stdout-path /amba@0/uart@E0001000 not found
Memory policy: Data cache writealloc
cma: Reserved 128 MiB at 0x38000000
random: get_random_bytes called from start_kernel+0xa0/0x404 with crng_init=0
percpu: Embedded 16 pages/cpu @(ptrval) s33600 r8192 d23744 u65536
Built 1 zonelists, mobility grouping on. Total pages: 260608
Kernel command line: console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlycon rootfstype=ext4 rootwait cpuidle.off=1
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 889444K/1048576K available (9216K kernel code, 759K rwdata, 6764K rodata, 1024K init, 169K bss, 28060K reserved, 131072K cma-reserved, 131072K highmem)
Virtual kernel memory layout:
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
fixmap : 0xffc00000 - 0xfff00000 (3072 kB)
vmalloc : 0xf0800000 - 0xff800000 ( 240 MB)
lowmem : 0xc0000000 - 0xf0000000 ( 768 MB)
pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
.text : 0x(ptrval) - 0x(ptrval) (10208 kB)
.init : 0x(ptrval) - 0x(ptrval) (1024 kB)
.data : 0x(ptrval) - 0x(ptrval) ( 760 kB)
.bss : 0x(ptrval) - 0x(ptrval) ( 170 kB)
rcu: Preemptible hierarchical RCU implementation.
rcu: RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
Tasks RCU enabled.
rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
efuse mapped to (ptrval)
slcr mapped to (ptrval)
L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 ID prefetch enabled, offset 1 lines
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 512 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
zynq_clock_init: clkc starts at (ptrval)
Zynq clock init
sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 4398046511103ns
clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4ce07af025, max_idle_ns: 440795209040 ns
Switching to timer-based delay loop, resolution 3ns
clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 537538477 ns
timer #0 at (ptrval), irq=17
Console: colour dummy device 80x30
Calibrating delay loop (skipped), value calculated using timer frequency.. 666.66 BogoMIPS (lpj=3333333)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
CPU: Testing write buffer coherency: ok
CPU0: Spectre v2: using BPIALL workaround
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x100000 - 0x100060
rcu: Hierarchical SRCU implementation.
smp: Bringing up secondary CPUs ...
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
CPU1: Spectre v2: using BPIALL workaround
smp: Brought up 1 node, 2 CPUs
SMP: Total of 2 processors activated (1333.33 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
futex hash table entries: 512 (order: 3, 32768 bytes)
pinctrl core: initialized pinctrl subsystem
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0x(ptrval)
zynq-pinctrl 700.pinctrl: zynq pinctrl initialized
e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 25, base_baud = 3125000) is a xuartps
console [ttyPS0] enabled
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
media: Linux media interface: v0.10
videodev: Linux video capture interface: v2.00
jesd204: found 0 devices and 0 topologies
FPGA manager framework
Advanced Linux Sound Architecture Driver Initialized.
clocksource: Switched to clocksource arm_global_timer
NET: Registered protocol family 2
tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes)
TCP established hash table entries: 8192 (order: 3, 32768 bytes)
TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
UDP hash table entries: 512 (order: 2, 16384 bytes)
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
NET: Registered protocol family 1
hw perfevents: no interrupt-affinity property for /pmu@f8891000, guessing.
hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
workingset: timestamp_bits=30 max_order=18 bucket_order=0
bounce: pool size: 64 pages
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
io scheduler mq-deadline registered
io scheduler kyber registered
dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-241330
dma-pl330 f8003000.dmac: DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
brd: module loaded
loop: module loaded
Registered mathworks_ip class
m25p80 spi1.0: found s25fl128s, expected n25q128a11
m25p80 spi1.0: s25fl128s (32768 Kbytes)
5 fixed-partitions partitions found on MTD device spi1.0
Creating 5 MTD partitions on "spi1.0":
0x000000000000-0x000000500000 : "boot"
0x000000500000-0x000000520000 : "bootenv"
0x000000520000-0x000000540000 : "config"
0x000000540000-0x000000fc0000 : "image"
0x000000fc0000-0x000002000000 : "spare"
MACsec IEEE 802.1AE
libphy: Fixed MDIO Bus: probed
tun: Universal TUN/TAP device driver, 1.6
libphy: MACB_mii_bus: probed
Marvell 88E1116R e000b000.ethernet-ffffffff:07: attached PHY driver [Marvell 88E1116R] (mii_bus:phy_addr=e000b000.ethernet-ffffffff:07, irq=POLL)
macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 28 (00:0a:35:00:01:22)
usbcore: registered new interface driver asix
usbcore: registered new interface driver ax88179_178a
usbcore: registered new interface driver cdc_ether
usbcore: registered new interface driver net1080
usbcore: registered new interface driver cdc_subset
usbcore: registered new interface driver zaurus
usbcore: registered new interface driver cdc_ncm
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
usbcore: registered new interface driver uas
usbcore: registered new interface driver usb-storage
usbcore: registered new interface driver usbserial_generic
usbserial: USB Serial support registered for generic
usbcore: registered new interface driver ftdi_sio
usbserial: USB Serial support registered for FTDI USB Serial Device
usbcore: registered new interface driver upd78f0730
usbserial: USB Serial support registered for upd78f0730
chipidea-usb2 e0002000.usb: e0002000.usb supply vbus not found, using dummy regulator
chipidea-usb2 e0002000.usb: Linked as a consumer to regulator.0
ULPI transceiver vendor/product ID 0x0424/0x0007
Found SMSC USB3320 ULPI transceiver.
ULPI integrity check: passed.
ci_hdrc ci_hdrc.0: EHCI Host Controller
ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1
ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00
usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 4.19
usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb1: Product: EHCI Host Controller
usb usb1: Manufacturer: Linux 4.19.0 ehci_hcd
usb usb1: SerialNumber: ci_hdrc.0
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
i2c /dev entries driver
si570 1-005d: registered, current frequency 156250000 Hz
i2c i2c-0: Added multiplexed i2c bus 1
adv7511 2-0039: 2-0039 supply avdd not found, using dummy regulator
adv7511 2-0039: Linked as a consumer to regulator.0
adv7511 2-0039: 2-0039 supply dvdd not found, using dummy regulator
adv7511 2-0039: 2-0039 supply pvdd not found, using dummy regulator
adv7511 2-0039: 2-0039 supply bgvdd not found, using dummy regulator
adv7511 2-0039: 2-0039 supply dvdd-3v not found, using dummy regulator
i2c i2c-0: Added multiplexed i2c bus 2
at24 3-0054: 1024 byte 24c08 EEPROM, writable, 1 bytes/write
i2c i2c-0: Added multiplexed i2c bus 3
pca953x 4-0021: 4-0021 supply vcc not found, using dummy regulator
pca953x 4-0021: Linked as a consumer to regulator.0
i2c i2c-0: Added multiplexed i2c bus 4
rtc-pcf8563 5-0051: rtc core: registered rtc-pcf8563 as rtc0
i2c i2c-0: Added multiplexed i2c bus 5
at24 6-0050: 256 byte 24c02 EEPROM, writable, 1 bytes/write
i2c i2c-0: Added multiplexed i2c bus 6
i2c i2c-0: Added multiplexed i2c bus 7
i2c i2c-0: Added multiplexed i2c bus 8
pca954x 0-0074: registered 8 multiplexed busses for I2C switch pca9548
usbcore: registered new interface driver uvcvideo
USB Video Class driver (1.1.1)
gspca_main: v2.14.0 registered
cdns-wdt f8005000.watchdog: Xilinx Watchdog Timer with timeout 10s
Xilinx Zynq CpuIdle Driver started
failed to register cpuidle driver
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
sdhci-pltfm: SDHCI platform and OF driver helper
mmc0: SDHCI controller on e0100000.mmc [e0100000.mmc] using ADMA
ledtrig-cpu: registered to indicate activity on CPUs
hidraw: raw HID events driver (C) Jiri Kosina
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
ad9371 spi0.1: ad9371_probe : enter
ad9528 spi0.0: spi0.0 supply vcc not found, using dummy regulator
ad9528 spi0.0: Linked as a consumer to regulator.0
mmc0: new high speed SDHC card at address 59b4
mmcblk0: mmc0:59b4 USDU1 29.4 GiB
mmcblk0: p1 p2 p3
random: fast init done
axi_sysid 45000000.axi-sysid-0: [adrv9371x] [sys rom custom string placeholder] on [zc706] git <3608381fb28040c2ae24010fb6345d5790a08175> clean [2022-01-13 08:11:00] UTC
fpga_manager fpga0: Xilinx Zynq FPGA Manager registered
usbcore: registered new interface driver snd-usb-audio
NET: Registered protocol family 10
Segment Routing with IPv6
sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
NET: Registered protocol family 17
NET: Registered protocol family 36
Registering SWP/SWPB emulation handler
Console: switching to colour frame buffer device 240x67
axi-hdmi 70e00000.axi_hdmi: fb0: DRM emulated frame buffer device
[drm] Initialized axi_hdmi_drm 1.0.0 20120930 for 70e00000.axi_hdmi on minor 0
ad9371 spi0.1: ad9371_probe : enter
axi_adxcvr 44a60000.axi-adxcvr-rx: AXI-ADXCVR-RX (17.01.a) using CPLL on GTX2 at 0x44A60000. Number of lanes: 2.
axi_adxcvr 44a50000.axi-adxcvr-rx-os: AXI-ADXCVR-RX (17.01.a) using CPLL on GTX2 at 0x44A50000. Number of lanes: 2.
axi_adxcvr 44a80000.axi-adxcvr-tx: AXI-ADXCVR-TX (17.01.a) using QPLL on GTX2 at 0x44A80000. Number of lanes: 4.
asoc-simple-card adv7511_hdmi_snd: spdif-hifi <-> 75c00000.axi-spdif-tx mapping ok
ad9371 spi0.1: ad9371_probe : enter
ad9371 spi0.1: deframerStatus (0x61)
WARNING: 136: Mismatch detected in MYKONOS_jesd204bIlasCheck()
ad9371 spi0.1: ILAS mismatch: c7f8
ad9371 spi0.1: ILAS lanes per converter did not match
ad9371 spi0.1: ILAS scrambling did not match
ad9371 spi0.1: ILAS octets per frame did not match
ad9371 spi0.1: ILAS frames per multiframe did not match
ad9371 spi0.1: ILAS number of converters did not match
ad9371 spi0.1: ILAS sample resolution did not match
ad9371 spi0.1: ILAS control bits per sample did not match
ad9371 spi0.1: ILAS bits per sample did not match
ad9371 spi0.1: ILAS checksum did not match
ad9371 spi0.1: AD9375 Rev 4, Firmware 5.2.2 API version: 1.5.2.3566 successfully initialized
cf_axi_dds 44a04000.axi-ad9371-tx-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x44A04000 mapped to 0x(ptrval), probed DDS AD9371
cf_axi_adc 44a00000.axi-ad9371-rx-hpc: ADI AIM (10.01.b) at 0x44A00000 mapped to 0x(ptrval), probed ADC AD9371 as MASTER
input: gpio_keys as /devices/soc0/gpio_keys/input/input0
rtc-pcf8563 5-0051: setting system clock to 2022-02-04 14:10:49 UTC (1643983849)
ALSA device list:
#0: HDMI monitor
EXT4-fs (mmcblk0p2): recovery complete
EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
VFS: Mounted root (ext4 filesystem) on device 179:2.
devtmpfs: mounted
Freeing unused kernel memory: 1024K
Run /sbin/init as init process
Mount failed for selinuxfs on /sys/fs/selinux: No such file or directory
random: init: uninitialized urandom read (12 bytes read)
random: mountall: uninitialized urandom read (12 bytes read)
axi-jesd204-rx 44ab0000.axi-jesd204-rx: Lane 0 desynced (131 errors), restarting link
axi-jesd204-rx 44ab0000.axi-jesd204-rx: Lane 1 desynced (126 errors), restarting link
jesd204: (NULL jesd204 device *): Device isn't a top-device, nor does it belong to topology with top-device
axi-jesd204-rx 44ab0000.axi-jesd204-rx: Lane 0 desynced (83175585 errors), restarting link
axi-jesd204-rx 44ab0000.axi-jesd204-rx: Lane 1 desynced (83507753 errors), restarting link
systemd-udevd[1395]: could not open moddep file '/lib/modules/4.19.0/modules.dep.bin'
* Setting up X socket directories... [ OK ]
axi-jesd204-rx 44ab0000.axi-jesd204-rx: Lane 0 desynced (163438350 errors), restarting link
* STARTDISTCC is set to false in /etc/default/distcc
* /usr/bin/distccd not starting
* Starting IIO Daemon iiod [ OK ]
axi-jesd204-rx 44ab0000.axi-jesd204-rx: Lane 0 desynced (45316907 errors), restarting link

Last login: Fri Feb 4 13:43:56 UTC 2022 on tty1
Welcome to Linaro 14.04 (GNU/Linux 4.19.0 armv7l)

axi-jesd204-rx 44ab0000.axi-jesd204-rx: Lane 0 desynced (79361395 errors), restarting link
root@analog:~# axi-jesd204-rx 44ab0000.axi-jesd204-rx: Lane 0 desynced (77929381 errors), restarting link
axi-jesd204-rx 44ab0000.axi-jesd204-rx: Lane 1 desynced (41340859 errors), restarting link

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▒▒(DEVICES) Found 3 JESD204 Link Layer peripherals▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒Ŀ▒
▒▒ ▒▒
▒▒(0): 44ab0000.axi-jesd204-rx ▒▒
▒▒(1): 44a90000.axi-jesd204-tx ▒▒
▒▒(2): 44aa0000.axi-jesd204-rx ▒▒
▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒ٳ
▒▒(STATUS)▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒(0)▒▒▒▒▒▒▒▒(1)▒▒▒▒▒▒▒▒▒▒(2)▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒Ŀ▒
▒▒Link is enabled enabled enabled ▒▒
▒▒Link Status DATA ILAS DATA ▒▒
▒▒Measured Link Clock 61.443 61.443 30.721 ▒▒
▒▒Reported Link Clock 61.440 61.440 30.720 ▒▒
▒▒Lane rate 2457.600 2457.600 1228.800 ▒▒
▒▒Lane rate / 40 61.440 61.440 30.720 ▒▒
▒▒LMFC rate 3.840 3.840 0.960 ▒▒
▒▒SYSREF captured Yes Yes Yes ▒▒
▒▒SYSREF alignment error No No No ▒▒
▒▒SYNC~ deasserted ▒▒
▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒
▒▒(LANE STATUS)▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒(2)▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒Ŀ▒
▒▒Lane# 0 1 ▒▒
▒▒Errors 1 0 ▒▒
▒▒Latency (Multiframes/Octets) 1/60 1/59 ▒▒
▒▒CGS State DATA DATA

-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Parents
  • Can you provide the profile you are loading and your device tree? Which Linux branch are you using 2019_R2 or 2019_R1?

    -Travis

  • Sorry, I have to post from another account. I use 2019_R1
    /dts-v1/;
    
    / {
    	#address-cells = <0x1>;
    	#size-cells = <0x1>;
    	compatible = "xlnx,zynq-7000";
    	interrupt-parent = <0x1>;
    	model = "Xilinx Zynq ZC706";
    
    	cpus {
    		#address-cells = <0x1>;
    		#size-cells = <0x0>;
    
    		cpu@0 {
    			compatible = "arm,cortex-a9";
    			device_type = "cpu";
    			reg = <0x0>;
    			clocks = <0x2 0x3>;
    			clock-latency = <0x3e8>;
    			cpu0-supply = <0x3>;
    			operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;
    		};
    
    		cpu@1 {
    			compatible = "arm,cortex-a9";
    			device_type = "cpu";
    			reg = <0x1>;
    			clocks = <0x2 0x3>;
    		};
    	};
    
    	fpga-full {
    		compatible = "fpga-region";
    		fpga-mgr = <0x4>;
    		#address-cells = <0x1>;
    		#size-cells = <0x1>;
    		ranges;
    	};
    
    	pmu@f8891000 {
    		compatible = "arm,cortex-a9-pmu";
    		interrupts = <0x0 0x5 0x4 0x0 0x6 0x4>;
    		interrupt-parent = <0x1>;
    		reg = <0xf8891000 0x1000 0xf8893000 0x1000>;
    	};
    
    	fixedregulator {
    		compatible = "regulator-fixed";
    		regulator-name = "VCCPINT";
    		regulator-min-microvolt = <0xf4240>;
    		regulator-max-microvolt = <0xf4240>;
    		regulator-boot-on;
    		regulator-always-on;
    		linux,phandle = <0x3>;
    		phandle = <0x3>;
    	};
    
    	amba {
    		u-boot,dm-pre-reloc;
    		compatible = "simple-bus";
    		#address-cells = <0x1>;
    		#size-cells = <0x1>;
    		interrupt-parent = <0x1>;
    		ranges;
    
    		adc@f8007100 {
    			compatible = "xlnx,zynq-xadc-1.00.a";
    			reg = <0xf8007100 0x20>;
    			interrupts = <0x0 0x7 0x4>;
    			interrupt-parent = <0x1>;
    			clocks = <0x2 0xc>;
    		};
    
    		can@e0008000 {
    			compatible = "xlnx,zynq-can-1.0";
    			status = "disabled";
    			clocks = <0x2 0x13 0x2 0x24>;
    			clock-names = "can_clk", "pclk";
    			reg = <0xe0008000 0x1000>;
    			interrupts = <0x0 0x1c 0x4>;
    			interrupt-parent = <0x1>;
    			tx-fifo-depth = <0x40>;
    			rx-fifo-depth = <0x40>;
    		};
    
    		can@e0009000 {
    			compatible = "xlnx,zynq-can-1.0";
    			status = "disabled";
    			clocks = <0x2 0x14 0x2 0x25>;
    			clock-names = "can_clk", "pclk";
    			reg = <0xe0009000 0x1000>;
    			interrupts = <0x0 0x33 0x4>;
    			interrupt-parent = <0x1>;
    			tx-fifo-depth = <0x40>;
    			rx-fifo-depth = <0x40>;
    		};
    
    		gpio@e000a000 {
    			compatible = "xlnx,zynq-gpio-1.0";
    			#gpio-cells = <0x2>;
    			clocks = <0x2 0x2a>;
    			gpio-controller;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x14 0x4>;
    			reg = <0xe000a000 0x1000>;
    			linux,phandle = <0x5>;
    			phandle = <0x5>;
    		};
    
    		i2c@e0004000 {
    			compatible = "cdns,i2c-r1p10";
    			status = "disabled";
    			clocks = <0x2 0x26>;
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x19 0x4>;
    			reg = <0xe0004000 0x1000>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    		};
    
    		i2c@e0005000 {
    			compatible = "cdns,i2c-r1p10";
    			status = "disabled";
    			clocks = <0x2 0x27>;
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x30 0x4>;
    			reg = <0xe0005000 0x1000>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    		};
    
    		interrupt-controller@f8f01000 {
    			compatible = "arm,cortex-a9-gic";
    			#interrupt-cells = <0x3>;
    			interrupt-controller;
    			reg = <0xf8f01000 0x1000 0xf8f00100 0x100>;
    			linux,phandle = <0x1>;
    			phandle = <0x1>;
    		};
    
    		cache-controller@f8f02000 {
    			compatible = "arm,pl310-cache";
    			reg = <0xf8f02000 0x1000>;
    			interrupts = <0x0 0x2 0x4>;
    			arm,data-latency = <0x3 0x2 0x2>;
    			arm,tag-latency = <0x2 0x2 0x2>;
    			cache-unified;
    			cache-level = <0x2>;
    		};
    
    		memory-controller@f8006000 {
    			compatible = "xlnx,zynq-ddrc-a05";
    			reg = <0xf8006000 0x1000>;
    		};
    
    		ocmc@f800c000 {
    			compatible = "xlnx,zynq-ocmc-1.0";
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x3 0x4>;
    			reg = <0xf800c000 0x1000>;
    		};
    
    		serial@e0000000 {
    			compatible = "xlnx,xuartps", "cdns,uart-r1p8";
    			status = "disabled";
    			clocks = <0x2 0x17 0x2 0x28>;
    			clock-names = "uart_clk", "pclk";
    			reg = <0xe0000000 0x1000>;
    			interrupts = <0x0 0x1b 0x4>;
    		};
    
    		serial@e0001000 {
    			compatible = "xlnx,xuartps", "cdns,uart-r1p8";
    			status = "okay";
    			clocks = <0x2 0x18 0x2 0x29>;
    			clock-names = "uart_clk", "pclk";
    			reg = <0xe0001000 0x1000>;
    			interrupts = <0x0 0x32 0x4>;
    		};
    
    		spi@e0006000 {
    			compatible = "xlnx,zynq-spi-r1p6";
    			reg = <0xe0006000 0x1000>;
    			status = "okay";
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x1a 0x4>;
    			clocks = <0x2 0x19 0x2 0x22>;
    			clock-names = "ref_clk", "pclk";
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    
    			ad9528-1@0 {
    				compatible = "adi,ad9528";
    				reg = <0x0>;
    				#address-cells = <0x1>;
    				#size-cells = <0x0>;
    				spi-max-frequency = <0x989680>;
    				clock-output-names = "ad9528-1_out0", "ad9528-1_out1", "ad9528-1_out2", "ad9528-1_out3", "ad9528-1_out4", "ad9528-1_out5", "ad9528-1_out6", "ad9528-1_out7", "ad9528-1_out8", "ad9528-1_out9", "ad9528-1_out10", "ad9528-1_out11", "ad9528-1_out12", "ad9528-1_out13";
    				#clock-cells = <0x1>;
    				adi,vcxo-freq = <122880000>;
    				adi,refa-enable;
    				adi,refa-diff-rcv-enable;
    				adi,refa-r-div = <0x1>;
    				adi,osc-in-cmos-neg-inp-enable;
    				/* Valid ranges based on VCO locking range:
    				*   1150.000 MHz - 1341.666 MHz
    				*    862.500 MHz - 1006.250 MHz
    				*    690.000 MHz -  805.000 MHz
    				*/
    	
            			adi,pll2-m1-frequency = <1228800000>;
    				adi,pll2-charge-pump-current-nA = <0xc4888>;				
    				/*
    				adi,pll1-feedback-div = <0x4>;
    				adi,pll1-charge-pump-current-nA = <0x1388>;
    				adi,pll2-vco-div-m1 = <0x3>;
    				adi,pll2-n2-div = <0xa>;
    				adi,pll2-r1-div = <0x1>;
    				
    				*/
    				/*
    				adi,sysref-src = <0x2>;
    				adi,sysref-pattern-mode = <0x1>;
    				adi,sysref-k-div = <0x200>;
    				adi,sysref-request-enable;
    				adi,sysref-nshot-mode = <0x3>;
    				adi,sysref-request-trigger-mode = <0x0>;
    				adi,rpole2 = <0x0>;
    				adi,rzero = <0x7>;
    				adi,cpole1 = <0x2>;
    				*/
    				adi,status-mon-pin0-function-select = <0x1>;
    				adi,status-mon-pin1-function-select = <0x7>;
    				reset-gpios = <0x5 0x71 0x0>;
    				linux,phandle = <0x9>;
    				phandle = <0x9>;
    
    				channel@13 {
    					reg = <0xd>;
    					adi,extended-name = "DEV_CLK";
    					adi,driver-mode = <0x0>;
    					adi,divider-phase = <0x0>;
    					adi,channel-divider = <0xa>;
    					adi,signal-source = <0x0>;
    				};
    
    				channel@1 {
    					reg = <0x1>;
    					adi,extended-name = "FMC_CLK";
    					adi,driver-mode = <0x0>;
    					adi,divider-phase = <0x0>;
    					adi,channel-divider = <0xa>;
    					adi,signal-source = <0x0>;
    				};
    
    				channel@12 {
    					reg = <0xc>;
    					adi,extended-name = "DEV_SYSREF";
    					adi,driver-mode = <0x0>;
    					adi,divider-phase = <0x0>;
    					adi,channel-divider = <0xa>;
    					adi,signal-source = <0x2>;
    				};
    
    				channel@3 {
    					reg = <0x3>;
    					adi,extended-name = "FMC_SYSREF";
    					adi,driver-mode = <0x0>;
    					adi,divider-phase = <0x0>;
    					adi,channel-divider = <0xa>;
    					adi,signal-source = <0x2>;
    				};
    			};
    
    			ad9371-phy@1 {
    				compatible = "adi,ad9375";
    				reg = <0x1>;
    				spi-max-frequency = <0x17d7840>;
    				clocks = <0x6 0x7 0x8 0x9 0xd 0x9 0x1 0x9 0xc 0x9 0x3>;
    				clock-names = "jesd_rx_clk", "jesd_tx_clk", "jesd_rx_os_clk", "dev_clk", "fmc_clk", "sysref_dev_clk", "sysref_fmc_clk";
    				clock-output-names = "rx_sampl_clk", "rx_os_sampl_clk", "tx_sampl_clk";
    				#clock-cells = <0x1>;
    				adi,clocks-clk-pll-vco-freq_khz = <9830400>;
    				adi,clocks-device-clock_khz = <122880>;
    				adi,clocks-clk-pll-hs-div = <0x4>;
    				adi,clocks-clk-pll-vco-div = <0x2>;
    				adi,jesd204-obs-framer-over-sample = <0x0>;
    				adi,rx-profile-adc-div = <0x1>;
    				adi,rx-profile-en-high-rej-dec5 = <0x1>;
    				adi,rx-profile-iq-rate_khz = <30720>;
    				adi,rx-profile-rf-bandwidth_hz = <20000000>;
    				adi,rx-profile-rhb1-decimation = <0x2>;
    				adi,rx-profile-rx-bbf-3db-corner_khz = <20000>;
    				adi,rx-profile-rx-dec5-decimation = <0x5>;
    				adi,rx-profile-rx-fir-decimation = <0x4>;
    				adi,rx-profile-rx-fir-gain_db = <0xfffffffa>;
    				adi,rx-profile-rx-fir-num-fir-coefs = <0x30>;
    				adi,rx-profile-rx-fir-coefs = <0xfffbffe6 0x200033 0xffbdff8c 0x8c00d4 0xff04fe91 0x1ad0253 0xfd50fc5d 0x4300593 0xf98ef774 0xa340da8 0xed3ee259 0x25b87e3d 0x7e3d25b8 0xe259ed3e 0xda80a34 0xf774f98e 0x5930430 0xfc5dfd50 0x25301ad 0xfe91ff04 0xd4008c 0xff8cffbd 0x330020 0xffe6fffb>;
    				adi,rx-profile-custom-adc-profile = <0x2160182 0xc90062 0x50001eb 0x6370117 0x51a0068 0x318001c 0x300027 0x1700bb>;
    				adi,obs-profile-adc-div = <0x1>;
    				adi,obs-profile-en-high-rej-dec5 = <1>;
    				adi,obs-profile-iq-rate_khz = <122880>;
    				adi,obs-profile-rf-bandwidth_hz = <100000000>;
    				adi,obs-profile-rhb1-decimation = <1>;
    				adi,obs-profile-rx-bbf-3db-corner_khz = <50000>;
    				adi,obs-profile-rx-dec5-decimation = <5>;
    				adi,obs-profile-rx-fir-decimation = <2>;
    				adi,obs-profile-rx-fir-gain_db = <0x6>;
    				adi,obs-profile-rx-fir-num-fir-coefs = <0x18>;
    				adi,obs-profile-rx-fir-coefs = <0xfedf0051 0xffe9ffaa 0xe5fe9e 0x18dff17 0xfd6f06a3 0xefb459e2 0xefb406a3 0xfd6fff17 0x18dfe9e 0xe5ffaa 0xffe90051 0xfedf0000>;
    				adi,obs-profile-custom-adc-profile = <0x1c2015d 0xc90062 0x50002da 0x65a0332 0x5c402dc 0x3420014 0x290024 0x1800c8>;
    				adi,obs-settings-custom-loopback-adc-profile = <0x2390171 0xc90062 0x5000123 0x6050095 0x528003a 0x3270022 0x300028 0x1700bd>;
    				adi,tx-profile-dac-div = <0x1>;
    				adi,tx-profile-iq-rate_khz = <122880>;
    				adi,tx-profile-primary-sig-bandwidth_hz = <20000000>;
    				adi,tx-profile-rf-bandwidth_hz = <100000000>;
    				adi,tx-profile-thb1-interpolation = <2>;
    				adi,tx-profile-thb2-interpolation = <2>;
    				adi,tx-profile-tx-bbf-3db-corner_khz = <50000>;
    				adi,tx-profile-tx-dac-3db-corner_khz = <100000>;
    				adi,tx-profile-tx-fir-interpolation = <1>;
    				adi,tx-profile-tx-input-hb-interpolation = <1>;
    				adi,tx-profile-tx-fir-gain_db = <0x6>;
    				adi,tx-profile-tx-fir-num-fir-coefs = <0x10>;
    				adi,tx-profile-tx-fir-coefs = <0x6fef2 0xcbff58 0xffac03d7 0xf36a5297 0xf36a03d7 0xffacff58 0xcbfef2 0x60000>;
    
    				adi,obs-settings-obs-rx-channels-enable = <3>; /* Disable Sniffer Profile */
    
    				/*adi,sniffer-profile-adc-div = <0x1>;
    				adi,sniffer-profile-en-high-rej-dec5 = <0x0>;
    				adi,sniffer-profile-iq-rate_khz = <0x7800>;
    				adi,sniffer-profile-rf-bandwidth_hz = <0x1312d00>;
    				adi,sniffer-profile-rhb1-decimation = <0x2>;
    				adi,sniffer-profile-rx-bbf-3db-corner_khz = <0x186a0>;
    				adi,sniffer-profile-rx-dec5-decimation = <0x5>;
    				adi,sniffer-profile-rx-fir-decimation = <0x4>;
    				*/
    				reset-gpios = <0x5 0x6a 0x0>;
    				test-gpios = <0x5 0x6b 0x0>;
    				sysref_req-gpios = <0x5 0x70 0x0>;
    				rx2_enable-gpios = <0x5 0x6c 0x0>;
    				rx1_enable-gpios = <0x5 0x6d 0x0>;
    				tx2_enable-gpios = <0x5 0x6e 0x0>;
    				tx1_enable-gpios = <0x5 0x6f 0x0>;
    				adi,dpd-damping = <0x5>;
    				adi,dpd-num-weights = <0x1>;
    				adi,dpd-model-version = <0x2>;
    				adi,dpd-high-power-model-update = <0x1>;
    				adi,dpd-model-prior-weight = <0x14>;
    				adi,dpd-robust-modeling = <0x0>;
    				adi,dpd-samples = <0x200>;
    				adi,dpd-outlier-threshold = <0x1000>;
    				adi,dpd-additional-delay-offset = <0x0>;
    				adi,dpd-path-delay-pn-seq-level = <0xff>;
    				adi,dpd-weights0-real = <0x40>;
    				adi,dpd-weights0-imag = <0x0>;
    				adi,dpd-weights1-real = <0x0>;
    				adi,dpd-weights1-imag = <0x0>;
    				adi,dpd-weights2-real = <0x0>;
    				adi,dpd-weights2-imag = <0x0>;
    				adi,clgc-tx1-desired-gain = <0xfffff830>;
    				adi,clgc-tx2-desired-gain = <0xfffff830>;
    				adi,clgc-tx1-atten-limit = <0x0>;
    				adi,clgc-tx2-atten-limit = <0x0>;
    				adi,clgc-tx1-control-ratio = <0x4b>;
    				adi,clgc-tx2-control-ratio = <0x4b>;
    				adi,clgc-allow-tx1-atten-updates = <0x1>;
    				adi,clgc-allow-tx2-atten-updates = <0x1>;
    				adi,clgc-additional-delay-offset = <0x0>;
    				adi,clgc-path-delay-pn-seq-level = <0xff>;
    				adi,clgc-tx1-rel-threshold = <0x258>;
    				adi,clgc-tx2-rel-threshold = <0x258>;
    				adi,clgc-tx1-rel-threshold-en = <0x0>;
    				adi,clgc-tx2-rel-threshold-en = <0x0>;
    				adi,vswr-additional-delay-offset = <0x0>;
    				adi,vswr-path-delay-pn-seq-level = <0xff>;
    				adi,vswr-tx1-vswr-switch-gpio3p3-pin = <0x0>;
    				adi,vswr-tx2-vswr-switch-gpio3p3-pin = <0x1>;
    				adi,vswr-tx1-vswr-switch-polarity = <0x0>;
    				adi,vswr-tx2-vswr-switch-polarity = <0x0>;
    				adi,vswr-tx1-vswr-switch-delay_us = <0x32>;
    				adi,vswr-tx2-vswr-switch-delay_us = <0x32>;
    				linux,phandle = <0x13>;
    				phandle = <0x13>;
    			};
    		};
    
    		spi@e0007000 {
    			compatible = "xlnx,zynq-spi-r1p6";
    			reg = <0xe0007000 0x1000>;
    			status = "disabled";
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x31 0x4>;
    			clocks = <0x2 0x1a 0x2 0x23>;
    			clock-names = "ref_clk", "pclk";
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    		};
    
    		spi@e000d000 {
    			clock-names = "ref_clk", "pclk";
    			clocks = <0x2 0xa 0x2 0x2b>;
    			compatible = "xlnx,zynq-qspi-1.0";
    			status = "okay";
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x13 0x4>;
    			reg = <0xe000d000 0x1000>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			is-dual = <0x1>;
    			num-cs = <0x1>;
    
    			ps7-qspi@0 {
    				#address-cells = <0x1>;
    				#size-cells = <0x1>;
    				spi-tx-bus-width = <0x1>;
    				spi-rx-bus-width = <0x4>;
    				compatible = "n25q128a11";
    				reg = <0x0>;
    				spi-max-frequency = <0x2faf080>;
    
    				partition@0 {
    					label = "boot";
    					reg = <0x0 0x500000>;
    				};
    
    				partition@500000 {
    					label = "bootenv";
    					reg = <0x500000 0x20000>;
    				};
    
    				partition@520000 {
    					label = "config";
    					reg = <0x520000 0x20000>;
    				};
    
    				partition@540000 {
    					label = "image";
    					reg = <0x540000 0xa80000>;
    				};
    
    				partition@fc0000 {
    					label = "spare";
    					reg = <0xfc0000 0x0>;
    				};
    			};
    		};
    
    		memory-controller@e000e000 {
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			status = "disabled";
    			clock-names = "memclk", "aclk";
    			clocks = <0x2 0xb 0x2 0x2c>;
    			compatible = "arm,pl353-smc-r2p1";
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x12 0x4>;
    			ranges;
    			reg = <0xe000e000 0x1000>;
    
    			flash@e1000000 {
    				status = "disabled";
    				compatible = "arm,pl353-nand-r2p1";
    				reg = <0xe1000000 0x1000000>;
    				#address-cells = <0x1>;
    				#size-cells = <0x1>;
    			};
    
    			flash@e2000000 {
    				status = "disabled";
    				compatible = "cfi-flash";
    				reg = <0xe2000000 0x2000000>;
    				#address-cells = <0x1>;
    				#size-cells = <0x1>;
    			};
    		};
    
    		ethernet@e000b000 {
    			compatible = "cdns,zynq-gem", "cdns,gem";
    			reg = <0xe000b000 0x1000>;
    			status = "okay";
    			interrupts = <0x0 0x16 0x4>;
    			clocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>;
    			clock-names = "pclk", "hclk", "tx_clk";
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			phy-handle = <0xa>;
    			phy-mode = "rgmii-id";
    
    			phy@7 {
    				device_type = "ethernet-phy";
    				reg = <0x7>;
    				linux,phandle = <0xa>;
    				phandle = <0xa>;
    			};
    		};
    
    		ethernet@e000c000 {
    			compatible = "cdns,zynq-gem", "cdns,gem";
    			reg = <0xe000c000 0x1000>;
    			status = "disabled";
    			interrupts = <0x0 0x2d 0x4>;
    			clocks = <0x2 0x1f 0x2 0x1f 0x2 0xe>;
    			clock-names = "pclk", "hclk", "tx_clk";
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    		};
    
    		mmc@e0100000 {
    			compatible = "arasan,sdhci-8.9a";
    			status = "okay";
    			clock-names = "clk_xin", "clk_ahb";
    			clocks = <0x2 0x15 0x2 0x20>;
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x18 0x4>;
    			reg = <0xe0100000 0x1000>;
    		};
    
    		mmc@e0101000 {
    			compatible = "arasan,sdhci-8.9a";
    			status = "disabled";
    			clock-names = "clk_xin", "clk_ahb";
    			clocks = <0x2 0x16 0x2 0x21>;
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x2f 0x4>;
    			reg = <0xe0101000 0x1000>;
    		};
    
    		slcr@f8000000 {
    			u-boot,dm-pre-reloc;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
    			reg = <0xf8000000 0x1000>;
    			ranges;
    			linux,phandle = <0xb>;
    			phandle = <0xb>;
    
    			clkc@100 {
    				u-boot,dm-pre-reloc;
    				#clock-cells = <0x1>;
    				compatible = "xlnx,ps7-clkc";
    				fclk-enable = <0xf>;
    				clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb";
    				reg = <0x100 0x100>;
    				ps-clk-frequency = <0x1fca055>;
    				linux,phandle = <0x2>;
    				phandle = <0x2>;
    			};
    
    			rstc@200 {
    				compatible = "xlnx,zynq-reset";
    				reg = <0x200 0x48>;
    				#reset-cells = <0x1>;
    				syscon = <0xb>;
    			};
    
    			pinctrl@700 {
    				compatible = "xlnx,pinctrl-zynq";
    				reg = <0x700 0x200>;
    				syscon = <0xb>;
    			};
    		};
    
    		dmac@f8003000 {
    			compatible = "arm,pl330", "arm,primecell";
    			reg = <0xf8003000 0x1000>;
    			interrupt-parent = <0x1>;
    			interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7";
    			interrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>;
    			#dma-cells = <0x1>;
    			#dma-channels = <0x8>;
    			#dma-requests = <0x4>;
    			clocks = <0x2 0x1b>;
    			clock-names = "apb_pclk";
    			linux,phandle = <0x10>;
    			phandle = <0x10>;
    		};
    
    		devcfg@f8007000 {
    			compatible = "xlnx,zynq-devcfg-1.0";
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x8 0x4>;
    			reg = <0xf8007000 0x100>;
    			clocks = <0x2 0xc 0x2 0xf 0x2 0x10 0x2 0x11 0x2 0x12>;
    			clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
    			syscon = <0xb>;
    			linux,phandle = <0x4>;
    			phandle = <0x4>;
    		};
    
    		efuse@f800d000 {
    			compatible = "xlnx,zynq-efuse";
    			reg = <0xf800d000 0x20>;
    		};
    
    		timer@f8f00200 {
    			compatible = "arm,cortex-a9-global-timer";
    			reg = <0xf8f00200 0x20>;
    			interrupts = <0x1 0xb 0x301>;
    			interrupt-parent = <0x1>;
    			clocks = <0x2 0x4>;
    		};
    
    		timer@f8001000 {
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>;
    			compatible = "cdns,ttc";
    			clocks = <0x2 0x6>;
    			reg = <0xf8001000 0x1000>;
    		};
    
    		timer@f8002000 {
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>;
    			compatible = "cdns,ttc";
    			clocks = <0x2 0x6>;
    			reg = <0xf8002000 0x1000>;
    		};
    
    		timer@f8f00600 {
    			interrupt-parent = <0x1>;
    			interrupts = <0x1 0xd 0x301>;
    			compatible = "arm,cortex-a9-twd-timer";
    			reg = <0xf8f00600 0x20>;
    			clocks = <0x2 0x4>;
    		};
    
    		usb@e0002000 {
    			compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
    			status = "okay";
    			clocks = <0x2 0x1c>;
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x15 0x4>;
    			reg = <0xe0002000 0x1000>;
    			phy_type = "ulpi";
    			dr_mode = "host";
    			xlnx,phy-reset-gpio = <0x5 0x7 0x0>;
    		};
    
    		usb@e0003000 {
    			compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
    			status = "disabled";
    			clocks = <0x2 0x1d>;
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x2c 0x4>;
    			reg = <0xe0003000 0x1000>;
    			phy_type = "ulpi";
    		};
    
    		watchdog@f8005000 {
    			clocks = <0x2 0x2d>;
    			compatible = "cdns,wdt-r1p2";
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x9 0x1>;
    			reg = <0xf8005000 0x1000>;
    			timeout-sec = <0xa>;
    		};
    	};
    
    	aliases {
    		ethernet0 = "/amba/ethernet@e000b000";
    		serial0 = "/amba/serial@e0001000";
    	};
    
    	memory {
    		device_type = "memory";
    		reg = <0x0 0x40000000>;
    	};
    
    	chosen {
    		bootargs = "console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait";
    		linux,stdout-path = "/amba@0/uart@E0001000";
    	};
    
    	leds {
    		compatible = "gpio-leds";
    
    		ds8 {
    			label = "ds12:green";
    			gpios = <0x5 0x3d 0x0>;
    		};
    
    		ds9 {
    			label = "ds15:green";
    			gpios = <0x5 0x3e 0x0>;
    		};
    
    		ds10 {
    			label = "ds16:green";
    			gpios = <0x5 0x3f 0x0>;
    		};
    
    		ds35 {
    			label = "ds17:green";
    			gpios = <0x5 0x40 0x0>;
    		};
    	};
    
    	gpio_keys {
    		compatible = "gpio-keys";
    		#address-cells = <0x1>;
    		#size-cells = <0x0>;
    		autorepeat;
    
    		sw7 {
    			label = "Left";
    			linux,code = <0x69>;
    			gpios = <0x5 0x3a 0x0>;
    		};
    
    		sw8 {
    			label = "Right";
    			linux,code = <0x6a>;
    			gpios = <0x5 0x3c 0x0>;
    		};
    
    		sw9 {
    			label = "Select";
    			linux,code = <0x1c>;
    			gpios = <0x5 0x3b 0x0>;
    		};
    	};
    
    	fpga-axi@0 {
    		compatible = "simple-bus";
    		#address-cells = <0x1>;
    		#size-cells = <0x1>;
    		ranges;
    
    		i2c@41600000 {
    			compatible = "xlnx,axi-iic-1.02.a", "xlnx,xps-iic-2.00.a";
    			reg = <0x41600000 0x10000>;
    			interrupt-parent = <0x1>;
    			interrupts = <0x0 0x3a 0x4>;
    			clocks = <0x2 0xf>;
    			clock-names = "pclk";
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    
    			i2cswitch@74 {
    				compatible = "nxp,pca9548";
    				#address-cells = <0x1>;
    				#size-cells = <0x0>;
    				reg = <0x74>;
    
    				i2c@0 {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					reg = <0x0>;
    
    					osc@5d {
    						compatible = "si570";
    						temperature-stability = <0x32>;
    						reg = <0x5d>;
    						factory-fout = <0x9502f90>;
    						initial-fout = <0x8d9ee20>;
    					};
    				};
    
    				i2c@1 {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					reg = <0x1>;
    
    					adv7511 {
    						compatible = "adi,adv7511";
    						reg = <0x39 0x3f>;
    						reg-names = "primary", "edid";
    						adi,input-depth = <0x8>;
    						adi,input-colorspace = "rgb";
    						adi,input-clock = "1x";
    						adi,clock-delay = <0x0>;
    						#sound-dai-cells = <0x0>;
    						linux,phandle = <0x1d>;
    						phandle = <0x1d>;
    
    						ports {
    							#address-cells = <0x1>;
    							#size-cells = <0x0>;
    
    							port@0 {
    								reg = <0x0>;
    
    								endpoint {
    									remote-endpoint = <0xc>;
    									linux,phandle = <0xf>;
    									phandle = <0xf>;
    								};
    							};
    
    							port@1 {
    								reg = <0x1>;
    							};
    						};
    					};
    				};
    
    				i2c@2 {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					reg = <0x2>;
    
    					eeprom@54 {
    						compatible = "at,24c08";
    						reg = <0x54>;
    					};
    				};
    
    				i2c@3 {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					reg = <0x3>;
    
    					gpio@21 {
    						compatible = "ti,tca6416";
    						reg = <0x21>;
    						gpio-controller;
    						#gpio-cells = <0x2>;
    					};
    				};
    
    				i2c@4 {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					reg = <0x4>;
    
    					rtc@54 {
    						compatible = "nxp,pcf8563";
    						reg = <0x51>;
    					};
    				};
    
    				i2c@5 {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					reg = <0x5>;
    
    					eeprom@50 {
    						compatible = "at24,24c02";
    						reg = <0x50>;
    					};
    
    					eeprom@54 {
    						compatible = "at24,24c02";
    						reg = <0x54>;
    					};
    
    					ad7291@2f {
    						compatible = "adi,ad7291";
    						reg = <0x2f>;
    					};
    				};
    			};
    		};
    
    		dma@43000000 {
    			compatible = "adi,axi-dmac-1.00.a";
    			reg = <0x43000000 0x10000>;
    			#dma-cells = <0x1>;
    			interrupts = <0x0 0x3b 0x0>;
    			clocks = <0x2 0x10>;
    			linux,phandle = <0xd>;
    			phandle = <0xd>;
    
    			adi,channels {
    				#size-cells = <0x0>;
    				#address-cells = <0x1>;
    
    				dma-channel@0 {
    					reg = <0x0>;
    					adi,source-bus-width = <0x40>;
    					adi,source-bus-type = <0x0>;
    					adi,destination-bus-width = <0x40>;
    					adi,destination-bus-type = <0x1>;
    				};
    			};
    		};
    
    		axi-clkgen@79000000 {
    			compatible = "adi,axi-clkgen-2.00.a";
    			reg = <0x79000000 0x10000>;
    			#clock-cells = <0x0>;
    			clocks = <0x2 0x10>;
    			linux,phandle = <0xe>;
    			phandle = <0xe>;
    		};
    
    		axi_hdmi@70e00000 {
    			compatible = "adi,axi-hdmi-tx-1.00.a";
    			reg = <0x70e00000 0x10000>;
    			dmas = <0xd 0x0>;
    			dma-names = "video";
    			clocks = <0xe>;
    			adi,is-rgb;
    
    			port {
    
    				endpoint {
    					remote-endpoint = <0xf>;
    					linux,phandle = <0xc>;
    					phandle = <0xc>;
    				};
    			};
    		};
    
    		axi-spdif-tx@75c00000 {
    			compatible = "adi,axi-spdif-tx-1.00.a";
    			reg = <0x75c00000 0x1000>;
    			dmas = <0x10 0x0>;
    			dma-names = "tx";
    			clocks = <0x2 0xf 0x11>;
    			clock-names = "axi", "ref";
    			#sound-dai-cells = <0x0>;
    			linux,phandle = <0x1c>;
    			phandle = <0x1c>;
    		};
    
    		axi-sysid-0@45000000 {
    			compatible = "adi,axi-sysid-1.00.a";
    			reg = <0x45000000 0x10000>;
    		};
    
    		rx-dmac@7c400000 {
    			compatible = "adi,axi-dmac-1.00.a";
    			reg = <0x7c400000 0x10000>;
    			#dma-cells = <0x1>;
    			interrupts = <0x0 0x39 0x0>;
    			clocks = <0x2 0x10>;
    			linux,phandle = <0x12>;
    			phandle = <0x12>;
    
    			adi,channels {
    				#size-cells = <0x0>;
    				#address-cells = <0x1>;
    
    				dma-channel@0 {
    					reg = <0x0>;
    					adi,source-bus-width = <0x40>;
    					adi,source-bus-type = <0x2>;
    					adi,destination-bus-width = <0x40>;
    					adi,destination-bus-type = <0x0>;
    				};
    			};
    		};
    
    		rx-obs-dmac@7c440000 {
    			compatible = "adi,axi-dmac-1.00.a";
    			reg = <0x7c440000 0x10000>;
    			#dma-cells = <0x1>;
    			interrupts = <0x0 0x37 0x0>;
    			clocks = <0x2 0x10>;
    			linux,phandle = <0x14>;
    			phandle = <0x14>;
    
    			adi,channels {
    				#size-cells = <0x0>;
    				#address-cells = <0x1>;
    
    				dma-channel@0 {
    					reg = <0x0>;
    					adi,source-bus-width = <0x40>;
    					adi,source-bus-type = <0x2>;
    					adi,destination-bus-width = <0x40>;
    					adi,destination-bus-type = <0x0>;
    				};
    			};
    		};
    
    		tx-dmac@7c420000 {
    			compatible = "adi,axi-dmac-1.00.a";
    			reg = <0x7c420000 0x10000>;
    			#dma-cells = <0x1>;
    			interrupts = <0x0 0x38 0x0>;
    			clocks = <0x2 0x10>;
    			linux,phandle = <0x15>;
    			phandle = <0x15>;
    
    			adi,channels {
    				#size-cells = <0x0>;
    				#address-cells = <0x1>;
    
    				dma-channel@0 {
    					reg = <0x0>;
    					adi,source-bus-width = <0x40>;
    					adi,source-bus-type = <0x0>;
    					adi,destination-bus-width = <0x80>;
    					adi,destination-bus-type = <0x1>;
    				};
    			};
    		};
    
    		axi-ad9371-rx-hpc@44a00000 {
    			compatible = "adi,axi-ad9371-rx-1.0";
    			reg = <0x44a00000 0x8000>;
    			dmas = <0x12 0x0>;
    			dma-names = "rx";
    			spibus-connected = <0x13>;
    			adi,axi-decimation-core-available;
    			decimation-gpios = <0x5 0x73 0x0>;
    		};
    
    		axi-ad9371-rx-obs-hpc@44a08000 {
    			compatible = "adi,axi-ad9371-obs-1.0";
    			reg = <0x44a08000 0x1000>;
    			dmas = <0x14 0x0>;
    			dma-names = "rx";
    			clocks = <0x13 0x1>;
    			clock-names = "sampl_clk";
    		};
    
    		axi-ad9371-tx-hpc@44a04000 {
    			compatible = "adi,axi-ad9371-tx-1.0";
    			reg = <0x44a04000 0x4000>;
    			dmas = <0x15 0x0>;
    			dma-names = "tx";
    			clocks = <0x13 0x2>;
    			clock-names = "sampl_clk";
    			spibus-connected = <0x13>;
    			adi,axi-pl-fifo-enable;
    			adi,axi-interpolation-core-available;
    			interpolation-gpios = <0x5 0x74 0x0>;
    			plddrbypass-gpios = <0x5 0x72 0x0>;
    		};
    
    		axi-jesd204-rx@44aa0000 {
    			compatible = "adi,axi-jesd204-rx-1.0";
    			reg = <0x44aa0000 0x1000>;
    			interrupts = <0x0 0x36 0x0>;
    			clocks = <0x2 0x10 0x16 0x17 0x0>;
    			clock-names = "s_axi_aclk", "device_clk", "lane_clk";
    			#clock-cells = <0x0>;
    			clock-output-names = "jesd_rx_lane_clk";
    			adi,octets-per-frame = <0x4>;
    			adi,frames-per-multiframe = <0x20>;
    			linux,phandle = <0x6>;
    			phandle = <0x6>;
    		};
    
    		axi-jesd204-tx@44a90000 {
    			compatible = "adi,axi-jesd204-tx-1.0";
    			reg = <0x44a90000 0x1000>;
    			interrupts = <0x0 0x35 0x0>;
    			clocks = <0x2 0x10 0x18 0x19 0x0>;
    			clock-names = "s_axi_aclk", "device_clk", "lane_clk";
    			#clock-cells = <0x0>;
    			clock-output-names = "jesd_tx_lane_clk";
    			adi,octets-per-frame = <0x2>;
    			adi,frames-per-multiframe = <0x20>;
    			adi,converter-resolution = <0xe>;
    			adi,bits-per-sample = <0x10>;
    			adi,converters-per-device = <0x4>;
    			adi,control-bits-per-sample = <0x2>;
    			linux,phandle = <0x7>;
    			phandle = <0x7>;
    		};
    
    		axi-jesd204-rx@44ab0000 {
    			compatible = "adi,axi-jesd204-rx-1.0";
    			reg = <0x44ab0000 0x1000>;
    			interrupts = <0x0 0x34 0x0>;
    			clocks = <0x2 0x10 0x1a 0x1b 0x0>;
    			clock-names = "s_axi_aclk", "device_clk", "lane_clk";
    			#clock-cells = <0x0>;
    			clock-output-names = "jesd_rx_os_lane_clk";
    			adi,octets-per-frame = <0x2>;
    			adi,frames-per-multiframe = <0x20>;
    			linux,phandle = <0x8>;
    			phandle = <0x8>;
    		};
    
    		axi-clkgen@43c00000 {
    			compatible = "adi,axi-clkgen-2.00.a";
    			reg = <0x43c00000 0x10000>;
    			#clock-cells = <0x0>;
    			clocks = <0x9 0x1>;
    			clock-output-names = "axi_tx_clkgen";
    			linux,phandle = <0x18>;
    			phandle = <0x18>;
    		};
    
    		axi-clkgen@43c10000 {
    			compatible = "adi,axi-clkgen-2.00.a";
    			reg = <0x43c10000 0x10000>;
    			#clock-cells = <0x0>;
    			clocks = <0x9 0x1>;
    			clock-output-names = "axi_rx_clkgen";
    			linux,phandle = <0x16>;
    			phandle = <0x16>;
    		};
    
    		axi-clkgen@43c20000 {
    			compatible = "adi,axi-clkgen-2.00.a";
    			reg = <0x43c20000 0x10000>;
    			#clock-cells = <0x0>;
    			clocks = <0x9 0x1>;
    			clock-output-names = "axi_rx_os_clkgen";
    			linux,phandle = <0x1a>;
    			phandle = <0x1a>;
    		};
    
    		axi-adxcvr-rx@44a60000 {
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			compatible = "adi,axi-adxcvr-1.0";
    			reg = <0x44a60000 0x1000>;
    			clocks = <0x9 0x1 0x16 0x0>;
    			clock-names = "conv", "div40";
    			#clock-cells = <0x1>;
    			clock-output-names = "rx_gt_clk", "rx_out_clk";
    			adi,sys-clk-select = <0x0>;
    			adi,out-clk-select = <0x3>;
    			adi,use-lpm-enable;
    			adi,use-cpll-enable;
    			linux,phandle = <0x17>;
    			phandle = <0x17>;
    		};
    
    		axi-adxcvr-rx-os@44a50000 {
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			compatible = "adi,axi-adxcvr-1.0";
    			reg = <0x44a50000 0x1000>;
    			clocks = <0x9 0x1 0x1a>;
    			clock-names = "conv", "div40";
    			#clock-cells = <0x1>;
    			clock-output-names = "rx_os_gt_clk", "rx_os_out_clk";
    			adi,sys-clk-select = <0x0>;
    			adi,out-clk-select = <0x3>;
    			adi,use-lpm-enable;
    			adi,use-cpll-enable;
    			linux,phandle = <0x1b>;
    			phandle = <0x1b>;
    		};
    
    		axi-adxcvr-tx@44a80000 {
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			compatible = "adi,axi-adxcvr-1.0";
    			reg = <0x44a80000 0x1000>;
    			clocks = <0x9 0x1 0x18>;
    			clock-names = "conv", "div40";
    			#clock-cells = <0x1>;
    			clock-output-names = "tx_gt_clk", "tx_out_clk";
    			adi,sys-clk-select = <0x3>;
    			adi,out-clk-select = <0x3>;
    			linux,phandle = <0x19>;
    			phandle = <0x19>;
    		};
    	};
    
    	audio_clock {
    		compatible = "fixed-clock";
    		#clock-cells = <0x0>;
    		clock-frequency = <0xbb8000>;
    		linux,phandle = <0x11>;
    		phandle = <0x11>;
    	};
    
    	adv7511_hdmi_snd {
    		compatible = "simple-audio-card";
    		simple-audio-card,name = "HDMI monitor";
    		simple-audio-card,widgets = "Speaker", "Speaker";
    		simple-audio-card,routing = "Speaker", "TX";
    
    		simple-audio-card,dai-link@0 {
    			format = "spdif";
    
    			cpu {
    				sound-dai = <0x1c>;
    				frame-master;
    				bitclock-master;
    			};
    
    			codec {
    				sound-dai = <0x1d>;
    			};
    		};
    	};
    };
    
    <profile AD9371 version=0 name=Rx 20, IQrate 30.720>
     <clocks>
      <deviceClock_kHz=122880>
      <clkPllVcoFreq_kHz=9830400>
      <clkPllVcoDiv=2>
      <clkPllHsDiv=4>
     </clocks>
    
     <rx>
      <adcDiv=1>
      <rxFirDecimation=4>
      <rxDec5Decimation=5>
      <enHighRejDec5=1>
      <rhb1Decimation=2>
      <iqRate_kHz=30720>
      <rfBandwidth_Hz=20000000>
      <rxBbf3dBCorner_kHz=20000>
    
      <filter FIR gain=-6 num=72>
      0
      2
      4
      3
      -4
      -14
      -21
      -12
      17
      56
      73
      39
      -53
      -159
      -198
      -101
      129
      377
      457
      229
      -274
      -793
      -951
      -482
      527
      1564
      1899
      1011
      -978
      -3154
      -4109
      -2611
      1669
      7795
      13807
      17524
      17524
      13807
      7795
      1669
      -2611
      -4109
      -3154
      -978
      1011
      1899
      1564
      527
      -482
      -951
      -793
      -274
      229
      457
      377
      129
      -101
      -198
      -159
      -53
      39
      73
      56
      17
      -12
      -21
      -14
      -4
      3
      4
      2
      0
      </filter>
    
      <adc-profile num=16>
      599
      357
      201
      98
      1280
      112
      1505
      53
      1331
      21
      820
      40
      48
      40
      23
      191
      </adc-profile>
     </rx>
    
     <obs>
      <adcDiv=1>
      <rxFirDecimation=2>
      <rxDec5Decimation=5>
      <enHighRejDec5=1>
      <rhb1Decimation=1>
      <iqRate_kHz=122880>
      <rfBandwidth_Hz=100000000>
      <rxBbf3dBCorner_kHz=50000>
    
      <filter FIR gain=0 num=48>
      0
      -21
      18
      39
      -36
      -87
      81
      157
      -149
      -269
      260
      432
      -423
      -672
      668
      1025
      -1036
      -1570
      1650
      2547
      -2971
      -5686
      4361
      18361
      18361
      4361
      -5686
      -2971
      2547
      1650
      -1570
      -1036
      1025
      668
      -672
      -423
      432
      260
      -269
      -149
      157
      81
      -87
      -36
      39
      18
      -21
      0
      </filter>
    
      <adc-profile num=16>
      534
      386
      201
      98
      1280
      491
      1591
      279
      1306
      104
      792
      28
      48
      39
      23
      187
      </adc-profile>
    
      <lpbk-adc-profile num=16>
      599
      357
      201
      98
      1280
      112
      1505
      53
      1331
      21
      820
      40
      48
      40
      23
      191
      </lpbk-adc-profile>
     </obs>
    
     <tx>
      <dacDiv=2.5>
      <txFirInterpolation=1>
      <thb1Interpolation=2>
      <thb2Interpolation=2>
      <txInputHbInterpolation=1>
      <iqRate_kHz=122880>
      <primarySigBandwidth_Hz=20000000>
      <rfBandwidth_Hz=100000000>
      <txDac3dBCorner_kHz=100000>
      <txBbf3dBCorner_kHz=50000>
    
      <filter FIR gain=6 num=16>
      7
      -244
      182
      -149
      -81
      909
      -2806
      20438
      -2806
      909
      -81
      -149
      182
      -244
      7
      0
      </filter>
     </tx>
    </profile>
    

  • I used BOOT.BIN 28 July 2021 (2019_R2 Released) wiki.analog.com/.../embedded_arm_images this is the latest version that is on the site, unfortunately I am not able to build an HDL project branches MASTER (vivado 2021.2) weighs a lot, uImage and dtb I collected from the git repo master branch, if you have a link or a ready-made BOOT.BIN (master) I could try, at the moment I can fully build 2019_1 and 2019_2, can I try to fix the work of jesd204 on the 2019_1 version?

  • 'this is the 2019_1 output of what i sent earlier, rx keeps switching

  • I'm looking into this right now. And I think I can replicate things on my side.

    Will get back to you later today.

    -Michael

  • Hi,

    Can you give this a try?

    Changes fixes will be committed tomorrow or early next week.

     

    AD9375-ZC706.zip

    -Michael

  • hi, thanks for the quick reply, I'll try tomorrow

  • Copying Linux from SD to RAM...
    reading uImage
    6996136 bytes read in 402 ms (16.6 MiB/s)
    reading devicetree.dtb
    32566 bytes read in 23 ms (1.3 MiB/s)
    ** Unable to read file uramdisk.image.gz **
    ## Booting kernel from Legacy Image at 03000000 ...
    Image Name: Linux-5.10.0-19263-g782606bd4fcf
    Image Type: ARM Linux Kernel Image (uncompressed)
    Data Size: 6996072 Bytes = 6.7 MiB
    Load Address: 00008000
    Entry Point: 00008000
    Verifying Checksum ... OK
    ## Flattened Device Tree blob at 02a00000
    Booting using the fdt blob at 0x2a00000
    Loading Kernel Image ... OK
    Loading Device Tree to 1fff5000, end 1fffff35 ... OK

    Starting kernel ...

    Booting Linux on physical CPU 0x0
    Linux version 5.10.0-19263-g782606bd4fcf-dirty (michael@mhenneri-D06) (arm-linux-gnueabihf-gcc (GCC) 8.2.0, GNU ld (Linaro_Binutils-) 2.31) #2886 SMP PREEMPT Thu Feb 10 17:28:19 CET 2022
    CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
    CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
    OF: fdt: Machine model: Xilinx Zynq ZC706
    OF: fdt: earlycon: stdout-path /amba@0/uart@E0001000 not found
    Memory policy: Data cache writealloc
    cma: Reserved 128 MiB at 0x38000000
    Zone ranges:
    Normal [mem 0x0000000000000000-0x000000002fffffff]
    HighMem [mem 0x0000000030000000-0x000000003fffffff]
    Movable zone start for each node
    Early memory node ranges
    node 0: [mem 0x0000000000000000-0x000000003fffffff]
    Initmem setup node 0 [mem 0x0000000000000000-0x000000003fffffff]
    percpu: Embedded 15 pages/cpu s29900 r8192 d23348 u61440
    Built 1 zonelists, mobility grouping on. Total pages: 260608
    Kernel command line: console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlycon rootfstype=ext4 rootwait cpuidle.off=1
    Dentry cache hash table entries: 131072 (order: 7, 524288 bytes, linear)
    Inode-cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
    mem auto-init: stack:off, heap alloc:off, heap free:off
    Memory: 887372K/1048576K available (10240K kernel code, 774K rwdata, 7272K rodata, 1024K init, 170K bss, 30132K reserved, 131072K cma-reserved, 131072K highmem)
    rcu: Preemptible hierarchical RCU implementation.
    rcu: RCU event tracing is enabled.
    rcu: RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
    Trampoline variant of Tasks RCU enabled.
    rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
    rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
    NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
    efuse mapped to (ptrval)
    slcr mapped to (ptrval)
    L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
    L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
    L2C-310 erratum 769419 enabled
    L2C-310 enabling early BRESP for Cortex-A9
    L2C-310 full line of zeros enabled for Cortex-A9
    L2C-310 ID prefetch enabled, offset 1 lines
    L2C-310 dynamic clock gating enabled, standby mode enabled
    L2C-310 cache controller enabled, 8 ways, 512 kB
    L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
    random: get_random_bytes called from start_kernel+0x340/0x4cc with crng_init=0
    zynq_clock_init: clkc starts at (ptrval)
    Zynq clock init
    sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 4398046511103ns
    clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4ce07af025, max_idle_ns: 440795209040 ns
    Switching to timer-based delay loop, resolution 3ns
    clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 537538477 ns
    timer #0 at (ptrval), irq=25
    Console: colour dummy device 80x30
    Calibrating delay loop (skipped), value calculated using timer frequency.. 666.66 BogoMIPS (lpj=3333333)
    pid_max: default: 32768 minimum: 301
    Mount-cache hash table entries: 2048 (order: 1, 8192 bytes, linear)
    Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes, linear)
    CPU: Testing write buffer coherency: ok
    CPU0: Spectre v2: using BPIALL workaround
    CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
    Setting up static identity map for 0x100000 - 0x100060
    rcu: Hierarchical SRCU implementation.
    smp: Bringing up secondary CPUs ...
    CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
    CPU1: Spectre v2: using BPIALL workaround
    smp: Brought up 1 node, 2 CPUs
    SMP: Total of 2 processors activated (1333.33 BogoMIPS).
    CPU: All CPU(s) started in SVC mode.
    devtmpfs: initialized
    VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
    clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
    futex hash table entries: 512 (order: 3, 32768 bytes, linear)
    pinctrl core: initialized pinctrl subsystem
    NET: Registered protocol family 16
    DMA: preallocated 256 KiB pool for atomic coherent allocations
    thermal_sys: Registered thermal governor 'step_wise'
    hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
    hw-breakpoint: maximum watchpoint size is 4 bytes.
    zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0x(ptrval)
    e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 33, base_baud = 3125000) is a xuartps
    printk: console [ttyPS0] enabled
    SCSI subsystem initialized
    usbcore: registered new interface driver usbfs
    usbcore: registered new interface driver hub
    usbcore: registered new device driver usb
    mc: Linux media interface: v0.10
    videodev: Linux video capture interface: v2.00
    jesd204: created con: id=0, topo=0, link=0, /axi/spi@e0006000/ad9528-1@0 <-> /fpga-axi@0/axi-adxcvr-tx@44a80000
    jesd204: created con: id=1, topo=0, link=2, /axi/spi@e0006000/ad9528-1@0 <-> /fpga-axi@0/axi-adxcvr-rx-os@44a50000
    jesd204: created con: id=2, topo=0, link=1, /axi/spi@e0006000/ad9528-1@0 <-> /fpga-axi@0/axi-adxcvr-rx@44a60000
    jesd204: created con: id=3, topo=0, link=2, /fpga-axi@0/axi-adxcvr-rx-os@44a50000 <-> /fpga-axi@0/axi-jesd204-rx@44ab0000
    jesd204: created con: id=4, topo=0, link=0, /fpga-axi@0/axi-adxcvr-tx@44a80000 <-> /fpga-axi@0/axi-jesd204-tx@44a90000
    jesd204: created con: id=5, topo=0, link=1, /fpga-axi@0/axi-adxcvr-rx@44a60000 <-> /fpga-axi@0/axi-jesd204-rx@44aa0000
    jesd204: created con: id=6, topo=0, link=0, /fpga-axi@0/axi-jesd204-tx@44a90000 <-> /fpga-axi@0/axi-ad9371-tx-hpc@44a04000
    jesd204: created con: id=7, topo=0, link=1, /fpga-axi@0/axi-jesd204-rx@44aa0000 <-> /axi/spi@e0006000/ad9371-phy@1
    jesd204: created con: id=8, topo=0, link=2, /fpga-axi@0/axi-jesd204-rx@44ab0000 <-> /axi/spi@e0006000/ad9371-phy@1
    jesd204: created con: id=9, topo=0, link=0, /fpga-axi@0/axi-ad9371-tx-hpc@44a04000 <-> /axi/spi@e0006000/ad9371-phy@1
    jesd204: /axi/spi@e0006000/ad9371-phy@1: JESD204[0] transition uninitialized -> initialized
    jesd204: /axi/spi@e0006000/ad9371-phy@1: JESD204[1] transition uninitialized -> initialized
    jesd204: /axi/spi@e0006000/ad9371-phy@1: JESD204[2] transition uninitialized -> initialized
    jesd204: found 9 devices and 1 topologies
    FPGA manager framework
    Advanced Linux Sound Architecture Driver Initialized.
    clocksource: Switched to clocksource arm_global_timer
    NET: Registered protocol family 2
    tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes, linear)
    TCP established hash table entries: 8192 (order: 3, 32768 bytes, linear)
    TCP bind hash table entries: 8192 (order: 4, 65536 bytes, linear)
    TCP: Hash tables configured (established 8192 bind 8192)
    UDP hash table entries: 512 (order: 2, 16384 bytes, linear)
    UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear)
    NET: Registered protocol family 1
    hw perfevents: no interrupt-affinity property for /pmu@f8891000, guessing.
    hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
    workingset: timestamp_bits=30 max_order=18 bucket_order=0
    bounce: pool size: 64 pages
    io scheduler mq-deadline registered
    io scheduler kyber registered
    zynq-pinctrl 700.pinctrl: zynq pinctrl initialized
    dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-241330
    dma-pl330 f8003000.dmac: DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
    brd: module loaded
    loop: module loaded
    Registered mathworks_ip class
    spi-nor spi1.0: found s25fl128s1, expected n25q128a11
    random: fast init done
    random: crng init done
    spi-nor spi1.0: trying to lock already unlocked area
    spi-nor spi1.0: s25fl128s1 (32768 Kbytes)
    5 fixed-partitions partitions found on MTD device spi1.0
    Creating 5 MTD partitions on "spi1.0":
    0x000000000000-0x000000500000 : "boot"
    0x000000500000-0x000000520000 : "bootenv"
    0x000000520000-0x000000540000 : "config"
    0x000000540000-0x000000fc0000 : "image"
    0x000000fc0000-0x000002000000 : "spare"
    MACsec IEEE 802.1AE
    libphy: Fixed MDIO Bus: probed
    tun: Universal TUN/TAP device driver, 1.6
    libphy: MACB_mii_bus: probed
    macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 36 (00:0a:35:00:01:22)
    usbcore: registered new interface driver asix
    usbcore: registered new interface driver ax88179_178a
    usbcore: registered new interface driver cdc_ether
    usbcore: registered new interface driver net1080
    usbcore: registered new interface driver cdc_subset
    usbcore: registered new interface driver zaurus
    usbcore: registered new interface driver cdc_ncm
    ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
    usbcore: registered new interface driver uas
    usbcore: registered new interface driver usb-storage
    usbcore: registered new interface driver usbserial_generic
    usbserial: USB Serial support registered for generic
    usbcore: registered new interface driver ftdi_sio
    usbserial: USB Serial support registered for FTDI USB Serial Device
    usbcore: registered new interface driver upd78f0730
    usbserial: USB Serial support registered for upd78f0730
    ULPI transceiver vendor/product ID 0x0424/0x0007
    Found SMSC USB3320 ULPI transceiver.
    ULPI integrity check: passed.
    ci_hdrc ci_hdrc.0: EHCI Host Controller
    ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1
    ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00
    usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.10
    usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
    usb usb1: Product: EHCI Host Controller
    usb usb1: Manufacturer: Linux 5.10.0-19263-g782606bd4fcf-dirty ehci_hcd
    usb usb1: SerialNumber: ci_hdrc.0
    hub 1-0:1.0: USB hub found
    hub 1-0:1.0: 1 port detected
    i2c /dev entries driver
    si570 1-005d: registered, current frequency 156250000 Hz
    i2c i2c-0: Added multiplexed i2c bus 1
    adv7511 2-0039: supply avdd not found, using dummy regulator
    adv7511 2-0039: supply dvdd not found, using dummy regulator
    adv7511 2-0039: supply pvdd not found, using dummy regulator
    adv7511 2-0039: supply bgvdd not found, using dummy regulator
    adv7511 2-0039: supply dvdd-3v not found, using dummy regulator
    i2c i2c-0: Added multiplexed i2c bus 2
    at24 3-0054: supply vcc not found, using dummy regulator
    at24 3-0054: 1024 byte 24c08 EEPROM, writable, 1 bytes/write
    i2c i2c-0: Added multiplexed i2c bus 3
    pca953x 4-0021: supply vcc not found, using dummy regulator
    pca953x 4-0021: using no AI
    i2c i2c-0: Added multiplexed i2c bus 4
    rtc-pcf8563 5-0051: registered as rtc0
    rtc-pcf8563 5-0051: setting system clock to 2022-02-11T05:26:44 UTC (1644557204)
    i2c i2c-0: Added multiplexed i2c bus 5
    at24 6-0050: supply vcc not found, using dummy regulator
    at24 6-0050: 256 byte 24c02 EEPROM, writable, 1 bytes/write
    i2c i2c-0: Added multiplexed i2c bus 6
    i2c i2c-0: Added multiplexed i2c bus 7
    i2c i2c-0: Added multiplexed i2c bus 8
    pca954x 0-0074: registered 8 multiplexed busses for I2C switch pca9548
    usbcore: registered new interface driver uvcvideo
    USB Video Class driver (1.1.1)
    gspca_main: v2.14.0 registered
    cdns-wdt f8005000.watchdog: Xilinx Watchdog Timer with timeout 10s
    Xilinx Zynq CpuIdle Driver started
    failed to register cpuidle driver
    sdhci: Secure Digital Host Controller Interface driver
    sdhci: Copyright(c) Pierre Ossman
    sdhci-pltfm: SDHCI platform and OF driver helper
    ledtrig-cpu: registered to indicate activity on CPUs
    hid: raw HID events driver (C) Jiri Kosina
    usbcore: registered new interface driver usbhid
    usbhid: USB HID core driver
    ad9371 spi0.1: ad9371_probe : enter
    mmc0: SDHCI controller on e0100000.mmc [e0100000.mmc] using ADMA
    ad9528 spi0.0: supply vcc not found, using dummy regulator
    mmc0: new high speed SDHC card at address aaaa
    mmcblk0: mmc0:aaaa SC16G 14.8 GiB
    mmcblk0: p1 p2 p3
    jesd204: /axi/spi@e0006000/ad9528-1@0,jesd204:0,parent=spi0.0: Using as SYSREF provider
    axi_adxcvr 44a60000.axi-adxcvr-rx: AXI-ADXCVR-RX (17.05.a) using CPLL on GTX2 at 0x44A60000. Number of lanes: 2.
    usb 1-1: new high-speed USB device number 2 using ci_hdrc
    axi_adxcvr 44a50000.axi-adxcvr-rx-os: AXI-ADXCVR-RX (17.05.a) using CPLL on GTX2 at 0x44A50000. Number of lanes: 2.
    axi_adxcvr 44a80000.axi-adxcvr-tx: AXI-ADXCVR-TX (17.05.a) using QPLL on GTX2 at 0x44A80000. Number of lanes: 4.
    axi_sysid 45000000.axi-sysid-0: AXI System ID core version (1.01.a) found
    axi_sysid 45000000.axi-sysid-0: [adrv9371x] on [zc706] git branch <fix_9371_9009_ref_clk> git <692db64086564104c1407353c61db7ca6a56a02e> clean [2022-02-10 13:59:04] UTC
    fpga_manager fpga0: Xilinx Zynq FPGA Manager registered
    usbcore: registered new interface driver snd-usb-audio
    NET: Registered protocol family 10
    Segment Routing with IPv6
    sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
    NET: Registered protocol family 17
    NET: Registered protocol family 36
    Registering SWP/SWPB emulation handler
    [drm] Initialized axi_hdmi_drm 1.0.0 20120930 for 70e00000.axi_hdmi on minor 0
    usb 1-1: New USB device found, idVendor=1a40, idProduct=0201, bcdDevice= 1.00
    usb 1-1: New USB device strings: Mfr=0, Product=1, SerialNumber=0
    usb 1-1: Product: USB 2.0 Hub [MTT]
    hub 1-1:1.0: USB hub found
    hub 1-1:1.0: 7 ports detected
    Console: switching to colour frame buffer device 240x67
    axi-hdmi 70e00000.axi_hdmi: [drm] fb0: axi_hdmi_drmdrm frame buffer device
    ad9371 spi0.1: ad9371_probe : enter
    cf_axi_dds 44a04000.axi-ad9371-tx-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x44A04000 mapped to 0x2d334382, probed DDS AD9371
    axi-jesd204-rx 44aa0000.axi-jesd204-rx: AXI-JESD204-RX (1.07.a) at 0x44AA0000. Encoder 8b10b, width 4/4, lanes 2, jesd204-fsm.
    axi-jesd204-rx 44ab0000.axi-jesd204-rx: AXI-JESD204-RX (1.07.a) at 0x44AB0000. Encoder 8b10b, width 4/4, lanes 2, jesd204-fsm.
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition initialized -> probed
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition initialized -> probed
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition initialized -> probed
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition probed -> idle
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition probed -> idle
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition probed -> idle
    usb 1-1.1: new low-speed USB device number 3 using ci_hdrc
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition idle -> device_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition idle -> device_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition idle -> device_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition device_init -> link_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition device_init -> link_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition device_init -> link_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_init -> link_supported
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_init -> link_supported
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_init -> link_supported
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_supported -> link_pre_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_supported -> link_pre_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_supported -> link_pre_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_pre_setup -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_pre_setup -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_pre_setup -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage1 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage1 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage1 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage2 -> clk_sync_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage2 -> clk_sync_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage2 -> clk_sync_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage3 -> link_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage3 -> link_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage3 -> link_setup
    usb 1-1.1: New USB device found, idVendor=2a7a, idProduct=2eb2, bcdDevice= 0.01
    usb 1-1.1: New USB device strings: Mfr=0, Product=2, SerialNumber=0
    usb 1-1.1: Product: USBKB
    input: USBKB as /devices/soc0/axi/e0002000.usb/ci_hdrc.0/usb1/1-1/1-1.1/1-1.1:1.0/0003:2A7A:2EB2.0001/input/input0
    hid-generic 0003:2A7A:2EB2.0001: input,hidraw0: USB HID v1.10 Keyboard [USBKB] on usb-ci_hdrc.0-1.1/input0
    input: USBKB Consumer Control as /devices/soc0/axi/e0002000.usb/ci_hdrc.0/usb1/1-1/1-1.1/1-1.1:1.1/0003:2A7A:2EB2.0002/input/input1
    input: USBKB System Control as /devices/soc0/axi/e0002000.usb/ci_hdrc.0/usb1/1-1/1-1.1/1-1.1:1.1/0003:2A7A:2EB2.0002/input/input2
    hid-generic 0003:2A7A:2EB2.0002: input,hidraw1: USB HID v1.10 Device [USBKB] on usb-ci_hdrc.0-1.1/input1
    usb 1-1.5: new low-speed USB device number 4 using ci_hdrc
    usb 1-1.5: New USB device found, idVendor=0458, idProduct=003a, bcdDevice= 1.00
    usb 1-1.5: New USB device strings: Mfr=1, Product=2, SerialNumber=0
    usb 1-1.5: Product: Optical Mouse
    usb 1-1.5: Manufacturer: Genius
    input: Genius Optical Mouse as /devices/soc0/axi/e0002000.usb/ci_hdrc.0/usb1/1-1/1-1.5/1-1.5:1.0/0003:0458:003A.0003/input/input3
    hid-generic 0003:0458:003A.0003: input,hidraw2: USB HID v1.11 Mouse [Genius Optical Mouse] on usb-ci_hdrc.0-1.5/input0
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_setup -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_setup -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_setup -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage1 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage1 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage1 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage2 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage2 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage2 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage3 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage3 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage3 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage4 -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage4 -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage4 -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage5 -> clocks_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage5 -> clocks_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage5 -> clocks_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clocks_enable -> link_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clocks_enable -> link_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clocks_enable -> link_enable
    axi-jesd204-rx 44aa0000.axi-jesd204-rx: axi_jesd204_rx_jesd204_link_running: Link1 status failed (CGS)
    jesd204: /fpga-axi@0/axi-jesd204-rx@44aa0000,jesd204:3,parent=44aa0000.axi-jesd204-rx: JESD204[1] In link_running got error from cb: -1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: Rolling back from 'link_enable', got error -1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_enable -> link_running
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_enable -> link_running
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_enable -> link_running
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_running -> link_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_running -> link_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_running -> link_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_enable -> clocks_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_enable -> clocks_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_enable -> clocks_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clocks_enable -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clocks_enable -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clocks_enable -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage5 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage5 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage5 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage4 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage4 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage4 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage3 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage3 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage3 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage2 -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage2 -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage2 -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage1 -> link_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage1 -> link_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage1 -> link_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_setup -> clk_sync_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_setup -> clk_sync_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_setup -> clk_sync_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage3 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage3 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage3 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage2 -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage2 -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage2 -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage1 -> link_pre_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage1 -> link_pre_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage1 -> link_pre_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_pre_setup -> link_supported
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_pre_setup -> link_supported
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_pre_setup -> link_supported
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_supported -> link_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_supported -> link_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_supported -> link_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_init -> device_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_init -> device_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_init -> device_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition device_init -> idle
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition device_init -> idle
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition device_init -> idle
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition idle -> idle
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition idle -> idle
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition idle -> idle
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition idle -> device_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition idle -> device_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition idle -> device_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition device_init -> link_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition device_init -> link_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition device_init -> link_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_init -> link_supported
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_init -> link_supported
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_init -> link_supported
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_supported -> link_pre_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_supported -> link_pre_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_supported -> link_pre_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_pre_setup -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_pre_setup -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_pre_setup -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage1 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage1 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage1 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage2 -> clk_sync_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage2 -> clk_sync_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage2 -> clk_sync_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage3 -> link_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage3 -> link_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage3 -> link_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_setup -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_setup -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_setup -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage1 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage1 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage1 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage2 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage2 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage2 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage3 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage3 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage3 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage4 -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage4 -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage4 -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage5 -> clocks_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage5 -> clocks_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage5 -> clocks_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clocks_enable -> link_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clocks_enable -> link_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clocks_enable -> link_enable
    axi-jesd204-rx 44aa0000.axi-jesd204-rx: axi_jesd204_rx_jesd204_link_running: Link1 status failed (CGS)
    jesd204: /fpga-axi@0/axi-jesd204-rx@44aa0000,jesd204:3,parent=44aa0000.axi-jesd204-rx: JESD204[1] In link_running got error from cb: -1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: Rolling back from 'link_enable', got error -1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_enable -> link_running
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_enable -> link_running
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_enable -> link_running
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_running -> link_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_running -> link_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_running -> link_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_enable -> clocks_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_enable -> clocks_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_enable -> clocks_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clocks_enable -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clocks_enable -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clocks_enable -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage5 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage5 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage5 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage4 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage4 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage4 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage3 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage3 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage3 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage2 -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage2 -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage2 -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage1 -> link_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage1 -> link_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage1 -> link_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_setup -> clk_sync_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_setup -> clk_sync_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_setup -> clk_sync_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage3 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage3 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage3 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage2 -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage2 -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage2 -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage1 -> link_pre_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage1 -> link_pre_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage1 -> link_pre_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_pre_setup -> link_supported
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_pre_setup -> link_supported
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_pre_setup -> link_supported
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_supported -> link_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_supported -> link_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_supported -> link_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_init -> device_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_init -> device_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_init -> device_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition device_init -> idle
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition device_init -> idle
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition device_init -> idle
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition idle -> idle
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition idle -> idle
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition idle -> idle
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition idle -> device_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition idle -> device_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition idle -> device_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition device_init -> link_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition device_init -> link_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition device_init -> link_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_init -> link_supported
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_init -> link_supported
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_init -> link_supported
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_supported -> link_pre_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_supported -> link_pre_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_supported -> link_pre_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_pre_setup -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_pre_setup -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_pre_setup -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage1 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage1 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage1 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage2 -> clk_sync_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage2 -> clk_sync_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage2 -> clk_sync_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage3 -> link_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage3 -> link_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage3 -> link_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_setup -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_setup -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_setup -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage1 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage1 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage1 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage2 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage2 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage2 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage3 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage3 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage3 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage4 -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage4 -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage4 -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage5 -> clocks_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage5 -> clocks_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage5 -> clocks_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clocks_enable -> link_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clocks_enable -> link_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clocks_enable -> link_enable
    axi-jesd204-rx 44aa0000.axi-jesd204-rx: axi_jesd204_rx_jesd204_link_running: Link1 status failed (CGS)
    jesd204: /fpga-axi@0/axi-jesd204-rx@44aa0000,jesd204:3,parent=44aa0000.axi-jesd204-rx: JESD204[1] In link_running got error from cb: -1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: Rolling back from 'link_enable', got error -1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_enable -> link_running
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_enable -> link_running
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_enable -> link_running
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_running -> link_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_running -> link_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_running -> link_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_enable -> clocks_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_enable -> clocks_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_enable -> clocks_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clocks_enable -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clocks_enable -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clocks_enable -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage5 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage5 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage5 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage4 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage4 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage4 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage3 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage3 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage3 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage2 -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage2 -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage2 -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage1 -> link_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage1 -> link_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage1 -> link_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_setup -> clk_sync_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_setup -> clk_sync_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_setup -> clk_sync_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage3 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage3 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage3 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage2 -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage2 -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage2 -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage1 -> link_pre_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage1 -> link_pre_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage1 -> link_pre_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_pre_setup -> link_supported
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_pre_setup -> link_supported
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_pre_setup -> link_supported
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_supported -> link_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_supported -> link_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_supported -> link_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_init -> device_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_init -> device_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_init -> device_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition device_init -> idle
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition device_init -> idle
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition device_init -> idle
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition idle -> idle
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition idle -> idle
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition idle -> idle
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition idle -> device_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition idle -> device_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition idle -> device_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition device_init -> link_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition device_init -> link_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition device_init -> link_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_init -> link_supported
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_init -> link_supported
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_init -> link_supported
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_supported -> link_pre_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_supported -> link_pre_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_supported -> link_pre_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_pre_setup -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_pre_setup -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_pre_setup -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage1 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage1 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage1 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage2 -> clk_sync_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage2 -> clk_sync_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage2 -> clk_sync_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage3 -> link_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage3 -> link_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage3 -> link_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_setup -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_setup -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_setup -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage1 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage1 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage1 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage2 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage2 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage2 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage3 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage3 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage3 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage4 -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage4 -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage4 -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage5 -> clocks_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage5 -> clocks_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage5 -> clocks_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clocks_enable -> link_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clocks_enable -> link_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clocks_enable -> link_enable
    axi-jesd204-rx 44aa0000.axi-jesd204-rx: axi_jesd204_rx_jesd204_link_running: Link1 status failed (CGS)
    jesd204: /fpga-axi@0/axi-jesd204-rx@44aa0000,jesd204:3,parent=44aa0000.axi-jesd204-rx: JESD204[1] In link_running got error from cb: -1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: Rolling back from 'link_enable', got error -1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_enable -> link_running
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_enable -> link_running
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_enable -> link_running
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_running -> link_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_running -> link_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_running -> link_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_enable -> clocks_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_enable -> clocks_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_enable -> clocks_enable
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clocks_enable -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clocks_enable -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clocks_enable -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage5 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage5 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage5 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage4 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage4 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage4 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage3 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage3 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage3 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage2 -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage2 -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage2 -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage1 -> link_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage1 -> link_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage1 -> link_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_setup -> clk_sync_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_setup -> clk_sync_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_setup -> clk_sync_stage3
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage3 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage3 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage3 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage2 -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage2 -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage2 -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage1 -> link_pre_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage1 -> link_pre_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage1 -> link_pre_setup
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_pre_setup -> link_supported
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_pre_setup -> link_supported
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_pre_setup -> link_supported
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_supported -> link_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_supported -> link_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_supported -> link_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_init -> device_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_init -> device_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_init -> device_init
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition device_init -> idle
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition device_init -> idle
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition device_init -> idle
    jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: FSM completed with error -1
    axi-jesd204-tx 44a90000.axi-jesd204-tx: AXI-JESD204-TX (1.06.a) at 0x44A90000. Encoder 8b10b, width 4/4, lanes 4, jesd204-fsm.
    cf_axi_adc 44a00000.axi-ad9371-rx-hpc: ADI AIM (10.01.b) at 0x44A00000 mapped to 0x53fb5434, probed ADC AD9371 as MASTER
    input: gpio_keys as /devices/soc0/gpio_keys/input/input4
    ALSA device list:
    #0: HDMI monitor
    EXT4-fs (mmcblk0p2): recovery complete
    EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
    VFS: Mounted root (ext4 filesystem) on device 179:2.
    devtmpfs: mounted
    Freeing unused kernel memory: 1024K
    Run /sbin/init as init process
    Mount failed for selinuxfs on /sys/fs/selinux: No such file or directory
    * Setting up X socket directories... [ OK ]
    * STARTDISTCC is set to false in /etc/default/distcc
    * /usr/bin/distccd not starting
    * Starting IIO Daemon iiod [ OK ]

    Last login: Fri Feb 11 05:23:48 UTC 2022 on tty1
    Welcome to Linaro 14.04 (GNU/Linux 5.10.0-19263-g782606bd4fcf-dirty armv7l)

    * Documentation: https://wiki.analog.com/ https://ez.analog.com/

    root@analog:~#

  • Can you check your ZC706 power supply, awhile ago I used one that shipped with a ZC702 and I also had strange JESD errors.

    Your link stays in CGS, or occasionally moves to DATA but then moves back to CGS due to lane errors.

    This is unexpected and with the latest files I can't replicate on my end.

    Actually the none jesd204-fsm did work for me, only FSM caused error due to the different link bring up sequence and the way the reference of the MMCM were connected in the FPGA design.

    The lanes look perfect on my end.

     There are a few things you can try:

    Remove the adi,use-lpm-enable; attribute from the adxcvr devicetree nodes.

    This will then use DFE instead of LPM mode.

    The AD9175 has some Framer configuration options for PRE Emphasis and Serializer Amplitude, you can alter them in OSC or finally in the devicetree.

     

    -Michael

Reply
  • Can you check your ZC706 power supply, awhile ago I used one that shipped with a ZC702 and I also had strange JESD errors.

    Your link stays in CGS, or occasionally moves to DATA but then moves back to CGS due to lane errors.

    This is unexpected and with the latest files I can't replicate on my end.

    Actually the none jesd204-fsm did work for me, only FSM caused error due to the different link bring up sequence and the way the reference of the MMCM were connected in the FPGA design.

    The lanes look perfect on my end.

     There are a few things you can try:

    Remove the adi,use-lpm-enable; attribute from the adxcvr devicetree nodes.

    This will then use DFE instead of LPM mode.

    The AD9175 has some Framer configuration options for PRE Emphasis and Serializer Amplitude, you can alter them in OSC or finally in the devicetree.

     

    -Michael

Children
  • I replaced the zc 706 together with the original power supply with the second set, I didn’t notice any changes, I assumed that there might be problems with the adrv 9375 W board itself, but the most interesting thing is that it comes with a Windows Based TES NOV 2016 rev 2.0 sd card, and with it I receive a signal from the generator without errors

  • Is it possible to say that if the GUI windows AD 9375 works and receives a signal without errors, then there are no hardware problems?

  • I think it's a fair assumption that the HW should work.

    However the TES GUI uses different bitstreams for each mode. With optimized GTX settings such as CDR.

    In the meantime we tested on another ZC706 and we also didn't run into any issues with that.

    Sometime the OSC autostart can cause issues, since it reloads previous (maybe erroneous) settings. Can you please delete following files on your SD card image.

    This will make sure OSC starts clean:  

    root@analog:~# rm /home/analog/.osc_profile.ini 
    root@analog:~# rm /root/.osc_profile.ini 

    Can you also check your AD9528 lock status using this command?

    root@analog:~# iio_attr -d ad9528-1
    dev 'ad9528-1', attr 'pll1_feedback_clk_present', value :'1'
    dev 'ad9528-1', attr 'pll1_locked', value :'1'
    dev 'ad9528-1', attr 'pll1_reference_clk_a_present', value :'1'
    dev 'ad9528-1', attr 'pll1_reference_clk_ab_missing', value :'0'
    dev 'ad9528-1', attr 'pll1_reference_clk_b_present', value :'0'
    dev 'ad9528-1', attr 'pll2_feedback_clk_present', value :'1'
    dev 'ad9528-1', attr 'pll2_locked', value :'1'
    dev 'ad9528-1', attr 'sync_dividers', value :ERROR: Permission denied (13)
    dev 'ad9528-1', attr 'vcxo_clk_present', value :'1'

    -Michael

  • MACsec IEEE 802.1AE
    libphy: Fixed MDIO Bus: probed
    tun: Universal TUN/TAP device driver, 1.6
    libphy: MACB_mii_bus: probed
    Marvell 88E1116R e000b000.ethernet-ffffffff:07: attached PHY driver [Marvell 88E1116R] (mii_bus:phy_addr=e000b000.ethernet-ffffffff:07, irq=POLL)
    macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 28 (00:0a:35:00:01:22)
    usbcore: registered new interface driver asix
    usbcore: registered new interface driver ax88179_178a
    usbcore: registered new interface driver cdc_ether
    usbcore: registered new interface driver net1080
    usbcore: registered new interface driver cdc_subset
    usbcore: registered new interface driver zaurus
    usbcore: registered new interface driver cdc_ncm
    ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
    usbcore: registered new interface driver uas
    usbcore: registered new interface driver usb-storage
    usbcore: registered new interface driver usbserial_generic
    usbserial: USB Serial support registered for generic
    usbcore: registered new interface driver ftdi_sio
    usbserial: USB Serial support registered for FTDI USB Serial Device
    usbcore: registered new interface driver upd78f0730
    usbserial: USB Serial support registered for upd78f0730
    chipidea-usb2 e0002000.usb: e0002000.usb supply vbus not found, using dummy regulator
    chipidea-usb2 e0002000.usb: Linked as a consumer to regulator.0
    ULPI transceiver vendor/product ID 0x0424/0x0007
    Found SMSC USB3320 ULPI transceiver.
    ULPI integrity check: passed.
    ci_hdrc ci_hdrc.0: EHCI Host Controller
    ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1
    ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00
    usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 4.19
    usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
    usb usb1: Product: EHCI Host Controller
    usb usb1: Manufacturer: Linux 4.19.0-g17f4223 ehci_hcd
    usb usb1: SerialNumber: ci_hdrc.0
    hub 1-0:1.0: USB hub found
    hub 1-0:1.0: 1 port detected
    i2c /dev entries driver
    si570 1-005d: registered, current frequency 156250000 Hz
    i2c i2c-0: Added multiplexed i2c bus 1
    adv7511 2-0039: 2-0039 supply avdd not found, using dummy regulator
    adv7511 2-0039: Linked as a consumer to regulator.0
    adv7511 2-0039: 2-0039 supply dvdd not found, using dummy regulator
    adv7511 2-0039: 2-0039 supply pvdd not found, using dummy regulator
    adv7511 2-0039: 2-0039 supply bgvdd not found, using dummy regulator
    adv7511 2-0039: 2-0039 supply dvdd-3v not found, using dummy regulator
    i2c i2c-0: Added multiplexed i2c bus 2
    at24 3-0054: 1024 byte 24c08 EEPROM, writable, 1 bytes/write
    i2c i2c-0: Added multiplexed i2c bus 3
    pca953x 4-0021: 4-0021 supply vcc not found, using dummy regulator
    pca953x 4-0021: Linked as a consumer to regulator.0
    i2c i2c-0: Added multiplexed i2c bus 4
    rtc-pcf8563 5-0051: rtc core: registered rtc-pcf8563 as rtc0
    i2c i2c-0: Added multiplexed i2c bus 5
    at24 6-0050: 256 byte 24c02 EEPROM, writable, 1 bytes/write
    i2c i2c-0: Added multiplexed i2c bus 6
    i2c i2c-0: Added multiplexed i2c bus 7
    i2c i2c-0: Added multiplexed i2c bus 8
    pca954x 0-0074: registered 8 multiplexed busses for I2C switch pca9548
    usbcore: registered new interface driver uvcvideo
    USB Video Class driver (1.1.1)
    gspca_main: v2.14.0 registered
    cdns-wdt f8005000.watchdog: Xilinx Watchdog Timer with timeout 10s
    Xilinx Zynq CpuIdle Driver started
    failed to register cpuidle driver
    sdhci: Secure Digital Host Controller Interface driver
    sdhci: Copyright(c) Pierre Ossman
    sdhci-pltfm: SDHCI platform and OF driver helper
    mmc0: SDHCI controller on e0100000.mmc [e0100000.mmc] using ADMA
    ledtrig-cpu: registered to indicate activity on CPUs
    hidraw: raw HID events driver (C) Jiri Kosina
    usbcore: registered new interface driver usbhid
    usbhid: USB HID core driver
    ad9371 spi0.1: ad9371_probe : enter
    ad9528 spi0.0: spi0.0 supply vcc not found, using dummy regulator
    ad9528 spi0.0: Linked as a consumer to regulator.0
    mmc0: new high speed SDHC card at address aaaa
    mmcblk0: mmc0:aaaa SC16G 14.8 GiB
    mmcblk0: p1 p2 p3
    random: fast init done
    axi_sysid 45000000.axi-sysid-0: [adrv9371x] on [zc706] git <43c6ae1ca9faf268f30c7ef489f1428fc30a8b23> clean [2021-06-09 22:31:32] UTC
    fpga_manager fpga0: Xilinx Zynq FPGA Manager registered
    usbcore: registered new interface driver snd-usb-audio
    NET: Registered protocol family 10
    Segment Routing with IPv6
    usb 1-1: new high-speed USB device number 2 using ci_hdrc
    sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
    NET: Registered protocol family 17
    NET: Registered protocol family 36
    Registering SWP/SWPB emulation handler
    usb 1-1: New USB device found, idVendor=1a40, idProduct=0201, bcdDevice= 1.00
    usb 1-1: New USB device strings: Mfr=0, Product=1, SerialNumber=0
    usb 1-1: Product: USB 2.0 Hub [MTT]
    hub 1-1:1.0: USB hub found
    hub 1-1:1.0: 7 ports detected
    Console: switching to colour frame buffer device 240x67
    axi-hdmi 70e00000.axi_hdmi: fb0: DRM emulated frame buffer device
    [drm] Initialized axi_hdmi_drm 1.0.0 20120930 for 70e00000.axi_hdmi on minor 0
    ad9371 spi0.1: ad9371_probe : enter
    axi_adxcvr 44a60000.axi-adxcvr-rx: AXI-ADXCVR-RX (17.01.a) using CPLL on GTX2 at 0x44A60000. Number of lanes: 2.
    axi_adxcvr 44a50000.axi-adxcvr-rx-os: AXI-ADXCVR-RX (17.01.a) using CPLL on GTX2 at 0x44A50000. Number of lanes: 2.
    axi_adxcvr 44a80000.axi-adxcvr-tx: AXI-ADXCVR-TX (17.01.a) using QPLL on GTX2 at 0x44A80000. Number of lanes: 4.
    asoc-simple-card adv7511_hdmi_snd: spdif-hifi <-> 75c00000.axi-spdif-tx mapping ok
    ad9371 spi0.1: ad9371_probe : enter
    usb 1-1.1: new low-speed USB device number 3 using ci_hdrc
    usb 1-1.1: New USB device found, idVendor=2a7a, idProduct=2eb2, bcdDevice= 0.01
    usb 1-1.1: New USB device strings: Mfr=0, Product=2, SerialNumber=0
    usb 1-1.1: Product: USBKB
    input: USBKB as /devices/soc0/amba/e0002000.usb/ci_hdrc.0/usb1/1-1/1-1.1/1-1.1:1.0/0003:2A7A:2EB2.0001/input/input0
    hid-generic 0003:2A7A:2EB2.0001: input,hidraw0: USB HID v1.10 Keyboard [USBKB] on usb-ci_hdrc.0-1.1/input0
    input: USBKB Consumer Control as /devices/soc0/amba/e0002000.usb/ci_hdrc.0/usb1/1-1/1-1.1/1-1.1:1.1/0003:2A7A:2EB2.0002/input/input1
    input: USBKB System Control as /devices/soc0/amba/e0002000.usb/ci_hdrc.0/usb1/1-1/1-1.1/1-1.1:1.1/0003:2A7A:2EB2.0002/input/input2
    hid-generic 0003:2A7A:2EB2.0002: input,hidraw1: USB HID v1.10 Device [USBKB] on usb-ci_hdrc.0-1.1/input1
    usb 1-1.5: new low-speed USB device number 4 using ci_hdrc
    usb 1-1.5: New USB device found, idVendor=0458, idProduct=003a, bcdDevice= 1.00
    usb 1-1.5: New USB device strings: Mfr=1, Product=2, SerialNumber=0
    usb 1-1.5: Product: Optical Mouse
    usb 1-1.5: Manufacturer: Genius
    input: Genius Optical Mouse as /devices/soc0/amba/e0002000.usb/ci_hdrc.0/usb1/1-1/1-1.5/1-1.5:1.0/0003:0458:003A.0003/input/input3
    hid-generic 0003:0458:003A.0003: input,hidraw2: USB HID v1.11 Mouse [Genius Optical Mouse] on usb-ci_hdrc.0-1.5/input0
    ad9371 spi0.1: obsFramerStatus (0x20)
    ad9371 spi0.1: AD9375 Rev 4, Firmware 5.2.2 API version: 1.5.2.3566 successfully initialized
    cf_axi_dds 44a04000.axi-ad9371-tx-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x44A04000 mapped to 0x(ptrval), probed DDS AD9371
    cf_axi_adc 44a00000.axi-ad9371-rx-hpc: ADI AIM (10.01.b) at 0x44A00000 mapped to 0x(ptrval), probed ADC AD9371 as MASTER
    input: gpio_keys as /devices/soc0/gpio_keys/input/input4
    rtc-pcf8563 5-0051: setting system clock to 2022-02-14 10:12:45 UTC (1644833565)
    clk: Not disabling unused clocks
    ALSA device list:
    #0: HDMI monitor
    EXT4-fs (mmcblk0p2): recovery complete
    EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
    VFS: Mounted root (ext4 filesystem) on device 179:2.
    devtmpfs: mounted
    Freeing unused kernel memory: 1024K
    Run /sbin/init as init process
    systemd[1]: Failed to lookup module alias 'autofs4': Function not implemented
    systemd[1]: systemd 241 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD -IDN2 +IDN -PCRE2 default-hierarchy=hybrid)
    systemd[1]: Detected architecture arm.

    Welcome to Kuiper GNU/Linux 10 (buster)!

    systemd[1]: Set hostname to <analog>.
    systemd[1]: File /lib/systemd/system/systemd-journald.service:12 configures an IP firewall (IPAddressDeny=any), but the local system does not support BPF/cgroup based firewalling.
    systemd[1]: Proceeding WITHOUT firewalling in effect! (This warning is only shown for the first loaded unit using IP firewalling.)
    systemd[1]: /etc/systemd/system/tof-server.service:1: Assignment outside of section. Ignoring.
    systemd[1]: /etc/systemd/system/tof-server.service:2: Assignment outside of section. Ignoring.
    random: systemd: uninitialized urandom read (16 bytes read)
    random: systemd: uninitialized urandom read (16 bytes read)
    systemd[1]: Listening on udev Kernel Socket.
    [ OK ] Listening on udev Kernel Socket.
    random: systemd: uninitialized urandom read (16 bytes read)
    systemd[1]: Reached target Swap.
    [ OK ] Reached target Swap.
    systemd[1]: Listening on initctl Compatibility Named Pipe.
    [ OK ] Listening on initctl Compatibility Named Pipe.
    [ OK ] Created slice system-getty.slice.
    [ OK ] Listening on Syslog Socket.
    [ OK ] Started Forward Password R…uests to Wall Directory Watch.
    [ OK ] Created slice User and Session Slice.
    [ OK ] Listening on Journal Socket (/dev/log).
    [ OK ] Listening on udev Control Socket.
    [ OK ] Created slice system-serial\x2dgetty.slice.
    [ OK ] Reached target Slices.
    [ OK ] Listening on Journal Socket.
    Starting udev Coldplug all Devices...
    Mounting Kernel Debug File System...
    Starting Load Kernel Modules...
    Starting Restore / save the current clock...
    Mounting RPC Pipe File System...
    Starting Journal Service...
    [ OK ] Created slice system-systemd\x2dfsck.slice.
    Starting Set the console keyboard layout...
    [ OK ] Listening on fsck to fsckd communication Socket.
    [ OK ] Mounted Kernel Debug File System.
    [FAILED] Failed to start Load Kernel Modules.
    See 'systemctl status systemd-modules-load.service' for details.
    [ OK ] Started Restore / save the current clock.
    [FAILED] Failed to mount RPC Pipe File System.
    See 'systemctl status run-rpc_pipefs.mount' for details.
    [DEPEND] Dependency failed for RPC …ice for NFS client and server.
    [DEPEND] Dependency failed for RPC …curity service for NFS server.
    [ OK ] Started Journal Service.
    [ OK ] Reached target NFS client services.
    [ OK ] Reached target Remote File Systems (Pre).
    [ OK ] Reached target Remote File Systems.
    Starting Remount Root and Kernel File Systems...
    Mounting Kernel Configuration File System...
    Starting Apply Kernel Variables...
    [ OK ] Mounted Kernel Configuration File System.
    [ OK ] Started udev Coldplug all Devices.
    [ OK ] Started Apply Kernel Variables.
    [ OK ] Started Set the console keyboard layout.
    Starting Helper to synchronize boot up for ifupdown...
    [ OK ] Started Helper to synchronize boot up for ifupdown.
    [ OK ] Started Remount Root and Kernel File Systems.
    Starting Flush Journal to Persistent Storage...
    Starting Create System Users...
    Starting Load/Save Random Seed...
    [ OK ] Started Load/Save Random Seed.
    [ OK ] Started Flush Journal to Persistent Storage.
    [ OK ] Started Create System Users.
    Starting Create Static Device Nodes in /dev...
    [ OK ] Started Create Static Device Nodes in /dev.
    [ OK ] Reached target Local File Systems (Pre).
    Starting udev Kernel Device Manager...
    [ OK ] Started udev Kernel Device Manager.
    Starting Show Plymouth Boot Screen...
    [ OK ] Started Show Plymouth Boot Screen.
    [ OK ] Reached target Local Encrypted Volumes.
    [ OK ] Started Forward Password R…s to Plymouth Directory Watch.
    [ OK ] Found device /dev/ttyPS0.
    Starting Load Kernel Modules...
    [FAILED] Failed to start Load Kernel Modules.
    See 'systemctl status systemd-modules-load.service' for details.
    [ OK ] Found device /dev/disk/by-partuuid/004ba301-01.
    Starting File System Check…isk/by-partuuid/004ba301-01...
    [ OK ] Started File System Check Daemon to report status.
    [ OK ] Started File System Check …/disk/by-partuuid/004ba301-01.
    Mounting /boot...
    [ OK ] Mounted /boot.
    [ OK ] Reached target Local File Systems.
    Starting Preprocess NFS configuration...
    Starting Raise network interfaces...
    Starting Tell Plymouth To Write Out Runtime Data...
    Starting Set console font and keymap...
    Starting Create Volatile Files and Directories...
    [ OK ] Started Preprocess NFS configuration.
    [ OK ] Started Tell Plymouth To Write Out Runtime Data.
    [ OK ] Started Set console font and keymap.
    [ OK ] Started Create Volatile Files and Directories.
    Starting Network Time Synchronization...
    Starting Update UTMP about System Boot/Shutdown...
    [ OK ] Started Update UTMP about System Boot/Shutdown.
    Starting Load Kernel Modules...
    Starting Tell Plymouth To Write Out Runtime Data...
    [ OK ] Started Raise network interfaces.
    [ OK ] Started Tell Plymouth To Write Out Runtime Data.
    [FAILED] Failed to start Load Kernel Modules.
    See 'systemctl status systemd-modules-load.service' for details.
    [ OK ] Started Network Time Synchronization.
    [ OK ] Reached target System Initialization.
    [ OK ] Listening on CUPS Scheduler.
    [ OK ] Started Daily Cleanup of Temporary Directories.
    [ OK ] Listening on D-Bus System Message Bus Socket.
    [ OK ] Listening on triggerhappy.socket.
    [ OK ] Started CUPS Scheduler.
    [ OK ] Reached target Paths.
    [ OK ] Listening on GPS (Global P…ioning System) Daemon Sockets.
    [ OK ] Listening on Avahi mDNS/DNS-SD Stack Activation Socket.
    [ OK ] Reached target Sockets.
    [ OK ] Reached target Basic System.
    Starting rng-tools.service...
    Starting Disk Manager...
    Starting System Logging Service...
    Starting Login Service...
    [ OK ] Started Regular background program processing daemon.
    [ OK ] Started Manage Sound Card State (restore and store).
    [ OK ] Started tof-server.service.
    Starting Avahi mDNS/DNS-SD Stack...
    Starting LSB: Switch to on…nless shift key is pressed)...
    [ OK ] Started D-Bus System Message Bus.
    Starting WPA supplicant...
    Starting triggerhappy global hotkey daemon...
    [ OK ] Started CUPS Scheduler.
    Starting Check for Raspberry Pi EEPROM updates...
    Starting dphys-swapfile - …unt, and delete a swap file...
    Starting Save/Restore Sound Card State...
    Starting dhcpcd on all interfaces...
    Starting Modem Manager...
    [ OK ] Reached target System Time Synchronized.
    [ OK ] Started Daily rotation of log files.
    [ OK ] Started Daily man-db regeneration.
    [ OK ] Started Daily apt download activities.
    [ OK ] Started Daily apt upgrade and clean activities.
    [ OK ] Reached target Timers.
    [ OK ] Started System Logging Service.
    [ OK ] Started triggerhappy global hotkey daemon.
    [FAILED] Failed to start rng-tools.service.
    See 'systemctl status rng-tools.service' for details.
    [ OK ] Started Check for Raspberry Pi EEPROM updates.
    [ OK ] Started Save/Restore Sound Card State.
    [ OK ] Reached target Sound Card.
    [ OK ] Started Login Service.
    [ OK ] Started dhcpcd on all interfaces.
    [ OK ] Started Avahi mDNS/DNS-SD Stack.
    [ OK ] Started WPA supplicant.
    [ OK ] Started Make remote CUPS printers available locally.
    [ OK ] Reached target Network.
    Starting OpenBSD Secure Shell server...
    Starting Permit User Sessions...
    [ OK ] Reached target Network is Online.
    Starting Internet superserver...
    [ OK ] Started IIO Daemon.
    Starting /etc/rc.local Compatibility...
    Starting HTTP based time synchronization tool...
    [ OK ] Started Internet superserver.
    [ OK ] Started /etc/rc.local Compatibility.
    [ OK ] Started dphys-swapfile - s…mount, and delete a swap file.
    [ OK ] Started Permit User Sessions.
    [ OK ] Started HTTP based time synchronization tool.
    Starting Light Display Manager...
    Starting Authorization Manager...
    Starting Hold until boot process finishes up...
    [ OK ] Started OpenBSD Secure Shell server.
    [ OK ] Started Authorization Manager.

    Raspbian GNU/Linux 10 analog ttyPS0

    analog login: root (automatic login)

    Last login: Mon Feb 14 08:43:21 GMT 2022 on ttyPS0
    Linux analog 4.19.0-g17f4223 #1848 SMP PREEMPT Tue Jul 27 12:46:50 IST 2021 armv7l

    The programs included with the Debian GNU/Linux system are free software;
    the exact distribution terms for each program are described in the
    individual files in /usr/share/doc/*/copyright.

    Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
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    root@analog:~# iio_attr -d ad9528-1
    dev 'ad9528-1', attr 'pll1_feedback_clk_present', value :'1'
    dev 'ad9528-1', attr 'pll1_locked', value :'0'
    dev 'ad9528-1', attr 'pll1_reference_clk_a_present', value :'0'
    dev 'ad9528-1', attr 'pll1_reference_clk_ab_missing', value :'1'
    dev 'ad9528-1', attr 'pll1_reference_clk_b_present', value :'0'
    dev 'ad9528-1', attr 'pll2_feedback_clk_present', value :'1'
    dev 'ad9528-1', attr 'pll2_locked', value :'1'
    dev 'ad9528-1', attr 'sync_dividers', value :ERROR: Permission denied (13)
    dev 'ad9528-1', attr 'vcxo_clk_present', value :'1'
    root@analog:~#

    working122_88.tar.gz

  • hello, I re-downloaded and burned img. 2019_2, but did not change the ad9375 profile, everything is stable here, just amazing, I will try to change another profile in this assembly
  • i uploaded the profile, after uploading and it seems to work

  • Hello, I got the impression that when using any profile, besides that, the default is wired in the device tree does not allow for initial initialization.
    I load everything by default, then I select a profile through the IIO GUI and it loads successfully, but if I sew it into the device tree, the initialization fails

  • I can now load the default profile, and then load the one I need and this mechanism works, but I need to change the VCXO to 80 MHz, but I don’t have such a profile that would be guaranteed to load at the beginning, after which I would already load the one that I need needed

  • Can you share your profile and your modified devicetree?

    I guess you're missing something.

    -Michael

  • new_adi_forum_2019_2_vxco80.tar.gz

    i changed <clkPllVcoDiv=1.5> to value 3, this problem was described on the forum that the divisor is set incorrectly