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Bypassing Interpolation and Decimation on Quad MxFE - directly writing to DAC and directly taking ADC samples

Hi there,

I'm working on writing a design tree for the Quad MxFE that bypasses the data paths and channelizers on the transmit and receive paths, writing data directly to the DACs and reading data directly to the ADCs, with no interpolation or decimation, upmixing or downmixing.

This is possible according to the AD9081/AD9082 System Development User Guide (UG-1578), but as far as I know, there isn't an example design provided by Analog for the AD9081 in which this bypass mode of operation is implemented.

As such, I want to check that my approach is correct - the relevant sections of the device tree I have made are below:

// relevant ad9081 device tree definitions

#define ADRF4360_RFAUX8_FREQUENCY_HZ	1500000000

#define HMC7043_FPGA_XCVR_CLKDIV		2
#define HMC7043_FPGA_LINK_CLKDIV_TX		2
#define HMC7043_FPGA_LINK_CLKDIV_RX		2
#define HMC7043_SYSREF_CLKDIV			1024 // Later try setting this to 128 to see if it still works
#define HMC7043_SYSREF_TIMER			(HMC7043_SYSREF_CLKDIV * 4)

#define AD9081_DAC_FREQUENCY			ADRF4360_RFAUX8_FREQUENCY_HZ
#define AD9081_ADC_FREQUENCY			1500000000

 /* TX path */
#define AD9081_TX_LANERATE_KHZ			24750000
#define AD9081_TX_LINK_CLK				375000000

#define AD9081_TX_MAIN_INTERPOLATION		1
#define AD9081_TX_CHAN_INTERPOLATION		1

#ifndef AD9081_TX_MAIN_NCO_SHIFT
#define AD9081_TX_MAIN_NCO_SHIFT		0
#endif
#ifndef AD9081_TX_CHAN_NCO_SHIFT
#define AD9081_TX_CHAN_NCO_SHIFT		0
#endif

#define AD9081_GAIN				1024

#define AD9081_TX_JESD_MODE			11
#define AD9081_TX_JESD_SUBCLASS		1
#define AD9081_TX_JESD_VERSION		2
#define AD9081_TX_JESD_M			4
#define AD9081_TX_JESD_F			2
#define AD9081_TX_JESD_K			128
#define AD9081_TX_JESD_N			16
#define AD9081_TX_JESD_NP			16
#define AD9081_TX_JESD_CS			0
#define AD9081_TX_JESD_L			4
#define AD9081_TX_JESD_S			1
#define AD9081_TX_JESD_HD			0

#define AD9081_JRX_TPL_PHASE_ADJUST		15

/* RX path */
#define AD9081_RX_LANERATE_KHZ			24750000
#define AD9081_RX_LINK_CLK				375000000

#define AD9081_RX_MAIN_DECIMATION		1
#define AD9081_RX_CHAN_DECIMATION		1

#ifndef AD9081_RX_MAIN_NCO_SHIFT
#define AD9081_RX_MAIN_NCO_SHIFT		0
#endif
#ifndef AD9081_RX_CHAN_NCO_SHIFT
#define AD9081_RX_CHAN_NCO_SHIFT		0
#endif

#ifndef AD9081_ADC_NYQUIST_ZONE
#define AD9081_ADC_NYQUIST_ZONE		AD9081_ADC_NYQUIST_ZONE_EVEN
#endif

#define AD9081_RX_JESD_MODE			11
#define AD9081_RX_JESD_SUBCLASS		1
#define AD9081_RX_JESD_VERSION		2
#define AD9081_RX_JESD_M			4
#define AD9081_RX_JESD_F			2
#define AD9081_RX_JESD_K			128
#define AD9081_RX_JESD_N			16
#define AD9081_RX_JESD_NP			16
#define AD9081_RX_JESD_CS			0
#define AD9081_RX_JESD_L			4
#define AD9081_RX_JESD_S			1
#define AD9081_RX_JESD_HD			0

// ad9081 device tree instantiation snippet

&trx0_ad9081 {

	adi,tx-dacs {
		#size-cells = <0>;
		#address-cells = <1>;
		adi,dac-frequency-hz = /bits/ 64 <AD9081_DAC_FREQUENCY>;
		adi,main-data-paths {
			#address-cells = <1>;
			#size-cells = <0>;
			adi,interpolation = <AD9081_TX_MAIN_INTERPOLATION>;
			trx0_ad9081_dac0: dac@0 {
			    reg = <0>;
			    adi,crossbar-select = <&trx0_ad9081_tx_fddc_chan0>;
			    adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_TX_MAIN_NCO_SHIFT>;
			};
			trx0_ad9081_dac1: dac@1 {
			    reg = <1>;
			    adi,crossbar-select = <&trx0_ad9081_tx_fddc_chan1>;
			    adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_TX_MAIN_NCO_SHIFT>;
			};
			trx0_ad9081_dac2: dac@2 {
			    reg = <2>;
			    adi,crossbar-select = <&trx0_ad9081_tx_fddc_chan2>;
			    adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_TX_MAIN_NCO_SHIFT>;
			};
			trx0_ad9081_dac3: dac@3 {
			    reg = <3>;
			    adi,crossbar-select = <&trx0_ad9081_tx_fddc_chan3>;
			    adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_TX_MAIN_NCO_SHIFT>;
			};
		};
		adi,channelizer-paths {
			#address-cells = <1>;
			#size-cells = <0>;
			adi,interpolation = <AD9081_TX_CHAN_INTERPOLATION>;
			trx0_ad9081_tx_fddc_chan0: channel@0 {
			    reg = <0>;
			    adi,gain = <AD9081_GAIN>; /* value * 10^(gain_dB/20) */
			    adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_TX_CHAN_NCO_SHIFT>;
			};
			trx0_ad9081_tx_fddc_chan1: channel@1 {
			    reg = <1>;
			    adi,gain = <AD9081_GAIN>; /* value * 10^(gain_dB/20) */
			    adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_TX_CHAN_NCO_SHIFT>;
			};
			trx0_ad9081_tx_fddc_chan2: channel@2 {
			    reg = <2>;
			    adi,gain = <AD9081_GAIN>; /* value * 10^(gain_dB/20) */
			    adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_TX_CHAN_NCO_SHIFT>;
			};
			trx0_ad9081_tx_fddc_chan3: channel@3 {
			    reg = <3>;
			    adi,gain = <AD9081_GAIN>; /* value * 10^(gain_dB/20) */
			    adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_TX_CHAN_NCO_SHIFT>;
			};
		};

		adi,jesd-links {
			#size-cells = <0>;
			#address-cells = <1>;
			trx0_ad9081_tx_jesd_l0: link@0 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0>;
				adi,tpl-phase-adjust = <AD9081_JRX_TPL_PHASE_ADJUST>;
				adi,logical-lane-mapping = /bits/ 8 <0 1 2 3 4 5 6 7>;
				adi,link-mode = <AD9081_TX_JESD_MODE>;			/* JESD Quick Configuration Mode */
				adi,subclass = <AD9081_TX_JESD_SUBCLASS>;			/* JESD SUBCLASS 0,1,2 */
				adi,version = <AD9081_TX_JESD_VERSION>;			/* JESD VERSION 0=204A,1=204B,2=204C */
				adi,dual-link = <0>;			/* JESD Dual Link Mode */
				adi,converters-per-device = <AD9081_TX_JESD_M>;	/* JESD M */
				adi,octets-per-frame = <AD9081_TX_JESD_F>;		/* JESD F */
				adi,frames-per-multiframe = <AD9081_TX_JESD_K>;	/* JESD K */
				adi,converter-resolution = <AD9081_TX_JESD_N>;	/* JESD N */
				adi,bits-per-sample = <AD9081_TX_JESD_N>;		/* JESD NP' */
				adi,control-bits-per-sample = <AD9081_TX_JESD_CS>;	/* JESD CS */
				adi,lanes-per-device = <AD9081_TX_JESD_L>;		/* JESD L */
				adi,samples-per-converter-per-frame = <AD9081_TX_JESD_S>; /* JESD S */
				adi,high-density = <AD9081_TX_JESD_HD>;			/* JESD HD */
			};
		};
	};

	adi,rx-adcs {
		#size-cells = <0>;
		#address-cells = <1>;
		adi,adc-frequency-hz = /bits/ 64 <AD9081_ADC_FREQUENCY>;
		adi,nyquist-zone = <AD9081_ADC_NYQUIST_ZONE>;
		adi,main-data-paths {
			#address-cells = <1>;
			#size-cells = <0>;
			trx0_ad9081_adc0: adc@0 {
				reg = <0>;
				adi,decimation = <AD9081_RX_MAIN_DECIMATION>;
				adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_RX_MAIN_NCO_SHIFT>;
				adi,nco-mixer-mode = <AD9081_ADC_NCO_ZIF>; /* NCO off, no mixing */
				//adi,crossbar-select = <&trx0_ad9081_rx_fddc_chan0>; /* Statically assigned */
			};
			trx0_ad9081_adc1: adc@1 {
				reg = <1>;
				adi,decimation = <AD9081_RX_MAIN_DECIMATION>;
				adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_RX_MAIN_NCO_SHIFT>;
				adi,nco-mixer-mode = <AD9081_ADC_NCO_ZIF>; /* NCO off, no mixing */
				//adi,crossbar-select = <&trx0_ad9081_rx_fddc_chan1>; /* Statically assigned */
			};
			trx0_ad9081_adc2: adc@2 {
				reg = <2>;
				adi,decimation = <AD9081_RX_MAIN_DECIMATION>;
				adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_RX_MAIN_NCO_SHIFT>;
				adi,nco-mixer-mode = <AD9081_ADC_NCO_ZIF>; /* NCO off, no mixing */
				//adi,crossbar-select = <&trx0_ad9081_rx_fddc_chan4>; /* Statically assigned */
			};
			trx0_ad9081_adc3: adc@3 {
				reg = <3>;
				adi,decimation = <AD9081_RX_MAIN_DECIMATION>;
				adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_RX_MAIN_NCO_SHIFT>;
				adi,nco-mixer-mode = <AD9081_ADC_NCO_ZIF>; /* NCO off, no mixing */
				//adi,crossbar-select = <&trx0_ad9081_rx_fddc_chan5>; /* Statically assigned */
			};
		};
		adi,channelizer-paths {
			#address-cells = <1>;
			#size-cells = <0>;
			trx0_ad9081_rx_fddc_chan0: channel@0 {
				reg = <0>;
				adi,decimation = <AD9081_RX_CHAN_DECIMATION>;
				adi,digital-gain-6db-enable = <0>;
				adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_RX_CHAN_NCO_SHIFT>;
			};
			trx0_ad9081_rx_fddc_chan1: channel@1 {
				reg = <1>;
				adi,decimation = <AD9081_RX_CHAN_DECIMATION>;
				adi,digital-gain-6db-enable = <0>;
				adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_RX_CHAN_NCO_SHIFT>;
			};
			trx0_ad9081_rx_fddc_chan4: channel@4 {
				reg = <4>;
				adi,decimation = <AD9081_RX_CHAN_DECIMATION>;
				adi,digital-gain-6db-enable = <0>;
				adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_RX_CHAN_NCO_SHIFT>;
			};
			trx0_ad9081_rx_fddc_chan5: channel@5 {
				reg = <5>;
				adi,decimation = <AD9081_RX_CHAN_DECIMATION>;
				adi,digital-gain-6db-enable = <0>;
				adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_RX_CHAN_NCO_SHIFT>;
			};
		};
		adi,jesd-links {
			#size-cells = <0>;
			#address-cells = <1>;
			trx0_ad9081_rx_jesd_l0: link@0 {
				reg = <0>;
				adi,converter-select =
					<&trx0_ad9081_rx_fddc_chan0 FDDC_I>, <&trx0_ad9081_rx_fddc_chan1 FDDC_I>,
					<&trx0_ad9081_rx_fddc_chan4 FDDC_I>, <&trx0_ad9081_rx_fddc_chan5 FDDC_I>;
				adi,logical-lane-mapping = /bits/ 8 <0 1 2 3 4 5 6 7>;
				adi,link-mode = <AD9081_RX_JESD_MODE>;			/* JESD Quick Configuration Mode */
				adi,subclass = <AD9081_RX_JESD_SUBCLASS>;			/* JESD SUBCLASS 0,1,2 */
				adi,version = <AD9081_RX_JESD_VERSION>;			/* JESD VERSION 0=204A,1=204B,2=204C */
				adi,dual-link = <0>;			/* JESD Dual Link Mode */
				adi,device-id = <3>;
				adi,converters-per-device = <AD9081_RX_JESD_M>;	/* JESD M */
				adi,octets-per-frame = <AD9081_RX_JESD_F>;		/* JESD F */
				adi,frames-per-multiframe = <AD9081_RX_JESD_K>;	/* JESD K */
				adi,converter-resolution = <AD9081_RX_JESD_N>;	/* JESD N */
				adi,bits-per-sample = <AD9081_RX_JESD_NP>;		/* JESD NP' */
				adi,control-bits-per-sample = <AD9081_RX_JESD_CS>;	/* JESD CS */
				adi,lanes-per-device = <AD9081_RX_JESD_L>;		/* JESD L */
				adi,samples-per-converter-per-frame = <AD9081_RX_JESD_S>; /* JESD S */
				adi,high-density = <AD9081_RX_JESD_HD>;			/* JESD HD */
			};
		};
	};
};

The main differences from the Analog example designs are as follows:

I have set AD9081_TX_MAIN_INTERPOLATION and AD9081_TX_CHAN_INTERPOLATION to 1. According to the AD9081/AD9082 software development guide, this should result in the virtual converters being mapped 1-to-1 directly to the DACs.

In main-data-paths, under tx-dacs, I have instantiated four data paths (normally this would be two for a design with upmixing and my JESD parameters).

In channelizer-paths, under tx-dacs, I have instantiated four channelizer paths (normally this would be two for a design with upmixing and my JESD parameters).

jesd-links, under tx-dacs, is as it normally would be.

I have set AD9081_RX_MAIN_DECIMATION and AD9081_RX_CHAN_DECIMATION to 1. According to the AD9081 software development guide, this doesn't result in bypass operation unlike for the DACs, but it does stop decimation from occurring.

In main-data-paths, under rx-adcs, I have instantiated four data paths (as normal for M=4), but I have set nco-mixer-mode to AD9081_ADC_NCO_ZIF to turn off downmixing.

In channelizer-paths, under rx-adcs, I have instantiated four channelizer paths (as normal for M=4, with ADC 2 mapping to Channel 4 and ADC 3 mapping to Channel 5 as done in other example designs).

jesd-links, under rx-adcs, is configured to select only the FDDC_I parts of the channelizers, rather than FDDC_I and FDDC_Q as would be used in a design with downmixing.

Was this the right approach?

Many thanks,
Kari

(Note 1, the nco-mode variable that appears in Analog device trees defining this doesn't appear in the C file that reads the device tree - I believe this may be an mistake and an update of the variable name from nco-mode to nco-mixer-mode in the device tree example files may have been forgotten.

Note 2, I have also changed the clocking to use the RFAUX8 output of the ADRF4360 and the selected output of the ADRF5020 as the DAC clock input frequency is <8 GHz, but I haven't discussed these changes above because I have high confidence that they will work)



Added additional notes
[edited by: Salisen at 1:13 PM (GMT -5) on 24 Jan 2022]
Parents
  • Was this the right approach?

    I think so. Have you tested it yet? My boards are currently configured for on-chip PLL operation.

    I can give it a try in this mode, if you run into any issues.

    (Note 1, the nco-mode variable that appears in Analog device trees defining this doesn't appear in the C file that reads the device tree - I believe this may be an mistake and an update of the variable name from nco-mode to nco-mixer-mode in the device tree example files may have been forgotten.

    Good catch. Thanks for reporting.

    https://github.com/analogdevicesinc/linux/pull/1797

    Note 2, I have also changed the clocking to use the RFAUX8 output of the ADRF4360 and the selected output of the ADRF5020 as the DAC clock input frequency is <8 GHz, but I haven't discussed these changes above because I have high confidence that they will work)

    I assume you controlled this GPIO here?

    https://github.com/analogdevicesinc/linux/blob/master/arch/microblaze/boot/dts/vcu118_quad_ad9081.dtsi#L271

    -Michael

  • I haven't tested the device trees yet but I should be able to tomorrow or Wednesday - it'll be interesting to see whether they work - good to know it looks like it probably is! I'll let you know the outcome.

    And yeah, indeed, I mean that GPIO. I altered the relevant sections of the device tree to the following which should work to change the clocking correctly:

    &adf4371_clk0 {
    	channel@1 {
    		reg = <1>;
    		adi,power-up-frequency = /bits/ 64 <ADRF4360_RFAUX8_FREQUENCY_HZ>;
    	};
    };
    
    &adf4371_clk1 {
    	channel@1 {
    		reg = <1>;
    		adi,power-up-frequency = /bits/ 64 <ADRF4360_RFAUX8_FREQUENCY_HZ>;
    	};
    };
    
    &adf4371_clk2 {
    	channel@1 {
    		reg = <1>;
    		adi,power-up-frequency = /bits/ 64 <ADRF4360_RFAUX8_FREQUENCY_HZ>;
    	};
    };
    
    &adf4371_clk3 {
    	channel@1 {
    		reg = <1>;
    		adi,power-up-frequency = /bits/ 64 <ADRF4360_RFAUX8_FREQUENCY_HZ>;
    	};
    };
    
    &axi_gpio {
    	/delete-node/ adrf5020_ctrl;
    	adrf5020_ctrl {
    		gpio-hog;
    		gpios = <34 GPIO_ACTIVE_HIGH>;
    		output-low; /* output-low for the RF2 <-> clk-rfaux8 output */
    		line-name = "ADRF5020_CTRL";
    	};
    };

    Best regards,
    Kari

Reply
  • I haven't tested the device trees yet but I should be able to tomorrow or Wednesday - it'll be interesting to see whether they work - good to know it looks like it probably is! I'll let you know the outcome.

    And yeah, indeed, I mean that GPIO. I altered the relevant sections of the device tree to the following which should work to change the clocking correctly:

    &adf4371_clk0 {
    	channel@1 {
    		reg = <1>;
    		adi,power-up-frequency = /bits/ 64 <ADRF4360_RFAUX8_FREQUENCY_HZ>;
    	};
    };
    
    &adf4371_clk1 {
    	channel@1 {
    		reg = <1>;
    		adi,power-up-frequency = /bits/ 64 <ADRF4360_RFAUX8_FREQUENCY_HZ>;
    	};
    };
    
    &adf4371_clk2 {
    	channel@1 {
    		reg = <1>;
    		adi,power-up-frequency = /bits/ 64 <ADRF4360_RFAUX8_FREQUENCY_HZ>;
    	};
    };
    
    &adf4371_clk3 {
    	channel@1 {
    		reg = <1>;
    		adi,power-up-frequency = /bits/ 64 <ADRF4360_RFAUX8_FREQUENCY_HZ>;
    	};
    };
    
    &axi_gpio {
    	/delete-node/ adrf5020_ctrl;
    	adrf5020_ctrl {
    		gpio-hog;
    		gpios = <34 GPIO_ACTIVE_HIGH>;
    		output-low; /* output-low for the RF2 <-> clk-rfaux8 output */
    		line-name = "ADRF5020_CTRL";
    	};
    };

    Best regards,
    Kari

Children
  •   Sorry about the slow reply on this, I finished my draft of the designs last week and had the opportunity to test them.

    I ran into issues unfortunately.

    I'm not sure whether the DAC and ADC bypass works or not yet, as a prerequisite for it is that the DACs and ADCs must be ran at a clock frequency that can only be served by the RFAUX8 output of the ADRF4360, without interpolation or decimation. I've been unable to get that to work yet - so best to focus on the clocking first.

    For this purpose, here's a device tree that I've generated that is identical to vcu118_quad_ad9081_204c_txmode_23_rxmode_25_revc.dts with the exception of an altered configuration to use the RFAUX8 output of the ADRF4360 (detailed in my previous response), a 4 GHz DAC clock frequency, and lastly a reduction of the DAC interpolation ratio from 6x1 to 2x1. I'm running the device tree with system_top.vcu118_quad_ad9081_204c_txmode_23_rxmode_25_revc.bit with the latest version of the Linux kernel from Github.

    // SPDX-License-Identifier: GPL-2.0
    /*
     * Analog Devices Quad-MxFE
     * https://wiki.analog.com/resources/eval/user-guides/quadmxfe
     * https://wiki.analog.com/resources/tools-software/linux-drivers/iio-mxfe/ad9081
     * https://wiki.analog.com/resources/eval/user-guides/ad_quadmxfe1_ebz/ad_quadmxfe1_ebz_hdl
     *
     * hdl_project: <ad_quadmxfe1_ebz/vcu118>
     * board_revision: <>
     *
     * Copyright (C) 2019-2020 Analog Devices Inc.
     *
     * Adapted by Dr. Kari Clark for direct 8x ADC and 8x DAC operation in February 2022
     */
    
    #include <dt-bindings/iio/frequency/hmc7044.h>
    #include <dt-bindings/iio/adc/adi,ad9081.h>
    #include <dt-bindings/gpio/gpio.h>
    
    #include "vcu118_quad_ad9081.dtsi"
    
    // This setup assumes 500MHz clock into J41 (0 dBm)
    // ad9081_204c_txmode_23_rxmode_25_lr_24_75Gbps: Np 12 use case with high lane rate
    //     * 2Txs / 2Rxs per MxFE
    //     * DAC_CLK = 4GSPS
    //     * ADC_CLK = 4GSPS
    //     * Tx I/Q Rate: 2 GSPS (Interpolation of 2x1)
    //     * Rx I/Q Rate: 2 GSPS (Decimation of 2x1)
    //     * DAC JESD204C: Mode 23, L=4, M=4, N=N'=12
    //     * ADC JESD204C: Mode 25, L=4, M=4, N=N'=12
    //     * DAC-Side JESD204C Lane Rate: 24.75Gbps
    //     * ADC-Side JESD204C Lane Rate: 24.75Gbps
    
    // HDL Synthesis Parameters:
    // JESD_MODE=64B66B
    // RX_RATE=24.75
    // TX_RATE=24.75
    // REF_CLK_RATE=250
    // RX_JESD_M=4
    // RX_JESD_L=4
    // RX_JESD_S=2
    // RX_JESD_NP=12
    // TX_JESD_M=4
    // TX_JESD_L=4
    // TX_JESD_S=2
    // TX_JESD_NP=12
    // RX_PLL_SEL=1
    // TX_PLL_SEL=1
    // RX_KS_PER_CHANNEL=16
    // TX_KS_PER_CHANNEL=16
    
    #define ADRF4360_RFAUX8_FREQUENCY_HZ	4000000000
    
    #define HMC7043_FPGA_XCVR_CLKDIV		2
    #define HMC7043_FPGA_LINK_CLKDIV_TX		2
    #define HMC7043_FPGA_LINK_CLKDIV_RX		2
    #define HMC7043_SYSREF_CLKDIV			1024
    
    #define AD9081_DAC_FREQUENCY			ADRF4360_RFAUX8_FREQUENCY_HZ
    #define AD9081_ADC_FREQUENCY			4000000000
    
     /* TX path */
    #define AD9081_TX_LANERATE_KHZ			24750000
    #define AD9081_TX_LINK_CLK			375000000
    
    #define AD9081_TX_MAIN_INTERPOLATION		2
    #define AD9081_TX_CHAN_INTERPOLATION		1
    
    #ifndef AD9081_TX_MAIN_NCO_SHIFT
    #define AD9081_TX_MAIN_NCO_SHIFT		2800000000
    #endif
    #ifndef AD9081_TX_CHAN_NCO_SHIFT
    #define AD9081_TX_CHAN_NCO_SHIFT		0
    #endif
    
    #define AD9081_GAIN				1024
    
    #define AD9081_TX_JESD_MODE			23
    #define AD9081_TX_JESD_SUBCLASS			1
    #define AD9081_TX_JESD_VERSION			2
    #define AD9081_TX_JESD_M			4
    #define AD9081_TX_JESD_F			3
    #define AD9081_TX_JESD_K			256
    #define AD9081_TX_JESD_N			12
    #define AD9081_TX_JESD_NP			12
    #define AD9081_TX_JESD_CS			0
    #define AD9081_TX_JESD_L			4
    #define AD9081_TX_JESD_S			2
    #define AD9081_TX_JESD_HD			1
    
    #define AD9081_JRX_TPL_PHASE_ADJUST		28
    
    /* RX path */
    #define AD9081_RX_LANERATE_KHZ			24750000
    #define AD9081_RX_LINK_CLK			375000000
    #define AD9081_RX_MAIN_DECIMATION		2
    #define AD9081_RX_CHAN_DECIMATION		1
    
    #ifndef AD9081_RX_MAIN_NCO_SHIFT
    #define AD9081_RX_MAIN_NCO_SHIFT		1000000000
    #endif
    #ifndef AD9081_RX_CHAN_NCO_SHIFT
    #define AD9081_RX_CHAN_NCO_SHIFT		0
    #endif
    
    #ifndef AD9081_ADC_NYQUIST_ZONE
    #define AD9081_ADC_NYQUIST_ZONE		AD9081_ADC_NYQUIST_ZONE_EVEN
    #endif
    
    #define AD9081_RX_JESD_MODE			25
    #define AD9081_RX_JESD_SUBCLASS			1
    #define AD9081_RX_JESD_VERSION			2
    #define AD9081_RX_JESD_M			4
    #define AD9081_RX_JESD_F			3
    #define AD9081_RX_JESD_K			256
    #define AD9081_RX_JESD_N			12
    #define AD9081_RX_JESD_NP			12
    #define AD9081_RX_JESD_CS			0
    #define AD9081_RX_JESD_L			4
    #define AD9081_RX_JESD_S			2
    #define AD9081_RX_JESD_HD			1
    
    
    / {
    	model = "Analog Devices AD-QUADMXFE1-EBZ Rev.C";
    };
    
    &gpio_hmc425a {
    	compatible = "adi,hmc540s";
    	ctrl-gpios = <&axi_gpio 38 GPIO_ACTIVE_HIGH>,
    		<&axi_gpio 37 GPIO_ACTIVE_HIGH>,
    		<&axi_gpio 36 GPIO_ACTIVE_HIGH>,
    		<&axi_gpio 35 GPIO_ACTIVE_HIGH>;
    };
    
    &fmc_i2c {
    	current_limiter@58 {
    		compatible = "adi,adm1177-iio";
    		reg = <0x58>;
    		adi,r-sense-mohm = <10>; /* 10 mOhm */
    		adi,shutdown-threshold-ma = <10000>; /* 10 A */
    		adi,vrange-high-enable;
    	};
    };
    
    / {
    	rx_fixed_linerate: clock@2 {
    		#clock-cells = <0>;
    		compatible = "fixed-clock";
    		clock-frequency = <AD9081_RX_LANERATE_KHZ>;
    		clock-output-names = "rx_lane_clk";
    	};
    
    	tx_fixed_linerate: clock@3 {
    		#clock-cells = <0>;
    		compatible = "fixed-clock";
    		clock-frequency = <AD9081_TX_LANERATE_KHZ>;
    		clock-output-names = "tx_lane_clk";
    	};
    	rx_fixed_link_clk: clock@4 {
    		#clock-cells = <0>;
    		compatible = "fixed-clock";
    		clock-frequency = <AD9081_RX_LINK_CLK>;
    		clock-output-names = "rx_link_clk";
    	};
    
    	tx_fixed_link_clk: clock@5 {
    		#clock-cells = <0>;
    		compatible = "fixed-clock";
    		clock-frequency = <AD9081_TX_LINK_CLK>;
    		clock-output-names = "tx_link_clk";
    	};
    };
    
    /delete-node/ &axi_ad9081_adxcvr_rx;
    /delete-node/ &axi_ad9081_adxcvr_tx;
    
    &axi_ad9081_rx_jesd {
    	clock-names = "s_axi_aclk", "device_clk", "link_clk", "lane_clk";
    	clocks = <&clk_bus_0>, <&hmc7043 2>, <&rx_fixed_link_clk>, <&rx_fixed_linerate>;
    	jesd204-inputs = <&hmc7043 0 FRAMER_LINK0_RX>; /* omit axi_ad9081_adxcvr_rx */
    };
    
    &axi_ad9081_tx_jesd {
    	clock-names = "s_axi_aclk", "device_clk", "link_clk", "lane_clk";
    	clocks = <&clk_bus_0>, <&hmc7043 4>, <&tx_fixed_link_clk>, <&tx_fixed_linerate>;
    	jesd204-inputs = <&hmc7043 0 DEFRAMER_LINK0_TX>; /* omit axi_ad9081_adxcvr_tx */
    };
    
    &rx_dma {
    	/delete-node/ adi,channels; /* This comes from the synthesis paramtes */
    };
    
    &tx_dma {
    	/delete-node/ adi,channels; /* This comes from the synthesis paramtes */
    };
    
    &adf4371_clk0 {
    	channel@1 {
    		reg = <1>;
    		adi,power-up-frequency = /bits/ 64 <ADRF4360_RFAUX8_FREQUENCY_HZ>;
    	};
    };
    
    &adf4371_clk1 {
    	channel@1 {
    		reg = <1>;
    		adi,power-up-frequency = /bits/ 64 <ADRF4360_RFAUX8_FREQUENCY_HZ>;
    	};
    };
    
    &adf4371_clk2 {
    	channel@1 {
    		reg = <1>;
    		adi,power-up-frequency = /bits/ 64 <ADRF4360_RFAUX8_FREQUENCY_HZ>;
    	};
    };
    
    &adf4371_clk3 {
    	channel@1 {
    		reg = <1>;
    		adi,power-up-frequency = /bits/ 64 <ADRF4360_RFAUX8_FREQUENCY_HZ>;
    	};
    };
    
    &axi_gpio {
    	/delete-node/ adrf5020_ctrl;
    	adrf5020_ctrl {
    		gpio-hog;
    		gpios = <34 GPIO_ACTIVE_HIGH>;
    		output-low; /* output-low for the RF2 <-> clk-rfaux8 output */
    		line-name = "ADRF5020_CTRL";
    	};
    };
    
    &hmc7043 {
    	hmc7043_c0: channel@0 {
    		reg = <0>;
    		adi,extended-name = "FPGA_REFCLK";
    		adi,divider = <HMC7043_FPGA_XCVR_CLKDIV>;
    		adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
    	};
    
    	hmc7043_c1: channel@1 {
    		reg = <1>;
    		adi,extended-name = "SYSREF_FPGA";
    		adi,divider = <HMC7043_SYSREF_CLKDIV>;
    		adi,driver-mode = <HMC7044_DRIVER_MODE_LVPECL>;
    		adi,coarse-digital-delay = <0>;
    		adi,fine-analog-delay = <0>;
    		adi,output-mux-mode = <0>;
    		adi,jesd204-sysref-chan;
    	};
    
    	hmc7043_c2: channel@2 {
    		reg = <2>;
    		adi,extended-name = "RX_CORE_LINK_CLK";
    		adi,divider = <HMC7043_FPGA_LINK_CLKDIV_RX>;
    		adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
    	};
    
    	/delete-node/ hmc7043_c3;
    
    	hmc7043_c4: channel@4 {
    		reg = <4>;
    		adi,extended-name = "TX_CORE_LINK_CLK";
    		adi,divider = <HMC7043_FPGA_LINK_CLKDIV_TX>;
    		adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
    	};
    
    	/delete-node/ hmc7043_c5;
    	/delete-node/ hmc7043_c6;
    
    	hmc7043_c7: channel@7 {
    		reg = <7>;
    		adi,extended-name = "SYSREF_MXFE0";
    		adi,divider = <HMC7043_SYSREF_CLKDIV>;
    		adi,driver-mode = <HMC7044_DRIVER_MODE_LVPECL>;
    		adi,coarse-digital-delay = <0>;
    		adi,fine-analog-delay = <0>;
    		adi,output-mux-mode = <0>;
    		adi,jesd204-sysref-chan;
    	};
    
    	/delete-node/ hmc7043_c8;
    
    	hmc7043_c9: channel@9 {
    		reg = <9>;
    		adi,extended-name = "SYSREF_MXFE1";
    		adi,divider = <HMC7043_SYSREF_CLKDIV>;
    		adi,driver-mode = <HMC7044_DRIVER_MODE_LVPECL>;
    		adi,coarse-digital-delay = <0>;
    		adi,fine-analog-delay = <0>;
    		adi,output-mux-mode = <0>;
    		adi,jesd204-sysref-chan;
    	};
    
    	/delete-node/ hmc7043_c10;
    
    	hmc7043_c11: channel@11 {
    		reg = <11>;
    		adi,extended-name = "SYSREF_MXFE2";
    		adi,divider = <HMC7043_SYSREF_CLKDIV>;
    		adi,driver-mode = <HMC7044_DRIVER_MODE_LVPECL>;
    		adi,coarse-digital-delay = <0>;
    		adi,fine-analog-delay = <0>;
    		adi,output-mux-mode = <0>;
    		adi,jesd204-sysref-chan;
    	};
    
    	/delete-node/ hmc7043_c12;
    
    	hmc7043_c13: channel@13 {
    		reg = <13>;
    		adi,extended-name = "SYSREF_MXFE3";
    		adi,divider = <HMC7043_SYSREF_CLKDIV>;
    		adi,driver-mode = <HMC7044_DRIVER_MODE_LVPECL>;
    		adi,coarse-digital-delay = <0>;
    		adi,fine-analog-delay = <0>;
    		adi,output-mux-mode = <0>;
    		adi,jesd204-sysref-chan;
    	};
    };
    
    &trx0_ad9081 {
    
    	/delete-property/ adi,jesd-sync-pins-01-swap-enable;
    	adi,jesd-sync-pin-0a-cmos-enable;
    
    	adi,tx-dacs {
    		#size-cells = <0>;
    		#address-cells = <1>;
    		adi,dac-frequency-hz = /bits/ 64 <AD9081_DAC_FREQUENCY>;
    		adi,main-data-paths {
    			#address-cells = <1>;
    			#size-cells = <0>;
    			adi,interpolation = <AD9081_TX_MAIN_INTERPOLATION>;
    			trx0_ad9081_dac0: dac@0 {
    			    reg = <0>;
    			    adi,crossbar-select = <&trx0_ad9081_tx_fddc_chan0>;
    			    adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_TX_MAIN_NCO_SHIFT>;
    			};
    			trx0_ad9081_dac1: dac@1 {
    			    reg = <1>;
    			    adi,crossbar-select = <&trx0_ad9081_tx_fddc_chan1>;
    			    adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_TX_MAIN_NCO_SHIFT>;
    			};
    		};
    		adi,channelizer-paths {
    			#address-cells = <1>;
    			#size-cells = <0>;
    			adi,interpolation = <AD9081_TX_CHAN_INTERPOLATION>;
    			trx0_ad9081_tx_fddc_chan0: channel@0 {
    			    reg = <0>;
    			    adi,gain = <AD9081_GAIN>; /* value * 10^(gain_dB/20) */
    			    adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_TX_CHAN_NCO_SHIFT>;
    			};
    			trx0_ad9081_tx_fddc_chan1: channel@1 {
    			    reg = <1>;
    			    adi,gain = <AD9081_GAIN>; /* value * 10^(gain_dB/20) */
    			    adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_TX_CHAN_NCO_SHIFT>;
    			};
    		};
    
    		adi,jesd-links {
    			#size-cells = <0>;
    			#address-cells = <1>;
    			trx0_ad9081_tx_jesd_l0: link@0 {
    				#address-cells = <1>;
    				#size-cells = <0>;
    				reg = <0>;
    				adi,tpl-phase-adjust = <AD9081_JRX_TPL_PHASE_ADJUST>;
    				adi,logical-lane-mapping = /bits/ 8 <0 1 2 3 4 5 6 7>;
    				adi,link-mode = <AD9081_TX_JESD_MODE>;			/* JESD Quick Configuration Mode */
    				adi,subclass = <AD9081_TX_JESD_SUBCLASS>;			/* JESD SUBCLASS 0,1,2 */
    				adi,version = <AD9081_TX_JESD_VERSION>;			/* JESD VERSION 0=204A,1=204B,2=204C */
    				adi,dual-link = <0>;			/* JESD Dual Link Mode */
    				adi,converters-per-device = <AD9081_TX_JESD_M>;	/* JESD M */
    				adi,octets-per-frame = <AD9081_TX_JESD_F>;		/* JESD F */
    				adi,frames-per-multiframe = <AD9081_TX_JESD_K>;	/* JESD K */
    				adi,converter-resolution = <AD9081_TX_JESD_N>;	/* JESD N */
    				adi,bits-per-sample = <AD9081_TX_JESD_N>;		/* JESD NP' */
    				adi,control-bits-per-sample = <AD9081_TX_JESD_CS>;	/* JESD CS */
    				adi,lanes-per-device = <AD9081_TX_JESD_L>;		/* JESD L */
    				adi,samples-per-converter-per-frame = <AD9081_TX_JESD_S>; /* JESD S */
    				adi,high-density = <AD9081_TX_JESD_HD>;			/* JESD HD */
    			};
    		};
    	};
    
    	adi,rx-adcs {
    		#size-cells = <0>;
    		#address-cells = <1>;
    		adi,adc-frequency-hz = /bits/ 64 <AD9081_ADC_FREQUENCY>;
    		adi,nyquist-zone = <AD9081_ADC_NYQUIST_ZONE>;
    		adi,main-data-paths {
    			#address-cells = <1>;
    			#size-cells = <0>;
    			trx0_ad9081_adc0: adc@0 {
    				reg = <0>;
    				adi,decimation = <AD9081_RX_MAIN_DECIMATION>;
    				adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_RX_MAIN_NCO_SHIFT>;
    				adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
    				//adi,crossbar-select = <&trx0_ad9081_rx_fddc_chan0>, <&trx0_ad9081_rx_fddc_chan2>; /* Static for now */
    			};
    			trx0_ad9081_adc1: adc@1 {
    				reg = <1>;
    				adi,decimation = <AD9081_RX_MAIN_DECIMATION>;
    				adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_RX_MAIN_NCO_SHIFT>;
    				adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
    				//adi,crossbar-select = <&trx0_ad9081_rx_fddc_chan1>, <&trx0_ad9081_rx_fddc_chan3>; /* Static for now */
    			};
    		};
    		adi,channelizer-paths {
    			#address-cells = <1>;
    			#size-cells = <0>;
    			trx0_ad9081_rx_fddc_chan0: channel@0 {
    				reg = <0>;
    				adi,decimation = <AD9081_RX_CHAN_DECIMATION>;
    				adi,gain = <AD9081_GAIN>; /* value * 10^(gain_dB/20) */
    				adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_RX_CHAN_NCO_SHIFT>;
    			};
    			trx0_ad9081_rx_fddc_chan1: channel@1 {
    				reg = <1>;
    				adi,decimation = <AD9081_RX_CHAN_DECIMATION>;
    				adi,gain = <AD9081_GAIN>; /* value * 10^(gain_dB/20) */
    				adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_RX_CHAN_NCO_SHIFT>;
    			};
    		};
    		adi,jesd-links {
    			#size-cells = <0>;
    			#address-cells = <1>;
    			trx0_ad9081_rx_jesd_l0: link@0 {
    				reg = <0>;
    				adi,converter-select =
    					<&trx0_ad9081_rx_fddc_chan0 FDDC_I>, <&trx0_ad9081_rx_fddc_chan0 FDDC_Q>,
    					<&trx0_ad9081_rx_fddc_chan1 FDDC_I>, <&trx0_ad9081_rx_fddc_chan1 FDDC_Q>;
    				adi,logical-lane-mapping = /bits/ 8 <0 1 2 3 4 5 6 7>;
    				adi,link-mode = <AD9081_RX_JESD_MODE>;			/* JESD Quick Configuration Mode */
    				adi,subclass = <AD9081_RX_JESD_SUBCLASS>;			/* JESD SUBCLASS 0,1,2 */
    				adi,version = <AD9081_RX_JESD_VERSION>;			/* JESD VERSION 0=204A,1=204B,2=204C */
    				adi,dual-link = <0>;			/* JESD Dual Link Mode */
    				adi,device-id = <3>;
    				adi,converters-per-device = <AD9081_RX_JESD_M>;	/* JESD M */
    				adi,octets-per-frame = <AD9081_RX_JESD_F>;		/* JESD F */
    				adi,frames-per-multiframe = <AD9081_RX_JESD_K>;	/* JESD K */
    				adi,converter-resolution = <AD9081_RX_JESD_N>;	/* JESD N */
    				adi,bits-per-sample = <AD9081_RX_JESD_NP>;		/* JESD NP' */
    				adi,control-bits-per-sample = <AD9081_RX_JESD_CS>;	/* JESD CS */
    				adi,lanes-per-device = <AD9081_RX_JESD_L>;		/* JESD L */
    				adi,samples-per-converter-per-frame = <AD9081_RX_JESD_S>; /* JESD S */
    				adi,high-density = <AD9081_RX_JESD_HD>;			/* JESD HD */
    			};
    		};
    	};
    };
    
    &trx1_ad9081 {
    	/delete-property/ adi,jesd-sync-pins-01-swap-enable;
    	adi,jesd-sync-pin-0a-cmos-enable;
    
    	adi,tx-dacs {
    		#size-cells = <0>;
    		#address-cells = <1>;
    		adi,dac-frequency-hz = /bits/ 64 <AD9081_DAC_FREQUENCY>;
    		adi,main-data-paths {
    			#address-cells = <1>;
    			#size-cells = <0>;
    			adi,interpolation = <AD9081_TX_MAIN_INTERPOLATION>;
    			trx1_ad9081_dac0: dac@0 {
    			    reg = <0>;
    			    adi,crossbar-select = <&trx1_ad9081_tx_fddc_chan0>;
    			    adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_TX_MAIN_NCO_SHIFT>; /* 100 MHz */
    			};
    			trx1_ad9081_dac1: dac@1 {
    			    reg = <1>;
    			    adi,crossbar-select = <&trx1_ad9081_tx_fddc_chan1>;
    			    adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_TX_MAIN_NCO_SHIFT>; /* 200 MHz */
    			};
    		};
    		adi,channelizer-paths {
    			#address-cells = <1>;
    			#size-cells = <0>;
    			adi,interpolation = <AD9081_TX_CHAN_INTERPOLATION>;
    			trx1_ad9081_tx_fddc_chan0: channel@0 {
    			    reg = <0>;
    			    adi,gain = <AD9081_GAIN>; /* value * 10^(gain_dB/20) */
    			    adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_TX_CHAN_NCO_SHIFT>;
    			};
    			trx1_ad9081_tx_fddc_chan1: channel@1 {
    			    reg = <1>;
    			    adi,gain = <AD9081_GAIN>; /* value * 10^(gain_dB/20) */
    			    adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_TX_CHAN_NCO_SHIFT>;
    			};
    		};
    
    		adi,jesd-links {
    			#size-cells = <0>;
    			#address-cells = <1>;
    			trx1_ad9081_tx_jesd_l0: link@0 {
    				#address-cells = <1>;
    				#size-cells = <0>;
    				reg = <0>;
    				adi,tpl-phase-adjust = <AD9081_JRX_TPL_PHASE_ADJUST>;
    				adi,logical-lane-mapping = /bits/ 8 <0 1 2 3 4 5 6 7>;
    				adi,link-mode = <AD9081_TX_JESD_MODE>;			/* JESD Quick Configuration Mode */
    				adi,subclass = <AD9081_TX_JESD_SUBCLASS>;			/* JESD SUBCLASS 0,1,2 */
    				adi,version = <AD9081_TX_JESD_VERSION>;			/* JESD VERSION 0=204A,1=204B,2=204C */
    				adi,dual-link = <0>;			/* JESD Dual Link Mode */
    				adi,converters-per-device = <AD9081_TX_JESD_M>;	/* JESD M */
    				adi,octets-per-frame = <AD9081_TX_JESD_F>;		/* JESD F */
    				adi,frames-per-multiframe = <AD9081_TX_JESD_K>;	/* JESD K */
    				adi,converter-resolution = <AD9081_TX_JESD_N>;	/* JESD N */
    				adi,bits-per-sample = <AD9081_TX_JESD_N>;		/* JESD NP' */
    				adi,control-bits-per-sample = <AD9081_TX_JESD_CS>;	/* JESD CS */
    				adi,lanes-per-device = <AD9081_TX_JESD_L>;		/* JESD L */
    				adi,samples-per-converter-per-frame = <AD9081_TX_JESD_S>; /* JESD S */
    				adi,high-density = <AD9081_TX_JESD_HD>;			/* JESD HD */
    			};
    		};
    	};
    
    	adi,rx-adcs {
    		#size-cells = <0>;
    		#address-cells = <1>;
    		adi,adc-frequency-hz = /bits/ 64 <AD9081_ADC_FREQUENCY>;
    		adi,nyquist-zone = <AD9081_ADC_NYQUIST_ZONE>;
    		adi,main-data-paths {
    			#address-cells = <1>;
    			#size-cells = <0>;
    			trx1_ad9081_adc0: adc@0 {
    				reg = <0>;
    				adi,decimation = <AD9081_RX_MAIN_DECIMATION>;
    				adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_RX_MAIN_NCO_SHIFT>;
    				adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
    				//adi,crossbar-select = <&trx1_ad9081_rx_fddc_chan0>, <&trx1_ad9081_rx_fddc_chan2>; /* Static for now */
    			};
    			trx1_ad9081_adc1: adc@1 {
    				reg = <1>;
    				adi,decimation = <AD9081_RX_MAIN_DECIMATION>;
    				adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_RX_MAIN_NCO_SHIFT>;
    				adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
    				//adi,crossbar-select = <&trx1_ad9081_rx_fddc_chan1>, <&trx1_ad9081_rx_fddc_chan3>; /* Static for now */
    			};
    		};
    		adi,channelizer-paths {
    			#address-cells = <1>;
    			#size-cells = <0>;
    			trx1_ad9081_rx_fddc_chan0: channel@0 {
    				reg = <0>;
    				adi,decimation = <AD9081_RX_CHAN_DECIMATION>;
    				adi,gain = <AD9081_GAIN>; /* value * 10^(gain_dB/20) */
    				adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_RX_CHAN_NCO_SHIFT>;
    			};
    			trx1_ad9081_rx_fddc_chan1: channel@1 {
    				reg = <1>;
    				adi,decimation = <AD9081_RX_CHAN_DECIMATION>;
    				adi,gain = <AD9081_GAIN>; /* value * 10^(gain_dB/20) */
    				adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_RX_CHAN_NCO_SHIFT>;
    			};
    		};
    		adi,jesd-links {
    			#size-cells = <0>;
    			#address-cells = <1>;
    			trx1_ad9081_rx_jesd_l0: link@0 {
    				reg = <0>;
    				adi,converter-select =
    					<&trx1_ad9081_rx_fddc_chan0 FDDC_I>, <&trx1_ad9081_rx_fddc_chan0 FDDC_Q>,
    					<&trx1_ad9081_rx_fddc_chan1 FDDC_I>, <&trx1_ad9081_rx_fddc_chan1 FDDC_Q>;
    				adi,logical-lane-mapping = /bits/ 8 <0 1 2 3 4 5 6 7>;
    				adi,link-mode = <AD9081_RX_JESD_MODE>;			/* JESD Quick Configuration Mode */
    				adi,subclass = <AD9081_RX_JESD_SUBCLASS>;			/* JESD SUBCLASS 0,1,2 */
    				adi,version = <AD9081_RX_JESD_VERSION>;			/* JESD VERSION 0=204A,1=204B,2=204C */
    				adi,dual-link = <0>;			/* JESD Dual Link Mode */
    				adi,device-id = <3>;
    				adi,converters-per-device = <AD9081_RX_JESD_M>;	/* JESD M */
    				adi,octets-per-frame = <AD9081_RX_JESD_F>;		/* JESD F */
    				adi,frames-per-multiframe = <AD9081_RX_JESD_K>;	/* JESD K */
    				adi,converter-resolution = <AD9081_RX_JESD_N>;	/* JESD N */
    				adi,bits-per-sample = <AD9081_RX_JESD_NP>;		/* JESD NP' */
    				adi,control-bits-per-sample = <AD9081_RX_JESD_CS>;	/* JESD CS */
    				adi,lanes-per-device = <AD9081_RX_JESD_L>;		/* JESD L */
    				adi,samples-per-converter-per-frame = <AD9081_RX_JESD_S>; /* JESD S */
    				adi,high-density = <AD9081_RX_JESD_HD>;			/* JESD HD */
    			};
    		};
    	};
    };
    
    &trx2_ad9081 {
    	/delete-property/ adi,jesd-sync-pins-01-swap-enable;
    	adi,jesd-sync-pin-0a-cmos-enable;
    
    	adi,tx-dacs {
    		#size-cells = <0>;
    		#address-cells = <1>;
    		adi,dac-frequency-hz = /bits/ 64 <AD9081_DAC_FREQUENCY>;
    		adi,main-data-paths {
    			#address-cells = <1>;
    			#size-cells = <0>;
    			adi,interpolation = <AD9081_TX_MAIN_INTERPOLATION>;
    			trx2_ad9081_dac0: dac@0 {
    			    reg = <0>;
    			    adi,crossbar-select = <&trx2_ad9081_tx_fddc_chan0>;
    			    adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_TX_MAIN_NCO_SHIFT>; /* 100 MHz */
    			};
    			trx2_ad9081_dac1: dac@1 {
    			    reg = <1>;
    			    adi,crossbar-select = <&trx2_ad9081_tx_fddc_chan1>;
    			    adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_TX_MAIN_NCO_SHIFT>; /* 200 MHz */
    			};
    		};
    		adi,channelizer-paths {
    			#address-cells = <1>;
    			#size-cells = <0>;
    			adi,interpolation = <AD9081_TX_CHAN_INTERPOLATION>;
    			trx2_ad9081_tx_fddc_chan0: channel@0 {
    			    reg = <0>;
    			    adi,gain = <AD9081_GAIN>; /* value * 10^(gain_dB/20) */
    			    adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_TX_CHAN_NCO_SHIFT>;
    			};
    			trx2_ad9081_tx_fddc_chan1: channel@1 {
    			    reg = <1>;
    			    adi,gain = <AD9081_GAIN>; /* value * 10^(gain_dB/20) */
    			    adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_TX_CHAN_NCO_SHIFT>;
    			};
    		};
    
    		adi,jesd-links {
    			#size-cells = <0>;
    			#address-cells = <1>;
    			trx2_ad9081_tx_jesd_l0: link@0 {
    				#address-cells = <1>;
    				#size-cells = <0>;
    				reg = <0>;
    				adi,tpl-phase-adjust = <AD9081_JRX_TPL_PHASE_ADJUST>;
    				adi,logical-lane-mapping = /bits/ 8 <0 1 2 3 4 5 6 7>;
    				adi,link-mode = <AD9081_TX_JESD_MODE>;			/* JESD Quick Configuration Mode */
    				adi,subclass = <AD9081_TX_JESD_SUBCLASS>;			/* JESD SUBCLASS 0,1,2 */
    				adi,version = <AD9081_TX_JESD_VERSION>;			/* JESD VERSION 0=204A,1=204B,2=204C */
    				adi,dual-link = <0>;			/* JESD Dual Link Mode */
    				adi,converters-per-device = <AD9081_TX_JESD_M>;	/* JESD M */
    				adi,octets-per-frame = <AD9081_TX_JESD_F>;		/* JESD F */
    				adi,frames-per-multiframe = <AD9081_TX_JESD_K>;	/* JESD K */
    				adi,converter-resolution = <AD9081_TX_JESD_N>;	/* JESD N */
    				adi,bits-per-sample = <AD9081_TX_JESD_N>;		/* JESD NP' */
    				adi,control-bits-per-sample = <AD9081_TX_JESD_CS>;	/* JESD CS */
    				adi,lanes-per-device = <AD9081_TX_JESD_L>;		/* JESD L */
    				adi,samples-per-converter-per-frame = <AD9081_TX_JESD_S>; /* JESD S */
    				adi,high-density = <AD9081_TX_JESD_HD>;			/* JESD HD */
    			};
    		};
    	};
    
    	adi,rx-adcs {
    		#size-cells = <0>;
    		#address-cells = <1>;
    		adi,adc-frequency-hz = /bits/ 64 <AD9081_ADC_FREQUENCY>;
    		adi,nyquist-zone = <AD9081_ADC_NYQUIST_ZONE>;
    		adi,main-data-paths {
    			#address-cells = <1>;
    			#size-cells = <0>;
    			trx2_ad9081_adc0: adc@0 {
    				reg = <0>;
    				adi,decimation = <AD9081_RX_MAIN_DECIMATION>;
    				adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_RX_MAIN_NCO_SHIFT>;
    				adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
    				//adi,crossbar-select = <&trx2_ad9081_rx_fddc_chan0>, <&trx2_ad9081_rx_fddc_chan2>; /* Static for now */
    			};
    			trx2_ad9081_adc1: adc@1 {
    				reg = <1>;
    				adi,decimation = <AD9081_RX_MAIN_DECIMATION>;
    				adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_RX_MAIN_NCO_SHIFT>;
    				adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
    				//adi,crossbar-select = <&trx2_ad9081_rx_fddc_chan1>, <&trx2_ad9081_rx_fddc_chan3>; /* Static for now */
    			};
    		};
    		adi,channelizer-paths {
    			#address-cells = <1>;
    			#size-cells = <0>;
    			trx2_ad9081_rx_fddc_chan0: channel@0 {
    				reg = <0>;
    				adi,decimation = <AD9081_RX_CHAN_DECIMATION>;
    				adi,gain = <AD9081_GAIN>; /* value * 10^(gain_dB/20) */
    				adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_RX_CHAN_NCO_SHIFT>;
    			};
    			trx2_ad9081_rx_fddc_chan1: channel@1 {
    				reg = <1>;
    				adi,decimation = <AD9081_RX_CHAN_DECIMATION>;
    				adi,gain = <AD9081_GAIN>; /* value * 10^(gain_dB/20) */
    				adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_RX_CHAN_NCO_SHIFT>;
    			};
    		};
    		adi,jesd-links {
    			#size-cells = <0>;
    			#address-cells = <1>;
    			trx2_ad9081_rx_jesd_l0: link@0 {
    				reg = <0>;
    				adi,converter-select =
    					<&trx2_ad9081_rx_fddc_chan0 FDDC_I>, <&trx2_ad9081_rx_fddc_chan0 FDDC_Q>,
    					<&trx2_ad9081_rx_fddc_chan1 FDDC_I>, <&trx2_ad9081_rx_fddc_chan1 FDDC_Q>;
    				adi,logical-lane-mapping = /bits/ 8 <0 1 2 3 4 5 6 7>;
    				adi,link-mode = <AD9081_RX_JESD_MODE>;			/* JESD Quick Configuration Mode */
    				adi,subclass = <AD9081_RX_JESD_SUBCLASS>;			/* JESD SUBCLASS 0,1,2 */
    				adi,version = <AD9081_RX_JESD_VERSION>;			/* JESD VERSION 0=204A,1=204B,2=204C */
    				adi,dual-link = <0>;			/* JESD Dual Link Mode */
    				adi,device-id = <3>;
    				adi,converters-per-device = <AD9081_RX_JESD_M>;	/* JESD M */
    				adi,octets-per-frame = <AD9081_RX_JESD_F>;		/* JESD F */
    				adi,frames-per-multiframe = <AD9081_RX_JESD_K>;	/* JESD K */
    				adi,converter-resolution = <AD9081_RX_JESD_N>;	/* JESD N */
    				adi,bits-per-sample = <AD9081_RX_JESD_NP>;		/* JESD NP' */
    				adi,control-bits-per-sample = <AD9081_RX_JESD_CS>;	/* JESD CS */
    				adi,lanes-per-device = <AD9081_RX_JESD_L>;		/* JESD L */
    				adi,samples-per-converter-per-frame = <AD9081_RX_JESD_S>; /* JESD S */
    				adi,high-density = <AD9081_RX_JESD_HD>;			/* JESD HD */
    			};
    		};
    	};
    };
    
    &trx3_ad9081 {
    	/delete-property/ adi,jesd-sync-pins-01-swap-enable;
    	adi,jesd-sync-pin-0a-cmos-enable;
    
    	adi,tx-dacs {
    		#size-cells = <0>;
    		#address-cells = <1>;
    		adi,dac-frequency-hz = /bits/ 64 <AD9081_DAC_FREQUENCY>;
    		adi,main-data-paths {
    			#address-cells = <1>;
    			#size-cells = <0>;
    			adi,interpolation = <AD9081_TX_MAIN_INTERPOLATION>;
    			trx3_ad9081_dac0: dac@0 {
    			    reg = <0>;
    			    adi,crossbar-select = <&trx3_ad9081_tx_fddc_chan0>;
    			    adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_TX_MAIN_NCO_SHIFT>; /* 100 MHz */
    			};
    			trx3_ad9081_dac1: dac@1 {
    			    reg = <1>;
    			    adi,crossbar-select = <&trx3_ad9081_tx_fddc_chan1>;
    			    adi,nco-frequency-shift-hz = /bits/ 64 <AD9081_TX_MAIN_NCO_SHIFT>; /* 200 MHz */
    			};
    		};
    		adi,channelizer-paths {
    			#address-cells = <1>;
    			#size-cells = <0>;
    			adi,interpolation = <AD9081_TX_CHAN_INTERPOLATION>;
    			trx3_ad9081_tx_fddc_chan0: channel@0 {
    			    reg = <0>;
    			    adi,gain = <AD9081_GAIN>; /* value * 10^(gain_dB/20) */
    			    adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_TX_CHAN_NCO_SHIFT>;
    			};
    			trx3_ad9081_tx_fddc_chan1: channel@1 {
    			    reg = <1>;
    			    adi,gain = <AD9081_GAIN>; /* value * 10^(gain_dB/20) */
    			    adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_TX_CHAN_NCO_SHIFT>;
    			};
    		};
    
    		adi,jesd-links {
    			#size-cells = <0>;
    			#address-cells = <1>;
    			trx3_ad9081_tx_jesd_l0: link@0 {
    				#address-cells = <1>;
    				#size-cells = <0>;
    				reg = <0>;
    				adi,tpl-phase-adjust = <AD9081_JRX_TPL_PHASE_ADJUST>;
    				adi,logical-lane-mapping = /bits/ 8 <0 1 2 3 4 5 6 7>;
    				adi,link-mode = <AD9081_TX_JESD_MODE>;			/* JESD Quick Configuration Mode */
    				adi,subclass = <AD9081_TX_JESD_SUBCLASS>;			/* JESD SUBCLASS 0,1,2 */
    				adi,version = <AD9081_TX_JESD_VERSION>;			/* JESD VERSION 0=204A,1=204B,2=204C */
    				adi,dual-link = <0>;			/* JESD Dual Link Mode */
    				adi,converters-per-device = <AD9081_TX_JESD_M>;	/* JESD M */
    				adi,octets-per-frame = <AD9081_TX_JESD_F>;		/* JESD F */
    				adi,frames-per-multiframe = <AD9081_TX_JESD_K>;	/* JESD K */
    				adi,converter-resolution = <AD9081_TX_JESD_N>;	/* JESD N */
    				adi,bits-per-sample = <AD9081_TX_JESD_N>;		/* JESD NP' */
    				adi,control-bits-per-sample = <AD9081_TX_JESD_CS>;	/* JESD CS */
    				adi,lanes-per-device = <AD9081_TX_JESD_L>;		/* JESD L */
    				adi,samples-per-converter-per-frame = <AD9081_TX_JESD_S>; /* JESD S */
    				adi,high-density = <AD9081_TX_JESD_HD>;			/* JESD HD */
    			};
    		};
    	};
    
    	adi,rx-adcs {
    		#size-cells = <0>;
    		#address-cells = <1>;
    		adi,adc-frequency-hz = /bits/ 64 <AD9081_ADC_FREQUENCY>;
    		adi,nyquist-zone = <AD9081_ADC_NYQUIST_ZONE>;
    		adi,main-data-paths {
    			#address-cells = <1>;
    			#size-cells = <0>;
    			trx3_ad9081_adc0: adc@0 {
    				reg = <0>;
    				adi,decimation = <AD9081_RX_MAIN_DECIMATION>;
    				adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_RX_MAIN_NCO_SHIFT>;
    				adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
    				//adi,crossbar-select = <&trx3_ad9081_rx_fddc_chan0>, <&trx3_ad9081_rx_fddc_chan2>; /* Static for now */
    			};
    			trx3_ad9081_adc1: adc@1 {
    				reg = <1>;
    				adi,decimation = <AD9081_RX_MAIN_DECIMATION>;
    				adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_RX_MAIN_NCO_SHIFT>;
    				adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
    				//adi,crossbar-select = <&trx3_ad9081_rx_fddc_chan1>, <&trx3_ad9081_rx_fddc_chan3>; /* Static for now */
    			};
    		};
    		adi,channelizer-paths {
    			#address-cells = <1>;
    			#size-cells = <0>;
    			trx3_ad9081_rx_fddc_chan0: channel@0 {
    				reg = <0>;
    				adi,decimation = <AD9081_RX_CHAN_DECIMATION>;
    				adi,gain = <AD9081_GAIN>; /* value * 10^(gain_dB/20) */
    				adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_RX_CHAN_NCO_SHIFT>;
    			};
    			trx3_ad9081_rx_fddc_chan1: channel@1 {
    				reg = <1>;
    				adi,decimation = <AD9081_RX_CHAN_DECIMATION>;
    				adi,gain = <AD9081_GAIN>; /* value * 10^(gain_dB/20) */
    				adi,nco-frequency-shift-hz =  /bits/ 64 <AD9081_RX_CHAN_NCO_SHIFT>;
    			};
    		};
    		adi,jesd-links {
    			#size-cells = <0>;
    			#address-cells = <1>;
    			trx3_ad9081_rx_jesd_l0: link@0 {
    				reg = <0>;
    				adi,converter-select =
    					<&trx3_ad9081_rx_fddc_chan0 FDDC_I>, <&trx3_ad9081_rx_fddc_chan0 FDDC_Q>,
    					<&trx3_ad9081_rx_fddc_chan1 FDDC_I>, <&trx3_ad9081_rx_fddc_chan1 FDDC_Q>;
    				adi,logical-lane-mapping = /bits/ 8 <0 1 2 3 4 5 6 7>;
    				adi,link-mode = <AD9081_RX_JESD_MODE>;			/* JESD Quick Configuration Mode */
    				adi,subclass = <AD9081_RX_JESD_SUBCLASS>;			/* JESD SUBCLASS 0,1,2 */
    				adi,version = <AD9081_RX_JESD_VERSION>;			/* JESD VERSION 0=204A,1=204B,2=204C */
    				adi,dual-link = <0>;			/* JESD Dual Link Mode */
    				adi,device-id = <3>;
    				adi,converters-per-device = <AD9081_RX_JESD_M>;	/* JESD M */
    				adi,octets-per-frame = <AD9081_RX_JESD_F>;		/* JESD F */
    				adi,frames-per-multiframe = <AD9081_RX_JESD_K>;	/* JESD K */
    				adi,converter-resolution = <AD9081_RX_JESD_N>;	/* JESD N */
    				adi,bits-per-sample = <AD9081_RX_JESD_NP>;		/* JESD NP' */
    				adi,control-bits-per-sample = <AD9081_RX_JESD_CS>;	/* JESD CS */
    				adi,lanes-per-device = <AD9081_RX_JESD_L>;		/* JESD L */
    				adi,samples-per-converter-per-frame = <AD9081_RX_JESD_S>; /* JESD S */
    				adi,high-density = <AD9081_RX_JESD_HD>;			/* JESD HD */
    			};
    		};
    	};
    };
    

    (Sorry for the direct code paste - can't upload dts files on EngineerZone for some reason! Note that this is the base dts file for revc non-NZ1 operation, we actually compile the Linux kernel with the NZ1 extension to this file, which is identical to vcu118_quad_ad9081_204c_txmode_23_rxmode_25_revc_nz1.dts other than the #include dts file statement.)

    With this configuration, the initialisation of the AD9081 chips fails to complete, with the following errors:

    ad9081 spi0.0: supply vdd not found, using dummy regulator
    ad9081 spi0.0: Boot did not reach spot where it waits for application code
    ad9081 spi0.0: Failed to initialize: -40
    ad9081: probe of spi0.0 failed with error -40
    ad9081 spi0.1: supply vdd not found, using dummy regulator
    ad9081 spi0.1: Boot did not reach spot where it waits for application code
    ad9081 spi0.1: Failed to initialize: -40
    ad9081: probe of spi0.1 failed with error -40
    ad9081 spi0.2: supply vdd not found, using dummy regulator
    ad9081 spi0.2: Boot did not reach spot where it waits for application code
    ad9081 spi0.2: Failed to initialize: -40
    ad9081: probe of spi0.2 failed with error -40
    ad9081 spi0.3: supply vdd not found, using dummy regulator
    ad9081 spi0.3: Boot did not reach spot where it waits for application code
    ad9081 spi0.3: Failed to initialize: -40
    ad9081: probe of spi0.3 failed with error -40

    I assume that the supply vdd error is fine as this is related to the use of the revc board (I think).

    Here is the complete Buildroot startup log for reference:

    Ramdisk addr 0x00000000,
    Compiled-in FDT at 0x80589c64
    earlycon: uartlite_a0 at MMIO 0x40600000 (options '115200n8')
    printk: bootconsole [uartlite_a0] enabled
    cma: Reserved 512 MiB at 0x8e000000
    Linux version 5.10.0-98017-geacf1591b324 (uceeacl@saturn.ee.ucl.ac.uk) (microblazeel-xilinx-linux-gcc.real (GCC) 10.2.0, GNU ld (GNU Binutils) 2.35.1) #17 Thu Feb 10 00:05:55 GMT 2022
    setup_memory: max_mapnr: 0x7ffff
    setup_memory: min_low_pfn: 0x80000
    setup_memory: max_low_pfn: 0xb0000
    setup_memory: max_pfn: 0xfffff
    Zone ranges:
      DMA      [mem 0x0000000080000000-0x00000000afffffff]
      Normal   empty
      HighMem  [mem 0x00000000b0000000-0x00000000ffffefff]
    Movable zone start for each node
    Early memory node ranges
      node   0: [mem 0x0000000080000000-0x00000000ffffefff]
    Initmem setup node 0 [mem 0x0000000080000000-0x00000000ffffefff]
    setup_cpuinfo: initialising cpu 0
    setup_cpuinfo: Using full CPU PVR support
    wt_msr_noirq
    pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
    pcpu-alloc: [0] 0
    Built 1 zonelists, mobility grouping on.  Total pages: 522751
    Kernel command line: earlycon
    Dentry cache hash table entries: 131072 (order: 7, 524288 bytes, linear)
    Inode-cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
    mem auto-init: stack:off, heap alloc:off, heap free:off
    Memory: 1536076K/2097148K available (5671K kernel code, 568K rwdata, 5476K rodata, 170K init, 170K bss, 36784K reserved, 524288K cma-reserved, 1310716K highmem)
    NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
    irq-xilinx: /amba_pl/interrupt-controller@41200000: num_irq=16, sw_irq=0, edge=0x4f0
    xilinx_timer_init: Timer base: 0xb0002000, Clocksource base: 0xb0002010
    clocksource: xilinx_clocksource: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604467 ns
    sched_clock: 32 bits at 100MHz, resolution 10ns, wraps every 21474836475ns
    /amba_pl/timer@41c00000: irq=1, cpu_id 0
    xilinx_timer_shutdown
    xilinx_timer_set_periodic
    Calibrating delay loop... 49.35 BogoMIPS (lpj=246784)
    pid_max: default: 4096 minimum: 301
    Mount-cache hash table entries: 2048 (order: 1, 8192 bytes, linear)
    Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes, linear)
    devtmpfs: initialized
    random: get_random_u32 called from bucket_table_alloc.isra.0+0x148/0x170 with crng_init=0
    clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
    futex hash table entries: 16 (order: -4, 448 bytes, linear)
    NET: Registered protocol family 16
    DMA: preallocated 256 KiB GFP_KERNEL pool for atomic allocations
    DMA: preallocated 256 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
    PCI: Probing PCI hardware
    gpio-482 (ADRF5020_CTRL): hogged as output/low
    gpio-428 (GPIO_0 HDL mux mode): hogged as output/high
    vgaarb: loaded
    jesd204: created con: id=0, topo=0, link=0, /amba_pl/spi@44a80000/hmc7043@4 <-> /amba_pl/axi-jesd204-tx@44b90000
    jesd204: created con: id=1, topo=0, link=2, /amba_pl/spi@44a80000/hmc7043@4 <-> /amba_pl/axi-jesd204-rx@44a90000
    jesd204: created con: id=2, topo=0, link=0, /amba_pl/axi-jesd204-tx@44b90000 <-> /amba_pl/axi-ad9081-tx-3@44b10000
    jesd204: created con: id=3, topo=0, link=2, /amba_pl/axi-jesd204-rx@44a90000 <-> /amba_pl/axi-ad9081-rx-3@44a10000
    jesd204: created con: id=4, topo=0, link=2, /amba_pl/spi@44a70000/axi-ad9081-rx-2@2 <-> /amba_pl/spi@44a70000/ad9081@3
    jesd204: created con: id=5, topo=0, link=0, /amba_pl/spi@44a70000/axi-ad9081-rx-2@2 <-> /amba_pl/spi@44a70000/ad9081@3
    jesd204: created con: id=6, topo=0, link=2, /amba_pl/spi@44a70000/axi-ad9081-rx-1@1 <-> /amba_pl/spi@44a70000/axi-ad9081-rx-2@2
    jesd204: created con: id=7, topo=0, link=0, /amba_pl/spi@44a70000/axi-ad9081-rx-1@1 <-> /amba_pl/spi@44a70000/axi-ad9081-rx-2@2
    jesd204: created con: id=8, topo=0, link=2, /amba_pl/spi@44a70000/axi-ad9081-rx-0@0 <-> /amba_pl/spi@44a70000/axi-ad9081-rx-1@1
    jesd204: created con: id=9, topo=0, link=0, /amba_pl/spi@44a70000/axi-ad9081-rx-0@0 <-> /amba_pl/spi@44a70000/axi-ad9081-rx-1@1
    jesd204: created con: id=10, topo=0, link=2, /amba_pl/axi-ad9081-rx-3@44a10000 <-> /amba_pl/spi@44a70000/axi-ad9081-rx-0@0
    jesd204: created con: id=11, topo=0, link=0, /amba_pl/axi-ad9081-tx-3@44b10000 <-> /amba_pl/spi@44a70000/axi-ad9081-rx-0@0
    jesd204: /amba_pl/spi@44a70000/ad9081@3: JESD204[2] transition uninitialized -> initialized
    jesd204: /amba_pl/spi@44a70000/ad9081@3: JESD204[0] transition uninitialized -> initialized
    jesd204: found 9 devices and 1 topologies
    clocksource: Switched to clocksource xilinx_clocksource
    NET: Registered protocol family 2
    tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 12288 bytes, linear)
    TCP established hash table entries: 8192 (order: 3, 32768 bytes, linear)
    TCP bind hash table entries: 8192 (order: 5, 163840 bytes, linear)
    TCP: Hash tables configured (established 8192 bind 8192)
    UDP hash table entries: 512 (order: 2, 24576 bytes, linear)
    UDP-Lite hash table entries: 512 (order: 2, 24576 bytes, linear)
    NET: Registered protocol family 1
    RPC: Registered named UNIX socket transport module.
    RPC: Registered udp transport module.
    RPC: Registered tcp transport module.
    RPC: Registered tcp NFSv4.1 backchannel transport module.
    PCI: CLS 0 bytes, default 32
    random: fast init done
    workingset: timestamp_bits=30 max_order=19 bucket_order=0
    Key type cifs.idmap registered
    jffs2: version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
    romfs: ROMFS MTD (C) 2007 Red Hat, Inc.
    bounce: pool size: 64 pages
    io scheduler mq-deadline registered
    io scheduler kyber registered
    Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
    40600000.serial: ttyUL0 at MMIO 0x40600000 (irq = 5, base_baud = 0) is a uartlite
    printk: console [ttyUL0] enabled
    printk: console [ttyUL0] enabled
    printk: bootconsole [uartlite_a0] disabled
    printk: bootconsole [uartlite_a0] disabled
    uartlite 41400000.serial: IRQ index 0 not found
    brd: module loaded
    Xilinx SystemACE device driver, major=254
    libphy: Fixed MDIO Bus: probed
    xilinx_axienet 40c00000.ethernet: TX_CSUM 2
    xilinx_axienet 40c00000.ethernet: RX_CSUM 2
    libphy: Xilinx Axi Ethernet MDIO: probed
    i2c /dev entries driver
    i2c i2c-0: Added multiplexed i2c bus 1
    at24 2-0050: supply vcc not found, using dummy regulator
    at24 2-0050: 256 byte 24c02 EEPROM, writable, 1 bytes/write
    i2c i2c-0: Added multiplexed i2c bus 2
    i2c i2c-0: Added multiplexed i2c bus 3
    at24 4-0054: supply vcc not found, using dummy regulator
    at24 4-0054: 1024 byte 24c08 EEPROM, writable, 1 bytes/write
    i2c i2c-0: Added multiplexed i2c bus 4
    i2c i2c-0: Added multiplexed i2c bus 5
    i2c i2c-0: Added multiplexed i2c bus 6
    i2c i2c-0: Added multiplexed i2c bus 7
    i2c i2c-0: Added multiplexed i2c bus 8
    pca954x 0-0075: registered 8 multiplexed busses for I2C switch pca9548
    si570 9-005d: registered, current frequency 148500000 Hz
    i2c i2c-0: Added multiplexed i2c bus 9
    i2c i2c-0: Added multiplexed i2c bus 10
    i2c i2c-0: Added multiplexed i2c bus 11
    i2c i2c-0: Added multiplexed i2c bus 12
    i2c i2c-0: Added multiplexed i2c bus 13
    i2c i2c-0: Added multiplexed i2c bus 14
    i2c i2c-0: Added multiplexed i2c bus 15
    i2c i2c-0: Added multiplexed i2c bus 16
    pca954x 0-0074: registered 8 multiplexed busses for I2C switch pca9548
    hmc425a amba_pl:hmc425a: supply vcc-supply not found, using dummy regulator
    hmc7044 spi1.4: CLKIN0 @ 500.000000 MHz
    jesd204: /amba_pl/spi@44a80000/hmc7043@4,jesd204:4,parent=spi1.4: Using as SYSREF provider
    axi-jesd204-rx 44a90000.axi-jesd204-rx: AXI-JESD204-RX (1.07.a) at 0x44A90000. Encoder 64b66b, width 8/12, lanes 16, jesd204-fsm.
    axi-jesd204-tx 44b90000.axi-jesd204-tx: AXI-JESD204-TX (1.06.a) at 0x44B90000. Encoder 64b66b, width 8/12, lanes 16, jesd204-fsm.
    axi_sysid 45000000.axi-sysid-0: AXI System ID core version (1.01.a) found
    axi_sysid 45000000.axi-sysid-0: [ad_quadmxfe1_ebz] [sys rom custom string placeholder] on [vcu118] git branch <dev_quad_mxfe_revc> git <08f24ed752311a2d6d67382fedff747ce7fc1a1f> clean [2021-03-04 13:36:27] UTC
    NET: Registered protocol family 17
    Key type encrypted registered
    ad9081 spi0.0: supply vdd not found, using dummy regulator
    ad9081 spi0.0: Boot did not reach spot where it waits for application code
    ad9081 spi0.0: Failed to initialize: -40
    ad9081: probe of spi0.0 failed with error -40
    ad9081 spi0.1: supply vdd not found, using dummy regulator
    ad9081 spi0.1: Boot did not reach spot where it waits for application code
    ad9081 spi0.1: Failed to initialize: -40
    ad9081: probe of spi0.1 failed with error -40
    ad9081 spi0.2: supply vdd not found, using dummy regulator
    ad9081 spi0.2: Boot did not reach spot where it waits for application code
    ad9081 spi0.2: Failed to initialize: -40
    ad9081: probe of spi0.2 failed with error -40
    ad9081 spi0.3: supply vdd not found, using dummy regulator
    ad9081 spi0.3: Boot did not reach spot where it waits for application code
    ad9081 spi0.3: Failed to initialize: -40
    ad9081: probe of spi0.3 failed with error -40
    Freeing unused kernel memory: 168K
    This architecture does not have kernel memory protection.
    Run /init as init process
      with arguments:
        /init
      with environment:
        HOME=/
        TERM=linux
    Starting syslogd: OK
    Starting klogd: OK
    Running sysctl: OK
    Saving random seed: random: dd: uninitialized urandom read (512 bytes read)
    OK
    Starting system message bus: random: dbus-uuidgen: uninitialized urandom read (12 bytes read)
    random: dbus-uuidgen: uninitialized urandom read (8 bytes read)
    dbus-daemon[93]: this watch should have been invalidated
    dbus-daemon[93]: Bad fd 808195644
    dbus-daemon[93]: Failed to start message bus: Memory allocation failure in message bus
    done
    Starting network: udhcpc: started, v1.33.1
    net eth0: Promiscuous mode disabled.
    net eth0: Promiscuous mode disabled.
    xilinx_axienet 40c00000.ethernet eth0: Link is Down
    udhcpc: sending discover
    xilinx_axienet 40c00000.ethernet eth0: Link is Up - 1Gbps/Full - flow control off
    udhcpc: sending discover
    udhcpc: sending discover
    udhcpc: sending discover
    udhcpc: sending discover
    udhcpc: sending discover
    udhcpc: sending discover
    urandom_read: 2 callbacks suppressed
    random: avahi-autoipd: uninitialized urandom read (4 bytes read)
    udhcpc: no lease, failing
    Analog Devices AD-QUADMXFE2-EBZ
    Checking FRU EEPROM: read 256 bytes from /sys/bus/i2c/devices/2-0050/eeprom
    Date of Man     : Thu Jun  3 12:00:00 2021
    Manufacturer    : Analog Devices
    Product Name    : Quad-MxFE (AD9082, NZ2)
    Serial Number   : S21-0290_2
    Part Number     : ADQUADMXFE3EBZ
    FRU File ID     : Empty Field
    PCB Rev         : C
    PCB ID          : 20_057438c
    BOM Rev         : D
    Uses LVDS       : Y
    random: avahi-daemon: uninitialized urandom read (4 bytes read)
    random: avahi-daemon: uninitialized urandom read (4 bytes read)
    Starting dropbear sshd: OK
    Starting IIO Server Daemon
    
    Welcome to Buildroot
    buildroot login:

    If you could have a look into this, I would much appreciate it.

    (Just to confirm, 500 MHz ~0 dBm output is going into the correct SMA port on the Quad MxFE.)

  • "Boot did not reach spot where it waits for application code"

    The error typically indicates some issue with the device clock.

    Either not present or completely wrong frequency.

    Can you please read:

    root@analog:~# cat /sys/kernel/debug/gpio

    root@analog:~# cat /sys/kernel/debug/clk/clk_summary

    I assume the 4 lock LEDs turn on?

    Can you probe the 4GHz between the HMC606 and the NCR2-123+ ?

    -Michael

     

  • Here's the output of those two cat commands:

    # cat /sys/kernel/debug/gpio
    gpiochip1: GPIOs 384-447, parent: platform/7c440000.gpio, 7c440000.gpio:
     gpio-428 (                    |GPIO_0 HDL mux mode ) in  hi
     gpio-440 (                    |out                 ) out lo
     gpio-441 (                    |out                 ) out lo
     gpio-442 (                    |out                 ) out lo
     gpio-443 (                    |out                 ) out lo
    
    gpiochip0: GPIOs 448-511, parent: platform/40000000.gpio, 40000000.gpio:
     gpio-482 (                    |ADRF5020_CTRL       ) in  lo
     gpio-483 (                    |ctrl                ) out lo
     gpio-484 (                    |ctrl                ) out lo
     gpio-485 (                    |ctrl                ) out lo
     gpio-486 (                    |ctrl                ) out lo

    # cat /sys/kernel/debug/clk/clk_summary
                                     enable  prepare  protect                                duty
       clock                          count    count    count        rate   accuracy phase  cycle  nshot
    ----------------------------------------------------------------------------------------------------
     clock-generator                      0        0        0   148499999          0     0  50000        0
     tx_link_clk                          0        0        0   375000000          0     0  50000        0
     rx_link_clk                          0        0        0   375000000          0     0  50000        0
     tx_lane_clk                          0        0        0    24750000          0     0  50000        0
     rx_lane_clk                          0        0        0    24750000          0     0  50000        0
     refclk_j41                           9        9        0   500000000          0     0  50000        0
        hmc7043_out13                     0        0        0      488281          0     0  50000        0
        hmc7043_out11                     0        0        0      488281          0     0  50000        0
        hmc7043_out9                      0        0        0      488281          0     0  50000        0
        hmc7043_out7                      0        0        0      488281          0     0  50000        0
        hmc7043_out4                      0        0        0   250000000          0     0  50000        0
        hmc7043_out2                      0        0        0   250000000          0     0  50000        0
        hmc7043_out1                      0        0        0      488281          0     0  50000        0
        hmc7043_out0                      0        0        0   250000000          0     0  50000        0
        pll3-clk-rf32                     0        0        0  1600000000          0     0  50000        0
        pll3-clk-rf16                     1        1        0   800000000          0     0  50000        0
        pll3-clk-rfaux8                   0        0        0   400000000          0     0  50000        0
        pll3-clk-rf8                      0        0        0   400000000          0     0  50000        0
        pll2-clk-rf32                     0        0        0  1600000000          0     0  50000        0
        pll2-clk-rf16                     1        1        0   800000000          0     0  50000        0
        pll2-clk-rfaux8                   0        0        0   400000000          0     0  50000        0
        pll2-clk-rf8                      0        0        0   400000000          0     0  50000        0
        pll1-clk-rf32                     0        0        0  1600000000          0     0  50000        0
        pll1-clk-rf16                     1        1        0   800000000          0     0  50000        0
        pll1-clk-rfaux8                   0        0        0   400000000          0     0  50000        0
        pll1-clk-rf8                      0        0        0   400000000          0     0  50000        0
        pll0-clk-rf32                     0        0        0  1600000000          0     0  50000        0
        pll0-clk-rf16                     1        1        0   800000000          0     0  50000        0
        pll0-clk-rfaux8                   0        0        0   400000000          0     0  50000        0
        pll0-clk-rf8                      0        0        0   400000000          0     0  50000        0
     clk_bus_0                            6        6        0   100000000          0     0  50000        0
     clk_cpu                              0        0        0   100000000          0     0  50000        0

    I'll see what I can do about probing the trace between HMC606 and the NCR2-123+ -> we might not have the right probe to do it but I'll see what we have.

    All 4 blue lock LEDs are on.

    EDIT: I've had an ask around but unfortunately we don't have the right probe to probe the trace that should be carrying the 4 GHz.

  • >    pll3-clk-rf16                     1        1 

    It's enabling the wrong output!

    You need to adjust the clock handle to point to the proper output.

    https://github.com/analogdevicesinc/linux/blob/master/arch/microblaze/boot/dts/vcu118_quad_ad9081.dtsi#L491

    This needs to be like this - and likewise for the 3 other clocks.

    /* Clocks */
    clocks = <&adf4371_clk0 1>;

    -Michael

  • Yep that worked, many thanks.

    # cat /sys/kernel/debug/clk/clk_summary
                                     enable  prepare  protect                                duty
       clock                          count    count    count        rate   accuracy phase  cycle  nshot
    ----------------------------------------------------------------------------------------------------
     clock-generator                      0        0        0   148499999          0     0  50000        0
     tx_link_clk                          1        1        0   375000000          0     0  50000        0
     rx_link_clk                          1        1        0   375000000          0     0  50000        0
     tx_lane_clk                          1        1        0    24750000          0     0  50000        0
     rx_lane_clk                          1        1        0    24750000          0     0  50000        0
     refclk_j41                          11       11        0   500000000          0     0  50000        0
        hmc7043_out13                     0        0        0     1953125          0     0  50000        0
        hmc7043_out11                     0        0        0     1953125          0     0  50000        0
        hmc7043_out9                      0        0        0     1953125          0     0  50000        0
        hmc7043_out7                      0        0        0     1953125          0     0  50000        0
        hmc7043_out4                      1        1        0   250000000          0     0  50000        0
        hmc7043_out2                      1        1        0   250000000          0     0  50000        0
        hmc7043_out1                      0        0        0     1953125          0     0  50000        0
        hmc7043_out0                      0        0        0   250000000          0     0  50000        0
        pll3-clk-rf32                     0        0        0  1600000000          0     0  50000        0
        pll3-clk-rf16                     0        0        0   800000000          0     0  50000        0
        pll3-clk-rfaux8                   2        2        0   400000000          0     0  50000        0
           spi0.3-tx_sampl_clk            1        1        0  1000000000          0     0  50000        0
           spi0.3-rx_sampl_clk            0        0        0  1000000000          0     0  50000        0
        pll3-clk-rf8                      0        0        0   400000000          0     0  50000        0
        pll2-clk-rf32                     0        0        0  1600000000          0     0  50000        0
        pll2-clk-rf16                     0        0        0   800000000          0     0  50000        0
        pll2-clk-rfaux8                   1        1        0   400000000          0     0  50000        0
           spi0.2-tx_sampl_clk            0        0        0  1000000000          0     0  50000        0
           spi0.2-rx_sampl_clk            0        0        0  1000000000          0     0  50000        0
        pll2-clk-rf8                      0        0        0   400000000          0     0  50000        0
        pll1-clk-rf32                     0        0        0  1600000000          0     0  50000        0
        pll1-clk-rf16                     0        0        0   800000000          0     0  50000        0
        pll1-clk-rfaux8                   1        1        0   400000000          0     0  50000        0
           spi0.1-tx_sampl_clk            0        0        0  1000000000          0     0  50000        0
           spi0.1-rx_sampl_clk            0        0        0  1000000000          0     0  50000        0
        pll1-clk-rf8                      0        0        0   400000000          0     0  50000        0
        pll0-clk-rf32                     0        0        0  1600000000          0     0  50000        0
        pll0-clk-rf16                     0        0        0   800000000          0     0  50000        0
        pll0-clk-rfaux8                   1        1        0   400000000          0     0  50000        0
           spi0.0-tx_sampl_clk            0        0        0  1000000000          0     0  50000        0
           spi0.0-rx_sampl_clk            0        0        0  1000000000          0     0  50000        0
        pll0-clk-rf8                      0        0        0   400000000          0     0  50000        0
     clk_bus_0                            6        6        0   100000000          0     0  50000        0
     clk_cpu                              0        0        0   100000000          0     0  50000        0
    

    With the clocking working with the RFAUX8 output, in the coming week or so I will dig deeper into getting the bypass operation working.