Device Tree for AD7606 SPI on Raspberry

Some Update about topic:

There is still problem with `raw ERROR: Input/output error (5)`. I connected to Logic Analyzer to SPI and GPIO signals. By trying to use iio_info command and reading in sysfs by cat in_volrageX_raw. More details were observed. Looks transfer of data is working but strange thigs were noticed:

4. The CONVST works opposite than it described in technical manual pic.48. On picture the signal is inverted.

5. Driver transfer first 16 bits and then stops with resetting AD7606. Even If I try to read other channels I can see only first 16 bits and then reset. See pictures below.

6. Looks clock signal and data MISO are not well aligned. 

7. Even if input channel connected to the ground the MISO signal could be FFFF or 0000.

Can anybody help with troubleshooting?

here is reading one channgel:

here is reading all 8 channels by iio_info. Transfer interrupts after each 16 bits.

  I checked conditions when driver set chip in reset state and found problem here. The driver verifies if FIRSTDATA input is high when reading first channel and if it is not then driver creates error and reset the device. It is in function static int ad7606_read_samples of ad7606.c driver file:

static int ad7606_read_samples(struct ad7606_state *st)
{
	unsigned int num = st->chip_info->num_channels - 1;
	u16 *data = st->data;
	int ret;

	/*
	 * The frstdata signal is set to high while and after reading the sample
	 * of the first channel and low for all other channels. This can be used
	 * to check that the incoming data is correctly aligned. During normal
	 * operation the data should never become unaligned, but some glitch or
	 * electrostatic discharge might cause an extra read or clock cycle.
	 * Monitoring the frstdata signal allows to recover from such failure
	 * situations.
	 */

	if (st->gpio_frstdata) {
		ret = st->bops->read_block(st->dev, 1, data);
		if (ret)
			return ret;

		if (!gpiod_get_value(st->gpio_frstdata)) {
			ad7606_reset(st);
			return -EIO;
		}

		data++;
		num--;
	}

	return st->bops->read_block(st->dev, num, data);
}

For some reason idk the driver doesn't see HIGH level on FRSTDATA pin however logic analyzer detect it. Temporary I deleted property adi,conversion-start-gpios in Device tree and data reading works now. Probably FIRSTDATA signal disappears too fast  from input after reading first channel and driver can't detect high level.

  I checked conditions when driver set chip in reset state and found problem here. The driver verifies if FIRSTDATA input is high when reading first channel and if it is not then driver creates error and reset the device. It is in function static int ad7606_read_samples of ad7606.c driver file:

static int ad7606_read_samples(struct ad7606_state *st)
{
	unsigned int num = st->chip_info->num_channels - 1;
	u16 *data = st->data;
	int ret;

	/*
	 * The frstdata signal is set to high while and after reading the sample
	 * of the first channel and low for all other channels. This can be used
	 * to check that the incoming data is correctly aligned. During normal
	 * operation the data should never become unaligned, but some glitch or
	 * electrostatic discharge might cause an extra read or clock cycle.
	 * Monitoring the frstdata signal allows to recover from such failure
	 * situations.
	 */

	if (st->gpio_frstdata) {
		ret = st->bops->read_block(st->dev, 1, data);
		if (ret)
			return ret;

		if (!gpiod_get_value(st->gpio_frstdata)) {
			ad7606_reset(st);
			return -EIO;
		}

		data++;
		num--;
	}

	return st->bops->read_block(st->dev, num, data);
}

For some reason idk the driver doesn't see HIGH level on FRSTDATA pin however logic analyzer detect it. Temporary I deleted property adi,conversion-start-gpios in Device tree and data reading works now. Probably FIRSTDATA signal disappears too fast  from input after reading first channel and driver can't detect high level.