Post Go back to editing

axi-adxcvr (17.05.a) report errors that (16.01.a) doesn't report

Hello,

Same hardware, same driver but different HDL version.

  • Old version log
  • JESD link is enabled on both RX and TX

hmc7044 spi1.2: PLL1: Holdover, CLKIN0 @ 40000000 Hz, PFD: 320 kHz - PLL2: Locked @ 2949.120000 MHz
jesd204: /axi/spi@e0006000/hmc7044@2,jesd204:1,parent=spi1.2: Using as SYSREF provider
axi_adxcvr 44a60000.axi-adxcvr-rx: AXI-ADXCVR-RX (16.01.a) using CPLL on GTX2 at 0x44A60000. Number of lanes: 2.
axi_adxcvr 44a80000.axi-adxcvr-tx: AXI-ADXCVR-TX (16.01.a) using QPLL on GTX2 at 0x44A80000. Number of lanes: 2.
fpga_manager fpga0: Xilinx Zynq FPGA Manager registered
usbcore: registered new interface driver snd-usb-audio
NET: Registered protocol family 10
Segment Routing with IPv6
sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
NET: Registered protocol family 17
NET: Registered protocol family 36
Registering SWP/SWPB emulation handler
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 35, base_baud = 3125000) is a xuartps
printk: console [ttyPS0] enabled
printk: console [ttyPS0] enabled
printk: bootconsole [earlycon0] disabled
printk: bootconsole [earlycon0] disabled
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
adrv9009 spi1.0: adrv9009_probe : enter
cf_axi_dds 44a14000.axi-adrv9009-tx-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.00.b) at 0x44A14000 mapped to 0x(ptrval), probed DDS AD9371
axi-jesd204-rx 44aa0000.axi-jesd204-rx: AXI-JESD204-RX (1.02.a) at 0x44AA0000. Encoder 8b10b, width 4/0, lanes 2, jesd204-fsm.
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition initialized -> probed
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition initialized -> probed
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition probed -> idle
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition probed -> idle
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition idle -> device_init
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition idle -> device_init
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition device_init -> link_init
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition device_init -> link_init
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_pre_setup -> clk_sync_stage1
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_pre_setup -> clk_sync_stage1
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition clk_sync_stage1 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition clk_sync_stage1 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition clk_sync_stage2 -> clk_sync_stage3
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition clk_sync_stage2 -> clk_sync_stage3
adrv9009 spi1.0: ADIHAL_resetHw
random: fast init done
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition clk_sync_stage3 -> link_setup
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition clk_sync_stage3 -> link_setup
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_setup -> opt_setup_stage1
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_setup -> opt_setup_stage1
random: crng init done
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage1 -> opt_setup_stage2
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage1 -> opt_setup_stage2
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage2 -> opt_setup_stage3
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage2 -> opt_setup_stage3
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage3 -> opt_setup_stage4
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage3 -> opt_setup_stage4
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage4 -> opt_setup_stage5
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage4 -> opt_setup_stage5
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage5 -> clocks_enable
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage5 -> clocks_enable
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition clocks_enable -> link_enable
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition clocks_enable -> link_enable
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_enable -> link_running
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_enable -> link_running
adrv9009 spi1.0: ERROR: 40: TALISE_gpIntHandler(): DeframerA reports error
adrv9009 spi1.0: deframerA GCS - Good CheckSum
adrv9009 spi1.0: adrv9009_info: adrv9009 Rev 192, Firmware 6.0.2 API version: 3.6.0.5 successfully initialized via jesd204-fsm
adrv9009 spi1.0: deframerA CSG - Code Group Sync
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_running -> opt_post_running_stage
adrv9009 spi1.0: AUX PLL lock detect reset
adrv9009 spi1.0: RF PLL lock detect reset
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_running -> opt_post_running_stage
adrv9009 spi1.0: ARM Command Wait TimeOut
axi-jesd204-tx 44a90000.axi-jesd204-tx: AXI-JESD204-TX (1.01.a) at 0x44A90000. Encoder 8b10b, width 4/0, lanes 2, jesd204-fsm.
adrv9009 spi1.0: (null)
adrv9009 spi1.0: (null)
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
adrv9009 spi1.0: (null)
adrv9009 spi1.0: GP Interrupt Status 0x20 Action: ERR_RESET_JESD204DEFRAMERA
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
cf_axi_adc 44a00000.axi-adrv9009-rx-hpc: ADI AIM (10.00.b) at 0x44A00000 mapped to 0xb187aace, probed ADC ADRV9009 as MASTER
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
ALSA device list:
  No soundcards found.
Warning: unable to open an initial console.
Freeing unused kernel memory: 44032K
Run /init as init process
axi-jesd204-rx 44aa0000.axi-jesd204-rx: Lane 0 desynced (9 errors), restarting link
axi-jesd204-rx 44aa0000.axi-jesd204-rx: Lane 1 desynced (10 errors), restarting link
udevd[77]: starting version 3.2.9
udevd[78]: starting eudev-3.2.9
axi-jesd204-rx 44aa0000.axi-jesd204-rx: Lane 0 desynced (10 errors), restarting link
axi-jesd204-rx 44aa0000.axi-jesd204-rx: Lane 1 desynced (9 errors), restarting link
samplemodule: loading out-of-tree module taints kernel.
<1>Hello module world : DRIVER !!
<1>Module parameters were (0xdeadbeef) and "default"
<1>Config_of ok.
Sorry, registering the character device  failed with
macb e000b000.ethernet eth0: PHY [e000b000.ethernet-ffffffff:00] driver [Marvell 88E1510] (irq=POLL)
macb e000b000.ethernet eth0: configuring for phy/rgmii-id link mode

hmc7044 spi1.2: PLL1: Holdover, CLKIN0 @ 40000000 Hz, PFD: 320 kHz - PLL2: Locked @ 2949.120000 MHz
jesd204: /axi/spi@e0006000/hmc7044@2,jesd204:1,parent=spi1.2: Using as SYSREF provider
axi_adxcvr 44a60000.axi-adxcvr-rx: AXI-ADXCVR-RX (17.05.a) using CPLL on GTX2 at 0x44A60000. Number of lanes: 2.
axi_adxcvr 44a80000.axi-adxcvr-tx: AXI-ADXCVR-TX (17.05.a) using QPLL on GTX2 at 0x44A80000. Number of lanes: 2.
fpga_manager fpga0: Xilinx Zynq FPGA Manager registered
usbcore: registered new interface driver snd-usb-audio
NET: Registered protocol family 10
Segment Routing with IPv6
sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
NET: Registered protocol family 17
NET: Registered protocol family 36
Registering SWP/SWPB emulation handler
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 35, base_baud = 3125000) is a xuartps
printk: console [ttyPS0] enabled
printk: console [ttyPS0] enabled
printk: bootconsole [earlycon0] disabled
printk: bootconsole [earlycon0] disabled
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
adrv9009 spi1.0: adrv9009_probe : enter
axi-jesd204-rx 44aa0000.axi-jesd204-rx: AXI-JESD204-RX (1.07.a) at 0x44AA0000. Encoder 8b10b, width 4/4, lanes 2, jesd204-fsm.
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition initialized -> probed
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition initialized -> probed
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition probed -> idle
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition probed -> idle
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition idle -> device_init
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition idle -> device_init
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition device_init -> link_init
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition device_init -> link_init
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_pre_setup -> clk_sync_stage1
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_pre_setup -> clk_sync_stage1
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition clk_sync_stage1 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition clk_sync_stage1 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition clk_sync_stage2 -> clk_sync_stage3
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition clk_sync_stage2 -> clk_sync_stage3
adrv9009 spi1.0: ADIHAL_resetHw
random: fast init done
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition clk_sync_stage3 -> link_setup
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition clk_sync_stage3 -> link_setup
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_setup -> opt_setup_stage1
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_setup -> opt_setup_stage1
random: crng init done
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage1 -> opt_setup_stage2
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage1 -> opt_setup_stage2
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage2 -> opt_setup_stage3
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage2 -> opt_setup_stage3
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage3 -> opt_setup_stage4
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage3 -> opt_setup_stage4
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage4 -> opt_setup_stage5
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage4 -> opt_setup_stage5
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage5 -> clocks_enable
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage5 -> clocks_enable
axi_adxcvr 44a60000.axi-adxcvr-rx: adxcvr_clk_enable: CPLL RX buffer underflow error, status: 0x61
axi_adxcvr 44a60000.axi-adxcvr-rx: adxcvr_clk_enable: CPLL RX buffer overflow error, status: 0x61
axi-jesd204-rx 44aa0000.axi-jesd204-rx: axi_jesd204_rx_jesd204_link_enable: Link1 enable lane clock failed (-5)
jesd204: /fpga-axi@0/axi-jesd204-rx@44aa0000,jesd204:2,parent=44aa0000.axi-jesd204-rx: JESD204[1] In link_enable got error from cb: -5 (ignoring!)
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition clocks_enable -> link_enable
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition clocks_enable -> link_enable
axi-jesd204-rx 44aa0000.axi-jesd204-rx: axi_jesd204_rx_jesd204_link_running: Link1 status failed (RESET)
jesd204: /fpga-axi@0/axi-jesd204-rx@44aa0000,jesd204:2,parent=44aa0000.axi-jesd204-rx: JESD204[1] In link_running got error from cb: -1 (ignoring!)
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_enable -> link_running
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_enable -> link_running
adrv9009 spi1.0: ERROR: 40: TALISE_gpIntHandler(): DeframerA reports error
adrv9009 spi1.0: adrv9009_info: adrv9009 Rev 192, Firmware 6.0.2 API version: 3.6.0.5 successfully initialized via jesd204-fsm
adrv9009 spi1.0: deframerA GCS - Good CheckSum
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_running -> opt_post_running_stage
adrv9009 spi1.0: AUX PLL lock detect reset
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_running -> opt_post_running_stage
adrv9009 spi1.0: RF PLL lock detect reset
adrv9009 spi1.0: ARM Command Wait TimeOut
adrv9009 spi1.0: (null)
axi-jesd204-tx 44a90000.axi-jesd204-tx: AXI-JESD204-TX (1.06.a) at 0x44A90000. Encoder 8b10b, width 4/4, lanes 2, jesd204-fsm.
adrv9009 spi1.0: (null)
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
adrv9009 spi1.0: (null)
adrv9009 spi1.0: GP Interrupt Status 0x20 Action: ERR_RESET_JESD204DEFRAMERA
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
cf_axi_adc 44a00000.axi-adrv9009-rx-hpc: ADI AIM (10.01.b) at 0x44A00000 mapped to 0xb94ee0bb, probed ADC ADRV9009 as MASTER
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
ALSA device list:
  No soundcards found.
Warning: unable to open an initial console.
Freeing unused kernel memory: 40960K
Run /init as init process
udevd[79]: starting version 3.2.9
udevd[80]: starting eudev-3.2.9
macb e000b000.ethernet eth0: PHY [e000b000.ethernet-ffffffff:00] driver [Marvell 88E1510] (irq=POLL)
macb e000b000.ethernet eth0: configuring for phy/rgmii-id link mode

I also saw that the register was only added from version 17.5.a AXI_ADXCVR [Analog Devices Wiki]

Regards,

Salah

  • Yes this instrumentation was only recently added. If you run into this that means that something with your clock is wrong.

    In your devicetree can you add jesd204-ignore-errors; to your jesd204-top device?

    jesd204-top-device = <0>; /* This is the TOP device */
    jesd204-ignore-errors;

    This should prevent the jesd204-fsm from rolling back on errors.

    After that can you run jesd_status utility on your RX and post the output?

    -Michael

  • Ok - I tested latest Linux master with HDL from master on ZC706, using GTX2 similar to your setup.

    No errors observed...

    adrv9009 spi0.1: adrv9009_probe : enter
    cf_axi_dds 44a04000.axi-adrv9009-tx-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x44A04000 mapped to 0xab1f755d, probed DDS AD9371
    axi-jesd204-rx 44aa0000.axi-jesd204-rx: AXI-JESD204-RX (1.07.a) at 0x44AA0000. Encoder 8b10b, width 4/4, lanes 2, jesd204-fsm.
    axi-jesd204-rx 44ab0000.axi-jesd204-rx-os: AXI-JESD204-RX (1.07.a) at 0x44AB0000. Encoder 8b10b, width 4/4, lanes 2, jesd204-fsm.
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition initialized -> probed
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition initialized -> probed
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition initialized -> probed
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition probed -> idle
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition probed -> idle
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition probed -> idle
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition idle -> device_init
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition idle -> device_init
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition idle -> device_init
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition device_init -> link_init
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition device_init -> link_init
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition device_init -> link_init
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_init -> link_supported
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_init -> link_supported
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_init -> link_supported
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_supported -> link_pre_setup
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_supported -> link_pre_setup
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_supported -> link_pre_setup
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_pre_setup -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_pre_setup -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_pre_setup -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage1 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage1 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage1 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage2 -> clk_sync_stage3
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage2 -> clk_sync_stage3
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage2 -> clk_sync_stage3
    adrv9009 spi0.1: ADIHAL_resetHw
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage3 -> link_setup
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage3 -> link_setup
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage3 -> link_setup
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_setup -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_setup -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_setup -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage1 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage1 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage1 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage2 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage2 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage2 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage3 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage3 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage3 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage4 -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage4 -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage4 -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition opt_setup_stage5 -> clocks_enable
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition opt_setup_stage5 -> clocks_enable
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition opt_setup_stage5 -> clocks_enable
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clocks_enable -> link_enable
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clocks_enable -> link_enable
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clocks_enable -> link_enable
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_enable -> link_running
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_enable -> link_running
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_enable -> link_running
    adrv9009 spi0.1: adrv9009_info: adrv9009 Rev 192, Firmware 6.0.2 API version: 3.6.0.5 successfully initialized via jesd204-fsm
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_running -> opt_post_running_stage
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_running -> opt_post_running_stage
    jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_running -> opt_post_running_stage
    axi-jesd204-tx 44a90000.axi-jesd204-tx: AXI-JESD204-TX (1.06.a) at 0x44A90000. Encoder 8b10b, width 4/4, lanes 4, jesd204-fsm.
    cf_axi_adc 44a00000.axi-adrv9009-rx-hpc: ADI AIM (10.01.b) at 0x44A00000 mapped to 0x5cc11731, probed ADC ADRV9009 as MASTER
    
    
      (DEVICES) Found 3 JESD204 Link Layer peripherals
    
      (0): axi-jesd204-rx/44ab0000.axi-jesd204-rx-os
      (1): axi-jesd204-rx/44aa0000.axi-jesd204-rx  [*]
      (2): axi-jesd204-tx/44a90000.axi-jesd204-tx
    
      (STATUS)
      Link is                      enabled
      Link Status                  DATA
      Measured Link Clock (MHz)    122.882
      Reported Link Clock (MHz)    122.880
      Measured Device Clock (MHz)  122.882
      Reported Device Clock (MHz)  122.880
      Desired Device Clock (MHz)   122.880
      Lane rate (MHz)              4915.200
      Lane rate / 40 (MHz)         122.880
      LMFC rate (MHz)              3.840
      SYSREF captured              Yes
      SYSREF alignment error       No
      SYNC~
    
      (LANE STATUS)
      Lane#                             0       1
      Errors                            1       0
      Latency (Multiframes/Octets)      2/107   2/106
      CGS State                         DATA    DATA
      Initial Frame Sync                Yes     Yes
      Initial Lane Alignment Sequence   Yes     Yes

    Can you also provide the output form clk_summary?

    root@analog:~# cat /sys/kernel/debug/clk/clk_summary 
                                     enable  prepare  protect                                duty
       clock                          count    count    count        rate   accuracy phase  cycle  nshot
    ----------------------------------------------------------------------------------------------------
     spi0.1-tx_sampl_clk                  1        1        0   122880000          0     0  50000        0
     spi0.1-obs_sampl_clk                 1        1        0   122880000          0     0  50000        0
     spi0.1-rx_sampl_clk                  0        0        0   122880000          0     0  50000        0
     ad9528-1_out3                        0        0        0     1920000          0     0  50000        0
     ad9528-1_out12                       0        0        0     1920000          0     0  50000        0
     ad9528-1_out1                       12       12        6   122880000          0     0  50000        0
        axi_rx_os_clkgen                  1        1        1    61440000          0     0  50000        0
        axi_rx_clkgen                     1        1        1   122880000          0     0  50000        0
        axi_tx_clkgen                     1        1        1    61440000          0     0  50000        0
        tx_out_clk                        0        0        0   122880000          0     0  50000        0
        tx_gt_clk                         1        1        1     2457600          0     0  50000        0
        rx_os_out_clk                     0        0        0   122880000          0     0  50000        0
        rx_os_gt_clk                      1        1        1     2457600          0     0  50000        0
        rx_out_clk                        0        0        0   122880000          0     0  50000        0
        rx_gt_clk                         1        1        1     4915200          0     0  50000        0
     ad9528-1_out13                       1        1        0   122880000          0     0  50000        0
     pcf8563-clkout                       0        0        0       32768          0     0  50000        0
     adrv9009_ext_refclk                  0        0        0    12288000          0     0  50000        0
    

    -Michael

  • Hello Michael,

    jesd204-ignore-errors; is already added as you mentioned it in some other topic.

    • Full log

     

     0
    switch to partitions #0, OK
    mmc0 is current device
    Scanning mmc 0:1...
    Found U-Boot script /boot.scr
    2595 bytes read in 28 ms (89.8 KiB/s)
    ## Executing script at 03000000
    Trying to load boot images from mmc0
    39845448 bytes read in 6514 ms (5.8 MiB/s)
    ## Loading kernel from FIT Image at 10000000 ...
       Using 'conf-system-top.dtb' configuration
       Verifying Hash Integrity ... OK
       Trying 'kernel-1' kernel subimage
         Description:  Linux kernel
         Type:         Kernel Image
         Compression:  uncompressed
         Data Start:   0x10000100
         Data Size:    23487488 Bytes = 22.4 MiB
         Architecture: ARM
         OS:           Linux
         Load Address: 0x00200000
         Entry Point:  0x00200000
         Hash algo:    sha256
         Hash value:   f4c12f9fd76662aec65ae796b63158575b200ecc22269879e8e01bfe652410aa
       Verifying Hash Integrity ... sha256+ OK
    ## Loading ramdisk from FIT Image at 10000000 ...
       Using 'conf-system-top.dtb' configuration
       Verifying Hash Integrity ... OK
       Trying 'ramdisk-1' ramdisk subimage
         Description:  petalinux-image-minimal
         Type:         RAMDisk Image
         Compression:  uncompressed
         Data Start:   0x116724b4
         Data Size:    16307232 Bytes = 15.6 MiB
         Architecture: ARM
         OS:           Linux
         Load Address: unavailable
         Entry Point:  unavailable
         Hash algo:    sha256
         Hash value:   102a74fd634683da90eba8d653376ce519a0562f4b69e993ca20ec3f7b331444
       Verifying Hash Integrity ... sha256+ OK
    ## Loading fdt from FIT Image at 10000000 ...
       Using 'conf-system-top.dtb' configuration
       Verifying Hash Integrity ... OK
       Trying 'fdt-system-top.dtb' fdt subimage
         Description:  Flattened Device Tree blob
         Type:         Flat Device Tree
         Compression:  uncompressed
         Data Start:   0x1166660c
         Data Size:    48603 Bytes = 47.5 KiB
         Architecture: ARM
         Hash algo:    sha256
         Hash value:   778e44560e5ca164d345bc72887736480b0b312115d2f247b0c42654a7f77b2e
       Verifying Hash Integrity ... sha256+ OK
       Booting using the fdt blob at 0x1166660c
       Loading Kernel Image
       Loading Ramdisk to 2f072000, end 2ffff420 ... OK
       Loading Device Tree to 2f063000, end 2f071dda ... OK
    
    Starting kernel ...
    
    Booting Linux on physical CPU 0x0
    Linux version 5.10.0-xilinx-v2021.1 (oe-user@oe-host) (arm-xilinx-linux-gnueabi-gcc (GCC) 10.2.0, GNU ld (GNU Binutils) 2.35.1) #1 SMP PREEMPT Tue Jan 18 08:22:36 UTC 2022
    CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
    CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
    OF: fdt: Machine model: Xilinx ZC706 board
    printk: bootconsole [earlycon0] enabled
    Memory policy: Data cache writealloc
    INITRD: 0x00800000+0x01000000 overlaps in-use memory region - disabling initrd
    cma: Reserved 128 MiB at 0x38000000
    Zone ranges:
      Normal   [mem 0x0000000000000000-0x000000002fffffff]
      HighMem  [mem 0x0000000030000000-0x000000003fffffff]
    Movable zone start for each node
    Early memory node ranges
      node   0: [mem 0x0000000000000000-0x000000003fffffff]
    Initmem setup node 0 [mem 0x0000000000000000-0x000000003fffffff]
    percpu: Embedded 15 pages/cpu s30028 r8192 d23220 u61440
    Built 1 zonelists, mobility grouping on.  Total pages: 260416
    Kernel command line: console=ttyPS0,115200n8 root=/dev/ram rw initrd=0x00800000,16M earlyprintk mtdparts=physmap-flash.0:512K(nor-fsbl),512K(nor-u-boot),5M(nor-linux),9M(nor-user),1M(nor-scratch),-(nor-rootfs)
    Dentry cache hash table entries: 131072 (order: 7, 524288 bytes, linear)
    Inode-cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
    mem auto-init: stack:off, heap alloc:off, heap free:off
    Memory: 830432K/1048576K available (10240K kernel code, 800K rwdata, 7204K rodata, 40960K init, 172K bss, 87072K reserved, 131072K cma-reserved, 131072K highmem)
    rcu: Preemptible hierarchical RCU implementation.
    rcu:    RCU event tracing is enabled.
    rcu:    RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
            Trampoline variant of Tasks RCU enabled.
    rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
    rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
    NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
    efuse mapped to (ptrval)
    slcr mapped to (ptrval)
    L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
    L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
    L2C-310 erratum 769419 enabled
    L2C-310 enabling early BRESP for Cortex-A9
    L2C-310 full line of zeros enabled for Cortex-A9
    L2C-310 ID prefetch enabled, offset 1 lines
    L2C-310 dynamic clock gating enabled, standby mode enabled
    L2C-310 cache controller enabled, 8 ways, 512 kB
    L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
    random: get_random_bytes called from start_kernel+0x33c/0x4e8 with crng_init=0
    zynq_clock_init: clkc starts at (ptrval)
    Zynq clock init
    ps_clk frequency not specified, using 33 MHz.
    sched_clock: 64 bits at 399MHz, resolution 2ns, wraps every 4398046511103ns
    clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x5c4093a7d1, max_idle_ns: 440795210635 ns
    Switching to timer-based delay loop, resolution 2ns
    clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 447945978 ns
    timer #0 at (ptrval), irq=25
    Console: colour dummy device 80x30
    Calibrating delay loop (skipped), value calculated using timer frequency.. 799.99 BogoMIPS (lpj=3999999)
    pid_max: default: 32768 minimum: 301
    Mount-cache hash table entries: 2048 (order: 1, 8192 bytes, linear)
    Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes, linear)
    CPU: Testing write buffer coherency: ok
    CPU0: Spectre v2: using BPIALL workaround
    CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
    Setting up static identity map for 0x100000 - 0x100060
    rcu: Hierarchical SRCU implementation.
    smp: Bringing up secondary CPUs ...
    CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
    CPU1: Spectre v2: using BPIALL workaround
    smp: Brought up 1 node, 2 CPUs
    SMP: Total of 2 processors activated (1599.99 BogoMIPS).
    CPU: All CPU(s) started in SVC mode.
    devtmpfs: initialized
    VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
    clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
    futex hash table entries: 512 (order: 3, 32768 bytes, linear)
    pinctrl core: initialized pinctrl subsystem
    NET: Registered protocol family 16
    DMA: preallocated 256 KiB pool for atomic coherent allocations
    thermal_sys: Registered thermal governor 'step_wise'
    cpuidle: using governor ladder
    irq: type mismatch, failed to map hwirq-88 for interrupt-controller@f8f01000!
    hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
    hw-breakpoint: maximum watchpoint size is 4 bytes.
    zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0x(ptrval)
    SCSI subsystem initialized
    usbcore: registered new interface driver usbfs
    usbcore: registered new interface driver hub
    usbcore: registered new device driver usb
    mc: Linux media interface: v0.10
    videodev: Linux video capture interface: v2.00
    jesd204: created con: id=0, topo=0, link=0, /axi/spi@e0006000/hmc7044@2 <-> /fpga-axi@0/axi-adxcvr-tx@44a80000
    jesd204: created con: id=1, topo=0, link=1, /axi/spi@e0006000/hmc7044@2 <-> /fpga-axi@0/axi-adxcvr-rx@44a60000
    jesd204: created con: id=2, topo=0, link=0, /fpga-axi@0/axi-adxcvr-tx@44a80000 <-> /fpga-axi@0/axi-jesd204-tx@44a90000
    jesd204: created con: id=3, topo=0, link=1, /fpga-axi@0/axi-adxcvr-rx@44a60000 <-> /fpga-axi@0/axi-jesd204-rx@44aa0000
    jesd204: created con: id=4, topo=0, link=1, /fpga-axi@0/axi-jesd204-rx@44aa0000 <-> /axi/spi@e0006000/adrv9009-phy@0
    jesd204: created con: id=5, topo=0, link=0, /fpga-axi@0/axi-jesd204-tx@44a90000 <-> /axi/spi@e0006000/adrv9009-phy@0
    jesd204: /axi/spi@e0006000/adrv9009-phy@0: JESD204[0] transition uninitialized -> initialized
    jesd204: /axi/spi@e0006000/adrv9009-phy@0: JESD204[1] transition uninitialized -> initialized
    jesd204: found 6 devices and 1 topologies
    FPGA manager framework
    Advanced Linux Sound Architecture Driver Initialized.
    clocksource: Switched to clocksource arm_global_timer
    NET: Registered protocol family 2
    tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes, linear)
    TCP established hash table entries: 8192 (order: 3, 32768 bytes, linear)
    TCP bind hash table entries: 8192 (order: 4, 65536 bytes, linear)
    TCP: Hash tables configured (established 8192 bind 8192)
    UDP hash table entries: 512 (order: 2, 16384 bytes, linear)
    UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear)
    NET: Registered protocol family 1
    hw perfevents: no interrupt-affinity property for /pmu@f8891000, guessing.
    hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
    workingset: timestamp_bits=14 max_order=18 bucket_order=4
    bounce: pool size: 64 pages
    io scheduler mq-deadline registered
    io scheduler kyber registered
    zynq-pinctrl 700.pinctrl: zynq pinctrl initialized
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    irq: type mismatch, failed to map hwirq-88 for interrupt-controller@f8f01000!
    dma-axi-dmac 7c420000.tx-dmac: IRQ index 0 not found
    dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-241330
    dma-pl330 f8003000.dmac:        DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
    brd: module loaded
    loop: module loaded
    Registered mathworks_ip class
    spi-nor spi0.0: unrecognized JEDEC id bytes: 00 00 00 00 00 00
    MACsec IEEE 802.1AE
    libphy: Fixed MDIO Bus: probed
    tun: Universal TUN/TAP device driver, 1.6
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    libphy: MACB_mii_bus: probed
    macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 38 (a2:ee:4d:d9:6d:dd)
    usbcore: registered new interface driver asix
    usbcore: registered new interface driver ax88179_178a
    usbcore: registered new interface driver cdc_ether
    usbcore: registered new interface driver net1080
    usbcore: registered new interface driver cdc_subset
    usbcore: registered new interface driver zaurus
    usbcore: registered new interface driver cdc_ncm
    ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
    usbcore: registered new interface driver uas
    usbcore: registered new interface driver usb-storage
    usbcore: registered new interface driver usbserial_generic
    usbserial: USB Serial support registered for generic
    usbcore: registered new interface driver ftdi_sio
    usbserial: USB Serial support registered for FTDI USB Serial Device
    usbcore: registered new interface driver upd78f0730
    usbserial: USB Serial support registered for upd78f0730
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    i2c /dev entries driver
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    cdns-i2c e0004000.i2c: 400 kHz mmio e0004000 irq 32
    pca954x 0-0074: probe failed
    usbcore: registered new interface driver uvcvideo
    USB Video Class driver (1.1.1)
    gspca_main: v2.14.0 registered
    cdns-wdt f8005000.watchdog: Xilinx Watchdog Timer with timeout 10s
    Xilinx Zynq CpuIdle Driver started
    sdhci: Secure Digital Host Controller Interface driver
    sdhci: Copyright(c) Pierre Ossman
    sdhci-pltfm: SDHCI platform and OF driver helper
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    ledtrig-cpu: registered to indicate activity on CPUs
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    hid: raw HID events driver (C) Jiri Kosina
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    usbcore: registered new interface driver usbhid
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    usbhid: USB HID core driver
    adrv9009 spi1.0: adrv9009_probe : enter
    mmc0: SDHCI controller on e0100000.mmc [e0100000.mmc] using ADMA
    hmc7044 spi1.2: PLL1: Holdover, CLKIN0 @ 40000000 Hz, PFD: 320 kHz - PLL2: Locked @ 2949.120000 MHz
    jesd204: /axi/spi@e0006000/hmc7044@2,jesd204:1,parent=spi1.2: Using as SYSREF provider
    axi_adxcvr 44a60000.axi-adxcvr-rx: AXI-ADXCVR-RX (17.05.a) using CPLL on GTX2 at 0x44A60000. Number of lanes: 2.
    axi_adxcvr 44a80000.axi-adxcvr-tx: AXI-ADXCVR-TX (17.05.a) using QPLL on GTX2 at 0x44A80000. Number of lanes: 2.
    fpga_manager fpga0: Xilinx Zynq FPGA Manager registered
    usbcore: registered new interface driver snd-usb-audio
    NET: Registered protocol family 10
    Segment Routing with IPv6
    sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
    NET: Registered protocol family 17
    NET: Registered protocol family 36
    Registering SWP/SWPB emulation handler
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 35, base_baud = 3125000) is a xuartps
    printk: console [ttyPS0] enabled
    printk: console [ttyPS0] enabled
    printk: bootconsole [earlycon0] disabled
    printk: bootconsole [earlycon0] disabled
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    adrv9009 spi1.0: adrv9009_probe : enter
    axi-jesd204-rx 44aa0000.axi-jesd204-rx: AXI-JESD204-RX (1.07.a) at 0x44AA0000. Encoder 8b10b, width 4/4, lanes 2, jesd204-fsm.
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition initialized -> probed
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition initialized -> probed
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition probed -> idle
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition probed -> idle
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition idle -> device_init
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition idle -> device_init
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition device_init -> link_init
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition device_init -> link_init
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_init -> link_supported
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_init -> link_supported
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_supported -> link_pre_setup
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_supported -> link_pre_setup
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_pre_setup -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_pre_setup -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition clk_sync_stage1 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition clk_sync_stage1 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition clk_sync_stage2 -> clk_sync_stage3
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition clk_sync_stage2 -> clk_sync_stage3
    adrv9009 spi1.0: ADIHAL_resetHw
    random: fast init done
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition clk_sync_stage3 -> link_setup
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition clk_sync_stage3 -> link_setup
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_setup -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_setup -> opt_setup_stage1
    random: crng init done
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage1 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage1 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage2 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage2 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage3 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage3 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage4 -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage4 -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage5 -> clocks_enable
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage5 -> clocks_enable
    axi_adxcvr 44a60000.axi-adxcvr-rx: adxcvr_clk_enable: CPLL RX buffer underflow error, status: 0x61
    axi_adxcvr 44a60000.axi-adxcvr-rx: adxcvr_clk_enable: CPLL RX buffer overflow error, status: 0x61
    axi-jesd204-rx 44aa0000.axi-jesd204-rx: axi_jesd204_rx_jesd204_link_enable: Link1 enable lane clock failed (-5)
    jesd204: /fpga-axi@0/axi-jesd204-rx@44aa0000,jesd204:2,parent=44aa0000.axi-jesd204-rx: JESD204[1] In link_enable got error from cb: -5 (ignoring!)
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition clocks_enable -> link_enable
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition clocks_enable -> link_enable
    axi-jesd204-rx 44aa0000.axi-jesd204-rx: axi_jesd204_rx_jesd204_link_running: Link1 status failed (RESET)
    jesd204: /fpga-axi@0/axi-jesd204-rx@44aa0000,jesd204:2,parent=44aa0000.axi-jesd204-rx: JESD204[1] In link_running got error from cb: -1 (ignoring!)
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_enable -> link_running
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_enable -> link_running
    adrv9009 spi1.0: ERROR: 40: TALISE_gpIntHandler(): DeframerA reports error
    adrv9009 spi1.0: adrv9009_info: adrv9009 Rev 192, Firmware 6.0.2 API version: 3.6.0.5 successfully initialized via jesd204-fsm
    adrv9009 spi1.0: deframerA GCS - Good CheckSum
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_running -> opt_post_running_stage
    adrv9009 spi1.0: AUX PLL lock detect reset
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_running -> opt_post_running_stage
    adrv9009 spi1.0: RF PLL lock detect reset
    adrv9009 spi1.0: ARM Command Wait TimeOut
    adrv9009 spi1.0: (null)
    axi-jesd204-tx 44a90000.axi-jesd204-tx: AXI-JESD204-TX (1.06.a) at 0x44A90000. Encoder 8b10b, width 4/4, lanes 2, jesd204-fsm.
    adrv9009 spi1.0: GP Interrupt Status 0x20 Action: ERR_RESET_JESD204DEFRAMERA
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    cf_axi_adc 44a00000.axi-adrv9009-rx-hpc: ADI AIM (10.01.b) at 0x44A00000 mapped to 0xe62427a6, probed ADC ADRV9009 as MASTER
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    ALSA device list:
      No soundcards found.
    Warning: unable to open an initial console.
    Freeing unused kernel memory: 40960K
    Run /init as init process
    udevd[79]: starting version 3.2.9
    udevd[80]: starting eudev-3.2.9
    macb e000b000.ethernet eth0: PHY [e000b000.ethernet-ffffffff:00] driver [Marvell 88E1510] (irq=POLL)
    macb e000b000.ethernet eth0: configuring for phy/rgmii-id link mode

    • jesd_status 

    • clk_summary

    root@ETRX:~# cat /sys/kernel/debug/clk/clk_summary
                                     enable  prepare  protect                                duty
       clock                          count    count    count        rate   accuracy phase  cycle  nshot
    ----------------------------------------------------------------------------------------------------
     spi1.0-tx_sampl_clk                  0        0        0   122880000          0     0  50000        0
     spi1.0-obs_sampl_clk                 0        0        0   122880000          0     0  50000        0
     spi1.0-rx_sampl_clk                  0        0        0   122880000          0     0  50000        0
     hmc7044_out9_FPGA_SYSREF_RX_AB       0        0        0     3840000          0     0  50000        0
     hmc7044_out8_FPGA_SYSREF_TX_OBS_AB       0        0        0     3840000          0     0  50000        0
     hmc7044_out5_JESD_REFCLK_RX_AB       0        0        0   245760000          0     0  50000        0
     hmc7044_out4_JESD_REFCLK_TX_OBS_AB       7        7        3   245760000          0     0  50000        0
        axi_rx_clkgen                     1        1        1   122880000          0     0  50000        0
        axi_tx_clkgen                     1        1        1   122880000          0     0  50000        0
        tx_out_clk                        0        0        0   245760000          0     0  50000        0
        tx_gt_clk                         1        1        1     4915200          0     0  50000        0
        rx_out_clk                        0        0        0   245760000          0     0  50000        0
        rx_gt_clk                         0        0        0     4915200          0     0  50000        0
     hmc7044_out3_DEV_SYSREF_B            0        0        0     3840000          0     0  50000        0
     hmc7044_out2_DEV_REFCLK_B            0        0        0   245760000          0     0  50000        0
     hmc7044_out1_DEV_SYSREF_A            0        0        0     3840000          0     0  50000        0
     hmc7044_out0_DEV_REFCLK_A            1        1        0   245760000          0     0  50000        0
     adrv9009_ext_refclk                  0        0        0    12288000          0     0  50000        0

    Indeed rx_gt_clk is 0, it may be related to xcvr settings.

    Regards,

    Salah

  • Where are you connecting the axi_rx_clkgen to the adxcvr driver or to the jesd_rx?

    Can you share your devicetree?

    -Michael

  • Here is the relevant device tree file 

    // SPDX-License-Identifier: GPL-2.0
    /*
     * Analog Devices ADRV9009
     * https://wiki.analog.com/resources/eval/user-guides/adrv9009
     * https://wiki.analog.com/resources/tools-software/linux-drivers/iio-transceiver/adrv9009
     * https://wiki.analog.com/resources/tools-software/linux-software/adrv9009_advanced_plugin
     *
     * hdl_project: <adrv9009/zc706>
     * board_revision: <>
     *
     * Copyright (C) 2019 Analog Devices Inc.
     */
    #include "zynq-zc706.dtsi"
    //#include "zynq-7000.dtsi"
    //#include "zc706.dtsi"
    
    #include "zynq-zc706-adv7511_mod.dtsi"
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/jesd204/adxcvr.h>
    
    //&i2c_mux {
    //	i2c@5 { /* HPC IIC */
    //		#address-cells = <1>;
    //		#size-cells = <0>;
    //		reg = <5>;
    //
    //		eeprom@50 {
    //			compatible = "at24,24c02";
    //			reg = <0x50>;
    //		};
    //
    //		eeprom@54 {
    //			compatible = "at24,24c02";
    //			reg = <0x54>;
    //		};
    //
    //		ad7291@2f {
    //			compatible = "adi,ad7291";
    //			reg = <0x2f>;
    //		};
    //	};
    //};
    
    &fpga_axi {
    	rx_dma: rx-dmac@7c400000 {
    		compatible = "adi,axi-dmac-1.00.a";
    		reg = <0x7c400000 0x10000>;
    		#dma-cells = <1>;
    		interrupt-parent = <&intc>;
    		interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
    		clocks = <&clkc 16>;
    
    		adi,channels {
    			#size-cells = <0>;
    			#address-cells = <1>;
    
    			dma-channel@0 {
    				reg = <0>;
    				adi,source-bus-width = <64>;
    				adi,source-bus-type = <2>;
    				adi,destination-bus-width = <64>;
    				adi,destination-bus-type = <0>;
    			};
    		};
    	};
    
    //	rx_obs_dma: rx-obs-dmac@7c440000  {
    //		compatible = "adi,axi-dmac-1.00.a";
    //		reg = <0x7c440000  0x10000>;
    //		#dma-cells = <1>;
    //		interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
    //		clocks = <&clkc 16>;
    //
    //		adi,channels {
    //			#size-cells = <0>;
    //			#address-cells = <1>;
    //
    //			dma-channel@0 {
    //				reg = <0>;
    //				adi,source-bus-width = <128>;
    //				adi,source-bus-type = <2>;
    //				adi,destination-bus-width = <64>;
    //				adi,destination-bus-type = <0>;
    //			};
    //		};
    //	};
    
    	tx_dma: tx-dmac@7c420000 {
    		compatible = "adi,axi-dmac-1.00.a";
    		reg = <0x7c420000 0x10000>;
    		#dma-cells = <1>;
    		interrupt-parent = <&intc>;
    		interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
    		clocks = <&clkc 16>;
    
    		adi,channels {
    			#size-cells = <0>;
    			#address-cells = <1>;
    
    			dma-channel@0 {
    				reg = <0>;
    				adi,source-bus-width = <64>;
    				adi,source-bus-type = <0>;
    				adi,destination-bus-width = <64>;
    				adi,destination-bus-type = <1>;
    			};
    		};
    	};
    
    	axi_adrv9009_core_rx: axi-adrv9009-rx-hpc@44a00000 {
    		compatible = "adi,axi-adrv9009-rx-1.0";
    		reg = <0x44a00000 0x10000>;
    		dmas = <&rx_dma 0>;
    		dma-names = "rx";
    		spibus-connected = <&trx0_adrv9009>;
    		adi,axi-decimation-core-available;
    		decimation-gpios = <&gpio0 115 GPIO_ACTIVE_HIGH>;
    	};
    
    //	axi_adrv9009_core_rx_obs: axi-adrv9009-rx-obs-hpc@44a08000 {
    //		compatible = "adi,axi-adrv9009-obs-1.0";
    //		reg = <0x44a08000 0x1000>;
    //		dmas = <&rx_obs_dma 0>;
    //		dma-names = "rx";
    //		clocks = <&trx0_adrv9009 1>;
    //		clock-names = "sampl_clk";
    //	};
    
    	axi_adrv9009_core_tx: axi-adrv9009-tx-hpc@44a14000 {
    		compatible = "adi,axi-adrv9009-tx-1.0";
    		reg = <0x44a14000 0x10000>;
    		dmas = <&tx_dma 0>;
    		dma-names = "tx";
    		clocks = <&trx0_adrv9009 2>;
    		clock-names = "sampl_clk";
    		spibus-connected = <&trx0_adrv9009>;
    		adi,axi-pl-fifo-enable;
    		adi,axi-interpolation-core-available;
    		interpolation-gpios = <&gpio0 116 GPIO_ACTIVE_HIGH>;
    	};
    
    	axi_adrv9009_rx_jesd: axi-jesd204-rx@44aa0000 {
    		compatible = "adi,axi-jesd204-rx-1.0";
    		reg = <0x44aa0000 0x4000>;
    		interrupt-parent = <&intc>;
    		interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
    
    		clocks = <&clkc 16>, <&axi_rx_clkgen>, <&axi_adrv9009_adxcvr_rx 0>;
    		//clocks = <&clkc 16>, <&hmc7044 1>, <&axi_adrv9009_adxcvr_rx 0>;
    		clock-names = "s_axi_aclk", "device_clk", "lane_clk";
    
    		#clock-cells = <0>;
    		clock-output-names = "jesd_rx_lane_clk";
    
    		adi,octets-per-frame = <4>;
    		adi,frames-per-multiframe = <32>;
    	};
    
    	axi_adrv9009_tx_jesd: axi-jesd204-tx@44a90000 {
    		compatible = "adi,axi-jesd204-tx-1.0";
    		reg = <0x44a90000 0x4000>;
    		interrupt-parent = <&intc>;
    		interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>;
    
    		clocks = <&clkc 16>, <&axi_tx_clkgen>, <&axi_adrv9009_adxcvr_tx 0>;
    		//clocks = <&clkc 16>, <&hmc7044 1>, <&axi_adrv9009_adxcvr_tx 0>;
    		clock-names = "s_axi_aclk", "device_clk", "lane_clk";
    
    		#clock-cells = <0>;
    		clock-output-names = "jesd_tx_lane_clk";
    
    		adi,octets-per-frame = <2>;
    		adi,frames-per-multiframe = <32>;
    		adi,converter-resolution = <16>;
    		adi,bits-per-sample = <16>;
    		adi,converters-per-device = <4>;
    		adi,control-bits-per-sample = <0>;
    	};
    
    //	axi_adrv9009_rx_os_jesd: axi-jesd204-rx-os@44ab0000 {
    //		compatible = "adi,axi-jesd204-rx-1.0";
    //		reg = <0x44ab0000 0x1000>;
    //
    //		interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
    //
    //		clocks = <&clkc 16>, <&axi_rx_os_clkgen>, <&axi_adrv9009_adxcvr_rx_os 0>;
    //		clock-names = "s_axi_aclk", "device_clk", "lane_clk";
    //
    //		#clock-cells = <0>;
    //		clock-output-names = "jesd_rx_os_lane_clk";
    //
    //		adi,octets-per-frame = <4>;
    //		adi,frames-per-multiframe = <32>;
    //	};
    
    	axi_tx_clkgen: axi-clkgen@43c00000  {
    		compatible = "adi,axi-clkgen-2.00.a";
    		reg = <0x43c00000 0x10000>;
    		#clock-cells = <0>;
    		clocks = <&clkc 15>, <&hmc7044 4>;
    		clock-names = "s_axi_aclk", "clkin1";
    		clock-output-names = "axi_tx_clkgen";
    	};
    
    	axi_rx_clkgen: axi-clkgen@43c10000  {
    		compatible = "adi,axi-clkgen-2.00.a";
    		reg = <0x43c10000 0x10000>;
    		#clock-cells = <0>;
    		clocks = <&clkc 15>, <&hmc7044 4>;
    		clock-names = "s_axi_aclk", "clkin1";
    		clock-output-names = "axi_rx_clkgen";
    	};
    
    //	axi_rx_os_clkgen: axi-clkgen@43c20000  {
    //		compatible = "adi,axi-clkgen-2.00.a";
    //		reg = <0x43c20000 0x10000>;
    //		#clock-cells = <0>;
    //		clocks = <&clkc 15>, <&clk0_ad9528 1>;
    //		clock-names = "s_axi_aclk", "clkin1";
    //		clock-output-names = "axi_rx_os_clkgen";
    //	};
    
    	axi_adrv9009_adxcvr_rx: axi-adxcvr-rx@44a60000 {
    		#address-cells = <1>;
    		#size-cells = <0>;
    		compatible = "adi,axi-adxcvr-1.0";
    		reg = <0x44a60000 0x10000>;
    
    		//clocks = <&hmc7044 1>, <&axi_rx_clkgen 0>;
    		clocks = <&hmc7044 4>;
    		//clock-names = "conv", "div40";
    		clock-names = "conv";
    
    		#clock-cells = <1>;
    		clock-output-names = "rx_gt_clk", "rx_out_clk";
    
    		adi,sys-clk-select = <XCVR_CPLL>;
    		adi,out-clk-select = <XCVR_REFCLK>;
    		adi,use-lpm-enable;
    	};
    
    //	axi_adrv9009_adxcvr_rx_os: axi-adxcvr-rx-os@44a50000 {
    //		#address-cells = <1>;
    //		#size-cells = <0>;
    //		compatible = "adi,axi-adxcvr-1.0";
    //		reg = <0x44a50000 0x1000>;
    //
    //		clocks = <&clk0_ad9528 1>, <&axi_rx_os_clkgen>;
    //		clock-names = "conv", "div40";
    //
    //		#clock-cells = <1>;
    //		clock-output-names = "rx_os_gt_clk", "rx_os_out_clk";
    //
    //		adi,sys-clk-select = <XCVR_CPLL>;
    //		adi,out-clk-select = <XCVR_REFCLK>;
    //		adi,use-lpm-enable;
    //	};
    
    	axi_adrv9009_adxcvr_tx: axi-adxcvr-tx@44a80000 {
    		#address-cells = <1>;
    		#size-cells = <0>;
    		compatible = "adi,axi-adxcvr-1.0";
    		reg = <0x44a80000 0x10000>;
    
    		//clocks = <&hmc7044 1>, <&axi_tx_clkgen>;
    		clocks = <&hmc7044 4>;
    		//clock-names = "conv", "div40";
    		clock-names = "conv";
    
    		#clock-cells = <1>;
    		clock-output-names = "tx_gt_clk", "tx_out_clk";
    
    		adi,sys-clk-select = <XCVR_QPLL>;
    		adi,out-clk-select = <XCVR_REFCLK>;
    	};
    };
    
    &spi0 {
    	status = "okay";
    };
    
    #define fmc_spi spi0
    
    #include "adi-adrv9009_mod.dtsi"
    
    // adrv9009_dac_fifo_bypass_s 60   						// 114
    // ad9528_reset_b,       // 59 //hmc7044_reset_b        // 113 
    // ad9528_sysref_req,    // 58 //hmc7044_sysref_req     // 112
    // adrv9009_tx1_enable,    // 57						// 111
    // adrv9009_tx2_enable,    // 56                        // 110                                
    // adrv9009_rx1_enable,    // 55                        // 109                 
    // adrv9009_rx2_enable,    // 54                        // 108                 
    // adrv9009_test,          // 53                        // 107                 
    // adrv9009_reset_b,       // 52                        // 106                 
    // adrv9009_gpint,         // 51                        // 105                 
    // adrv9009_gpio_00,       // 50                        // 104                 
    // adrv9009_gpio_01,       // 49                        // 103                 
    // adrv9009_gpio_02,       // 48                        // 102                 
    // adrv9009_gpio_03,       // 47                        // 101                 
    // adrv9009_gpio_04,       // 46                        // 100                 
    // adrv9009_gpio_05,       // 45                        // 99                 
    // adrv9009_gpio_06,       // 44                                         
    // adrv9009_gpio_07,       // 43                                         
    // adrv9009_gpio_15,       // 42                                         
    // adrv9009_gpio_08,       // 41                                         
    // adrv9009_gpio_09,       // 40                                         
    // adrv9009_gpio_10,       // 39                                         
    // adrv9009_gpio_11,       // 38                                         
    // adrv9009_gpio_12,       // 37                                         
    // adrv9009_gpio_14,       // 36                                         
    // adrv9009_gpio_13,       // 35                                         
    // adrv9009_gpio_17,       // 34                                         
    // adrv9009_gpio_16,       // 33                                         
    // adrv9009_gpio_18}));    // 32 + 54
    
    //&trx0_adrv9009 {
    //	reset-gpios = <&gpio0 106 0>;
    //	test-gpios = <&gpio0 107 0>;
    //	sysref-req-gpios = <&gpio0 112 0>;
    //	rx2-enable-gpios = <&gpio0 108 0>;
    //	rx1-enable-gpios = <&gpio0 109 0>;
    //	tx2-enable-gpios = <&gpio0 110 0>;
    //	tx1-enable-gpios = <&gpio0 111 0>;
    //};
    
    //&hmc7044 {
    //	reset-gpios = <&gpio0 113 0>;
    //};
    
    &amba_pl{
    	samplemodule_instance: samplemodule {
    		compatible = "etelm,samplemodule";
    		reg = <0x40000000 0x20000>;
    		etelm,reg_gpio0 = <0x41200000 0x1000>;
    		etelm,mem_tx   = <0x40000000 0x20000>;
    		interrupt-parent = <&intc>;
    		interrupts = < 0 56 1 >;
    	};
    };

    Salah

  • Is this correct that you drive both Rx and Tx from hmc7044_out4 ?

    If you comment these lines which return the over/under run error, your links come up?

    -Michael 

  • Is this correct that you drive both Rx and Tx from hmc7044_out4 ?

    Yes, same config work with older HDL

    If you comment these lines which return the over/under run error, your links come up?

    I tried old adxcvr_clk_enable function that have no check on those bits but axi_jesd204_rx_jesd204_link_enable report error and RX link wont come up

    axi-jesd204-rx 44aa0000.axi-jesd204-rx: AXI-JESD204-RX (1.07.a) at 0x44AA0000. Encoder 8b10b, width 4/4, lanes 2, jesd204-fsm.
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition initialized -> probed
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition initialized -> probed
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition probed -> idle
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition probed -> idle
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition idle -> device_init
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition idle -> device_init
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition device_init -> link_init
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition device_init -> link_init
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_init -> link_supported
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_init -> link_supported
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_supported -> link_pre_setup
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_supported -> link_pre_setup
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_pre_setup -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_pre_setup -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition clk_sync_stage1 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition clk_sync_stage1 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition clk_sync_stage2 -> clk_sync_stage3
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition clk_sync_stage2 -> clk_sync_stage3
    adrv9009 spi1.0: ADIHAL_resetHw
    random: fast init done
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition clk_sync_stage3 -> link_setup
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition clk_sync_stage3 -> link_setup
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_setup -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_setup -> opt_setup_stage1
    random: crng init done
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage1 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage1 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage2 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage2 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage3 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage3 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage4 -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage4 -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage5 -> clocks_enable
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage5 -> clocks_enable
    axi-jesd204-rx 44aa0000.axi-jesd204-rx: axi_jesd204_rx_jesd204_link_enable: Link1 enable lane clock failed (-5)
    jesd204: /fpga-axi@0/axi-jesd204-rx@44aa0000,jesd204:2,parent=44aa0000.axi-jesd204-rx: JESD204[1] In link_enable got error from cb: -5 (ignoring!)
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition clocks_enable -> link_enable
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition clocks_enable -> link_enable
    axi-jesd204-rx 44aa0000.axi-jesd204-rx: axi_jesd204_rx_jesd204_link_running: Link1 status failed (RESET)
    jesd204: /fpga-axi@0/axi-jesd204-rx@44aa0000,jesd204:2,parent=44aa0000.axi-jesd204-rx: JESD204[1] In link_running got error from cb: -1 (ignoring!)
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_enable -> link_running
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_enable -> link_running

    Salah

  • Hi Salah,

    in HDL what clock drives the util_adxcv   rx_clk_<*>   pins  ?

    Are you using a axi_clkgen  module to get the above clock and the device clock  of the link layer?

    If so, it could happen the axi_clkgen   is not ready (PLL not locked) when  the util_adxcvr is reset and cause the buffer over/under runs.

    For test try setting the ref clock ( hmc7044_out4) to 122 MHz so the   axi_clkgen    don't have to be reprogrammed.

    Also make sure you have the following patch:

    https://github.com/analogdevicesinc/linux/commit/9a902a41643845442eeadb6eb71920501d706f50

    Laszlo

  • Hi Laszlo,

    in HDL what clock drives the util_adxcv   rx_clk_<*>   pins  ?

    Are you using a axi_clkgen  module to get the above clock and the device clock  of the link layer?

    Yes, rx_clk_0 and rx_clk_1 are provided by clk_gen.

    If so, it could happen the axi_clkgen   is not ready (PLL not locked) when  the util_adxcvr is reset and cause the buffer over/under runs.

    How come is it working on older HDL ? 

      How is the order managed in terms of what driver is load up first ?

    For test try setting the ref clock ( hmc7044_out4) to 122 MHz so the   axi_clkgen    don't have to be reprogrammed.

    Here is my hmc setup

    	hmc7044: hmc7044@2 {
    		#address-cells = <1>;
    		#size-cells = <0>;		
    		#clock-cells = <1>;
    
    		compatible = "adi,hmc7044";
    		reg = <2>; // SPI CS 2
    		//spi-max-frequency = <10000000>;
    		spi-max-frequency = <100000>;
    		adi,sync-pin-mode = <1>;
    		adi,pll1-clkin-frequencies = <40000000 0 0 0>;
    		adi,pll1-ref-prio-ctrl = <0xE4>; /* prefer CLKIN0 */
    
    		adi,pll1-loop-bandwidth = <200>;
    
    		adi,vcxo-frequency = <122880000>;
    
    		adi,pll2-output-frequency = <2949120000>;
    
    		adi,sysref-timer-divider = <3840>;
    		adi,pulse-generator-mode = <0>;
    
    		adi,clkin0-buffer-mode = <0x0D>;
    		adi,clkin1-buffer-mode = <0x0D>;
    		adi,clkin2-buffer-mode = <0x0D>;
    		adi,clkin3-buffer-mode = <0x0D>;		
    		adi,oscin-buffer-mode = <0x07>;
    
    		adi,gpi-controls = <0x00 0x00 0x00 0x11>;
    		adi,gpo-controls = <0x1f 0x2b 0x00 0x00>;
    
    		clock-output-names = 
    			"hmc7044_out0_DEV_REFCLK_A", "hmc7044_out1_DEV_SYSREF_A",
    			"hmc7044_out2_DEV_REFCLK_B", "hmc7044_out3_DEV_SYSREF_B",
    			"hmc7044_out4_JESD_REFCLK_TX_OBS_AB", "hmc7044_out5_JESD_REFCLK_RX_AB",
    			"hmc7044_out6_CORE_CLK_TX_OBS_AB", "hmc7044_out7_CORE_CLK_RX_AB",
    			"hmc7044_out8_FPGA_SYSREF_TX_OBS_AB","hmc7044_out9_FPGA_SYSREF_RX_AB",
    			"hmc7044_out10", "hmc7044_out11",
    			"hmc7044_out12", "hmc7044_out13";				
    
    		hmc7044_c0: channel@0 {
    			reg = <0>;
    			adi,extended-name = "DEV_REFCLK_A";
    			adi,divider = <12>;	// 245760000
    			adi,driver-mode = <2>;	// LVDS
    			adi,coarse-digital-delay = <15>;
    		};
    		hmc7044_c1: channel@1 {
    			reg = <1>;
    			adi,extended-name = "DEV_SYSREF_A";
    			adi,divider = <3840>;	// 768000
    			adi,driver-mode = <1>;	// LVPECL  
    			adi,startup-mode-dynamic-enable;
    			adi,high-performance-mode-disable;
    			adi,driver-impedance-mode = <1>;
    			adi,force-mute-enable;
    			adi,control0-rb4-enable;
    		};
    		hmc7044_c2: channel@2 {
    			reg = <2>;
    			adi,extended-name = "DEV_REFCLK_B";
    			adi,divider = <12>;	// 245760000
    			adi,driver-mode = <2>;	// LVDS
    			adi,coarse-digital-delay = <15>;
    		};
    		hmc7044_c3: channel@3 {
    			reg = <3>;
    			adi,extended-name = "DEV_SYSREF_B";
    			adi,divider = <3840>;	// 768000
    			adi,driver-mode = <1>;	// LVPECL
    			adi,startup-mode-dynamic-enable;
    			adi,high-performance-mode-disable;
    			adi,driver-impedance-mode = <0>;
    			adi,force-mute-enable;
    			adi,control0-rb4-enable;
    		};
    		hmc7044_c4: channel@4 {
    			reg = <4>;
    			adi,extended-name = "JESD_REFCLK_TX_OBS_AB";
    			adi,divider = <12>;	// 245760000
    			adi,driver-mode = <2>;	// LVDS
    		};
    		hmc7044_c5: channel@5 {
    			reg = <5>;
    			adi,extended-name = "JESD_REFCLK_RX_AB";
    			adi,divider = <12>;	// 245760000
    			adi,driver-mode = <2>;	// LVDS
    		};
    //		hmc7044_c6: channel@6 {
    //			reg = <6>;
    //			adi,extended-name = "CORE_CLK_TX_OBS_AB";
    //			adi,divider = <24>;	// 122880000
    //			adi,driver-mode = <0>;	// 
    //		};
    //		hmc7044_c7: channel@7 {
    //			reg = <7>;
    //			adi,extended-name = "CORE_CLK_RX_AB";
    //			adi,divider = <12>;	// 245760000
    //			adi,driver-mode = <0>;	// LVDS
    //		};
    		hmc7044_c8: channel@8 {
    			reg = <8>;
    			adi,extended-name = "FPGA_SYSREF_TX_OBS_AB";
    			adi,divider = <3840>;	// 768000
    			adi,driver-mode = <1>;	// 
    			adi,startup-mode-dynamic-enable;
    			adi,high-performance-mode-disable;
    			adi,force-mute-enable;
    			adi,control0-rb4-enable;
    		};
    		hmc7044_c9: channel@9 {
    			reg = <9>;
    			adi,extended-name = "FPGA_SYSREF_RX_AB";
    			adi,divider = <3840>;	// 768000
    			adi,driver-mode = <1>;	// LVDS
    			adi,startup-mode-dynamic-enable;
    			adi,high-performance-mode-disable;
    			adi,force-mute-enable;
    			adi,control0-rb4-enable;
    		};
    
    	};
    
    };

    hmc7044_c4 is the one used, so as i have 2949120000 Hz as pll freq, divider should be 24 to have 122.88 MHz.

    Is this right ?

    Salah

  • How come is it working on older HDL ? 

    The old hdl  does not have the  internal buffer monitoring bits, The driver checks the ip version and ignores this check,   while the issue slips through.    By the way,  I noticed some errors in your original log,  mentioning link restarts ... the root cause could be the same.

    hmc7044_c4 is the one used, so as i have 2949120000 Hz as pll freq, divider should be 24 to have 122.88 MHz.

    Is this right ?

    Yes, it should be 24.

    Laszlo