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AD5764 NO Analog Output Voltage of DAC

Hello ALL,

I'm using AD5764,

followed https://wiki.analog.com/resources/tools-software/linux-drivers/iio-dac/ad5764 to enable the driver.

I'm able to see the dac device after changing the device tree. Here is the log attached.

root@fps_clc:/sys/bus/iio/devices# cd iio\:device0
root@fps_clc:/sys/bus/iio/devices/iio:device0# ls
dev out_voltage0_calibscale out_voltage1_calibscale out_voltage2_calibscale out_voltage3_calibscale power
name out_voltage0_raw out_voltage1_raw out_voltage2_raw out_voltage3_raw subsystem
of_node out_voltage0_scale out_voltage1_scale out_voltage2_scale out_voltage3_scale uevent
out_voltage0_calibbias out_voltage1_calibbias out_voltage2_calibbias out_voltage3_calibbias out_voltage_offset
root@fps_clc:/sys/bus/iio/devices/iio:device0# cat out_voly tage0_scale
0.305175781
root@fps_clc:/sys/bus/iio/devices/iio:device0# echo 10000 > out_voltage0_raw
root@fps_clc:/sys/bus/iio/devices/iio:device0# cat out_voltage0_scale
0.305175781

i'm probing pin VOUTA, no voltage is coming from the pin.

Please let me know what i'm missing.

Thanks,

Regards.

  • Hello,

    I have solved this by making LDAC from high to low after writing to scale. Got to know this after reading AD5764 datasheet.

    Here is the pera from datasheet

    Load DAC. Logic input. This is used to update the data register and consequently the analog outputs. When tied permanently low, the addressed data register is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the DAC input shift register is updated but the output update is held off until the falling edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC. The LDAC pin must not be left unconnected.

    Thanks,

    Balaji.G