Hello ADI Team
Thanks for the support provided for configuring ADRV9008-1 and ADRV9008-2 using Baremetal. The solutions offered in https://ez.analog.com/fpga/f/q-a/551024/adrv9009-zcu102-hdl-for-2-lanes were of great help.
Now I am trying to configure these Transceivers using Linux. The integrated version of project (.tcl file) in which ADRV9008-1 is connected to HPC0 and ADRV9008-2 connected to HPC1 is found in this post https://ez.analog.com/fpga/f/q-a/551024/adrv9009-zcu102-hdl-for-2-lanes. The same .hdf is used to create Linux Image. I followed the steps that were provided in https://wiki.analog.com/resources/eval/user-guides/adrv9002/quickstart/zynqmp and tried to add zynqmp-zcu102-rev10-adrv9008-1-jesd204-fsm.dts and zynqmp-zcu102-rev10-adrv9008-2-jesd204-fsm.dts in petalinuxbsp.conf before building the project. However, on booting, it was observed that only ADRV9008-1 was configured. The PL.dtsi generated after build is attached for reference. It does'nt reflect the zynqmp-zcu102-rev10-adrv9008-2-jesd204-fsm.dts. Am I following the right steps to build this project?
/*
* CAUTION: This file is automatically generated by Xilinx.
* Version:
* Today is: Thu Dec 9 08:38:38 2021
*/
/ {
amba_pl: amba_pl@0 {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges ;
axi_adrv9009_rx_clkgen: axi_clkgen@83c10000 {
clock-names = "clk", "s_axi_aclk";
clocks = <&misc_clk_0>, <&zynqmp_clk 71>;
compatible = "xlnx,axi-clkgen-1.0";
reg = <0x0 0x83c10000 0x0 0x10000>;
};
misc_clk_0: misc_clk_0 {
#clock-cells = <0>;
clock-frequency = <100000000>;
compatible = "fixed-clock";
};
axi_adrv9009_rx_dma: axi_dmac@9c400000 {
clock-names = "s_axi_aclk", "m_dest_axi_aclk", "fifo_wr_clk";
clocks = <&zynqmp_clk 71>, <&zynqmp_clk 72>, <&misc_clk_0>;
compatible = "xlnx,axi-dmac-1.0";
interrupt-names = "irq";
interrupt-parent = <&gic>;
interrupts = <0 109 4>;
reg = <0x0 0x9c400000 0x0 0x1000>;
};
axi_adrv9009_rx_jesd_rx_axi: axi_jesd204_rx@84aa0000 {
clock-names = "s_axi_aclk", "core_clk";
clocks = <&zynqmp_clk 71>, <&misc_clk_0>;
compatible = "xlnx,axi-jesd204-rx-1.0";
interrupt-names = "irq";
interrupt-parent = <&gic>;
interrupts = <0 106 4>;
reg = <0x0 0x84aa0000 0x0 0x4000>;
};
axi_adrv9009_rx_os_clkgen: axi_clkgen@83c20000 {
clock-names = "clk", "s_axi_aclk";
clocks = <&misc_clk_0>, <&zynqmp_clk 71>;
compatible = "xlnx,axi-clkgen-1.0";
reg = <0x0 0x83c20000 0x0 0x10000>;
};
axi_adrv9009_rx_os_dma: axi_dmac@9c440000 {
clock-names = "s_axi_aclk", "m_dest_axi_aclk", "fifo_wr_clk";
clocks = <&zynqmp_clk 71>, <&zynqmp_clk 72>, <&misc_clk_0>;
compatible = "xlnx,axi-dmac-1.0";
interrupt-names = "irq";
interrupt-parent = <&gic>;
interrupts = <0 107 4>;
reg = <0x0 0x9c440000 0x0 0x1000>;
};
axi_adrv9009_rx_os_jesd_rx_axi: axi_jesd204_rx@84ab0000 {
clock-names = "s_axi_aclk", "core_clk";
clocks = <&zynqmp_clk 71>, <&misc_clk_0>;
compatible = "xlnx,axi-jesd204-rx-1.0";
interrupt-names = "irq";
interrupt-parent = <&gic>;
interrupts = <0 104 4>;
reg = <0x0 0x84ab0000 0x0 0x4000>;
};
axi_adrv9009_rx_os_xcvr: axi_adxcvr@84a50000 {
clock-names = "s_axi_aclk";
clocks = <&zynqmp_clk 71>;
compatible = "xlnx,axi-adxcvr-1.0";
reg = <0x0 0x84a50000 0x0 0x10000>;
};
axi_adrv9009_rx_xcvr: axi_adxcvr@84a60000 {
clock-names = "s_axi_aclk";
clocks = <&zynqmp_clk 71>;
compatible = "xlnx,axi-adxcvr-1.0";
reg = <0x0 0x84a60000 0x0 0x10000>;
};
axi_adrv9009_tx_clkgen: axi_clkgen@83c00000 {
clock-names = "clk", "s_axi_aclk";
clocks = <&misc_clk_0>, <&zynqmp_clk 71>;
compatible = "xlnx,axi-clkgen-1.0";
reg = <0x0 0x83c00000 0x0 0x10000>;
};
axi_adrv9009_tx_dma: axi_dmac@9c420000 {
clock-names = "s_axi_aclk", "m_src_axi_aclk", "m_axis_aclk";
clocks = <&zynqmp_clk 71>, <&zynqmp_clk 72>, <&zynqmp_clk 72>;
compatible = "xlnx,axi-dmac-1.0";
interrupt-names = "irq";
interrupt-parent = <&gic>;
interrupts = <0 108 4>;
reg = <0x0 0x9c420000 0x0 0x1000>;
};
axi_adrv9009_tx_jesd_tx_axi: axi_jesd204_tx@84a90000 {
clock-names = "s_axi_aclk", "core_clk";
clocks = <&zynqmp_clk 71>, <&misc_clk_0>;
compatible = "xlnx,axi-jesd204-tx-1.0";
interrupt-names = "irq";
interrupt-parent = <&gic>;
interrupts = <0 105 4>;
reg = <0x0 0x84a90000 0x0 0x4000>;
};
axi_adrv9009_tx_xcvr: axi_adxcvr@84a80000 {
clock-names = "s_axi_aclk";
clocks = <&zynqmp_clk 71>;
compatible = "xlnx,axi-adxcvr-1.0";
reg = <0x0 0x84a80000 0x0 0x10000>;
};
axi_sysid_0: axi_sysid@85000000 {
clock-names = "s_axi_aclk";
clocks = <&zynqmp_clk 71>;
compatible = "xlnx,axi-sysid-1.0";
reg = <0x0 0x85000000 0x0 0x10000>;
};
psu_ctrl_ipi: PERIPHERAL@ff380000 {
compatible = "xlnx,PERIPHERAL-1.0";
reg = <0x0 0xff380000 0x0 0x80000>;
};
psu_message_buffers: PERIPHERAL@ff990000 {
compatible = "xlnx,PERIPHERAL-1.0";
reg = <0x0 0xff990000 0x0 0x10000>;
};
rx_adrv9009_tpl_core_adc_tpl_core: ad_ip_jesd204_tpl_adc@84a00000 {
clock-names = "link_clk", "s_axi_aclk";
clocks = <&misc_clk_0>, <&zynqmp_clk 71>;
compatible = "xlnx,ad-ip-jesd204-tpl-adc-1.0";
reg = <0x0 0x84a00000 0x0 0x2000>;
};
rx_os_adrv9009_tpl_core_adc_tpl_core: ad_ip_jesd204_tpl_adc@84a08000 {
clock-names = "link_clk", "s_axi_aclk";
clocks = <&misc_clk_0>, <&zynqmp_clk 71>;
compatible = "xlnx,ad-ip-jesd204-tpl-adc-1.0";
reg = <0x0 0x84a08000 0x0 0x2000>;
};
tx_adrv9009_tpl_core_dac_tpl_core: ad_ip_jesd204_tpl_dac@84a04000 {
clock-names = "link_clk", "s_axi_aclk";
clocks = <&misc_clk_0>, <&zynqmp_clk 71>;
compatible = "xlnx,ad-ip-jesd204-tpl-dac-1.0";
reg = <0x0 0x84a04000 0x0 0x2000>;
};
};
};
/include/ "pl-delete-nodes-zynqmp-zcu102-rev10-adrv9008-1-jesd204-fsm.dtsi"
Requesting to provide solution for adding ADC and DAC in the same image and configuring it using Linux.
Thanks
Deepika
