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Follow up adrv9009 QPLL not locking with hmc7044

Hello,

Previous discussion was locked for some reason : Custom board adrv9009 QPLL not locking with hmc7044 - Q&A - Linux Software Drivers - EngineerZone (analog.com)

Thanks for the reply

  • Indeed, forgot to remove clock assignement from JESD FSM device tree. They are well defined in another device tree file
  • added jesd204-ignore-errors;
  • removed axi clkgen nodes
  • spi-max-frequency = <100000>; instead of  //spi-max-frequency = <10000000>; inside hmc node

Boot log


U-Boot 2021.01 (Jun 01 2021 - 11:54:06 +0000)

CPU:   Zynq 7z045
Silicon: v3.1
Model: Xilinx ZC706 board
DRAM:  ECC disabled 1 GiB
Flash: 0 Bytes
NAND:  0 MiB
MMC:   mmc@e0100000: 0
Loading Environment from FAT... *** Warning - bad CRC, using default environment

In:    serial@e0001000
Out:   serial@e0001000
Err:   serial@e0001000
Net:
ZYNQ GEM: e000b000, mdio bus e000b000, phyaddr 0, interface rgmii-id

Warning: ethernet@e000b000 (eth0) using random MAC address - 36:07:34:74:f2:9d
eth0: ethernet@e000b000
Hit any key to stop autoboot:  0
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
Found U-Boot script /boot.scr
2595 bytes read in 28 ms (89.8 KiB/s)
## Executing script at 03000000
Trying to load boot images from mmc0
43292884 bytes read in 7071 ms (5.8 MiB/s)
## Loading kernel from FIT Image at 10000000 ...
   Using 'conf-system-top.dtb' configuration
   Verifying Hash Integrity ... OK
   Trying 'kernel-1' kernel subimage
     Description:  Linux kernel
     Type:         Kernel Image
     Compression:  uncompressed
     Data Start:   0x10000100
     Data Size:    25175072 Bytes = 24 MiB
     Architecture: ARM
     OS:           Linux
     Load Address: 0x00200000
     Entry Point:  0x00200000
     Hash algo:    sha256
     Hash value:   53ffb458f6a7d03799f1a1d7a7c78914beef3c9ae808e065981703b049112304
   Verifying Hash Integrity ... sha256+ OK
## Loading ramdisk from FIT Image at 10000000 ...
   Using 'conf-system-top.dtb' configuration
   Verifying Hash Integrity ... OK
   Trying 'ramdisk-1' ramdisk subimage
     Description:  petalinux-image-minimal
     Type:         RAMDisk Image
     Compression:  uncompressed
     Data Start:   0x1180e500
     Data Size:    18067040 Bytes = 17.2 MiB
     Architecture: ARM
     OS:           Linux
     Load Address: unavailable
     Entry Point:  unavailable
     Hash algo:    sha256
     Hash value:   63acd6d7636a2f96572a0cbe74ca4eebc76015c8aa3158fdff260d6071271e5b
   Verifying Hash Integrity ... sha256+ OK
## Loading fdt from FIT Image at 10000000 ...
   Using 'conf-system-top.dtb' configuration
   Verifying Hash Integrity ... OK
   Trying 'fdt-system-top.dtb' fdt subimage
     Description:  Flattened Device Tree blob
     Type:         Flat Device Tree
     Compression:  uncompressed
     Data Start:   0x1180262c
     Data Size:    48648 Bytes = 47.5 KiB
     Architecture: ARM
     Hash algo:    sha256
     Hash value:   fc4bf5530c9fc71e931fb17736e586267ccba779fd78705785957cbc5a5309d9
   Verifying Hash Integrity ... sha256+ OK
   Booting using the fdt blob at 0x1180262c
   Loading Kernel Image
   Loading Ramdisk to 2eec5000, end 2ffffe60 ... OK
   Loading Device Tree to 2eeb6000, end 2eec4e07 ... OK

Starting kernel ...

Booting Linux on physical CPU 0x0
Linux version 5.10.0-xilinx-v2021.1 (oe-user@oe-host) (arm-xilinx-linux-gnueabi-gcc (GCC) 10.2.0, GNU ld (GNU Binutils) 2.35.1) #1 SMP PREEMPT Thu Nov 18 14:55:54 UTC 2021
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
OF: fdt: Machine model: Xilinx ZC706 board
printk: bootconsole [earlycon0] enabled
Memory policy: Data cache writealloc
INITRD: 0x00800000+0x01000000 overlaps in-use memory region - disabling initrd
cma: Reserved 128 MiB at 0x38000000
Zone ranges:
  Normal   [mem 0x0000000000000000-0x000000002fffffff]
  HighMem  [mem 0x0000000030000000-0x000000003fffffff]
Movable zone start for each node
Early memory node ranges
  node   0: [mem 0x0000000000000000-0x000000003fffffff]
Initmem setup node 0 [mem 0x0000000000000000-0x000000003fffffff]
percpu: Embedded 15 pages/cpu s30028 r8192 d23220 u61440
Built 1 zonelists, mobility grouping on.  Total pages: 260416
Kernel command line: console=ttyPS0,115200n8 root=/dev/ram rw initrd=0x00800000,16M earlyprintk mtdparts=physmap-flash.0:512K(nor-fsbl),512K(nor-u-boot),5M(nor-linux),9M(nor-user),1M(nor-scratch),-(nor-rootfs)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes, linear)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
mem auto-init: stack:off, heap alloc:off, heap free:off
Memory: 825596K/1048576K available (10240K kernel code, 852K rwdata, 7196K rodata, 44032K init, 168K bss, 91908K reserved, 131072K cma-reserved, 131072K highmem)
rcu: Preemptible hierarchical RCU implementation.
rcu:    RCU event tracing is enabled.
rcu:    RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
        Trampoline variant of Tasks RCU enabled.
rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
efuse mapped to (ptrval)
slcr mapped to (ptrval)
L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 ID prefetch enabled, offset 1 lines
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 512 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
random: get_random_bytes called from start_kernel+0x33c/0x4e8 with crng_init=0
zynq_clock_init: clkc starts at (ptrval)
Zynq clock init
ps_clk frequency not specified, using 33 MHz.
sched_clock: 64 bits at 399MHz, resolution 2ns, wraps every 4398046511103ns
clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x5c4093a7d1, max_idle_ns: 440795210635 ns
Switching to timer-based delay loop, resolution 2ns
clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 447945978 ns
timer #0 at (ptrval), irq=25
Console: colour dummy device 80x30
Calibrating delay loop (skipped), value calculated using timer frequency.. 799.99 BogoMIPS (lpj=3999999)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 2048 (order: 1, 8192 bytes, linear)
Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes, linear)
CPU: Testing write buffer coherency: ok
CPU0: Spectre v2: using BPIALL workaround
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x100000 - 0x100060
rcu: Hierarchical SRCU implementation.
smp: Bringing up secondary CPUs ...
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
CPU1: Spectre v2: using BPIALL workaround
smp: Brought up 1 node, 2 CPUs
SMP: Total of 2 processors activated (1599.99 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
futex hash table entries: 512 (order: 3, 32768 bytes, linear)
pinctrl core: initialized pinctrl subsystem
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
thermal_sys: Registered thermal governor 'step_wise'
cpuidle: using governor ladder
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0x(ptrval)
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
mc: Linux media interface: v0.10
videodev: Linux video capture interface: v2.00
jesd204: created con: id=0, topo=0, link=0, /axi/spi@e0006000/hmc7044@2 <-> /fpga-axi@0/axi-adxcvr-tx@44a80000
jesd204: created con: id=1, topo=0, link=1, /axi/spi@e0006000/hmc7044@2 <-> /fpga-axi@0/axi-adxcvr-rx@44a60000
jesd204: created con: id=2, topo=0, link=0, /fpga-axi@0/axi-adxcvr-tx@44a80000 <-> /fpga-axi@0/axi-jesd204-tx@44a90000
jesd204: created con: id=3, topo=0, link=1, /fpga-axi@0/axi-adxcvr-rx@44a60000 <-> /fpga-axi@0/axi-jesd204-rx@44aa0000
jesd204: created con: id=4, topo=0, link=1, /fpga-axi@0/axi-jesd204-rx@44aa0000 <-> /axi/spi@e0006000/adrv9009-phy@0
jesd204: created con: id=5, topo=0, link=0, /fpga-axi@0/axi-jesd204-tx@44a90000 <-> /axi/spi@e0006000/adrv9009-phy@0
jesd204: /axi/spi@e0006000/adrv9009-phy@0: JESD204[0] transition uninitialized -> initialized
jesd204: /axi/spi@e0006000/adrv9009-phy@0: JESD204[1] transition uninitialized -> initialized
jesd204: found 6 devices and 1 topologies
FPGA manager framework
Advanced Linux Sound Architecture Driver Initialized.
clocksource: Switched to clocksource arm_global_timer
NET: Registered protocol family 2
tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes, linear)
TCP established hash table entries: 8192 (order: 3, 32768 bytes, linear)
TCP bind hash table entries: 8192 (order: 4, 65536 bytes, linear)
TCP: Hash tables configured (established 8192 bind 8192)
UDP hash table entries: 512 (order: 2, 16384 bytes, linear)
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear)
NET: Registered protocol family 1
hw perfevents: no interrupt-affinity property for /pmu@f8891000, guessing.
hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
workingset: timestamp_bits=14 max_order=18 bucket_order=4
bounce: pool size: 64 pages
io scheduler mq-deadline registered
io scheduler kyber registered
zynq-pinctrl 700.pinctrl: zynq pinctrl initialized
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-241330
dma-pl330 f8003000.dmac:        DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
brd: module loaded
loop: module loaded
Registered mathworks_ip class
spi-nor spi0.0: unrecognized JEDEC id bytes: 00 00 00 00 00 00
MACsec IEEE 802.1AE
libphy: Fixed MDIO Bus: probed
tun: Universal TUN/TAP device driver, 1.6
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
libphy: MACB_mii_bus: probed
macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 38 (36:07:34:74:f2:9d)
usbcore: registered new interface driver asix
usbcore: registered new interface driver ax88179_178a
usbcore: registered new interface driver cdc_ether
usbcore: registered new interface driver net1080
usbcore: registered new interface driver cdc_subset
usbcore: registered new interface driver zaurus
usbcore: registered new interface driver cdc_ncm
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
usbcore: registered new interface driver uas
usbcore: registered new interface driver usb-storage
usbcore: registered new interface driver usbserial_generic
usbserial: USB Serial support registered for generic
usbcore: registered new interface driver ftdi_sio
usbserial: USB Serial support registered for FTDI USB Serial Device
usbcore: registered new interface driver upd78f0730
usbserial: USB Serial support registered for upd78f0730
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
udc-core: couldn't find an available UDC - added [g_mass_storage] to list of pending drivers
i2c /dev entries driver
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
cdns-i2c e0004000.i2c: 400 kHz mmio e0004000 irq 32
pca954x 0-0074: probe failed
usbcore: registered new interface driver uvcvideo
USB Video Class driver (1.1.1)
gspca_main: v2.14.0 registered
cdns-wdt f8005000.watchdog: Xilinx Watchdog Timer with timeout 10s
Xilinx Zynq CpuIdle Driver started
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
sdhci-pltfm: SDHCI platform and OF driver helper
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
ledtrig-cpu: registered to indicate activity on CPUs
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
hid: raw HID events driver (C) Jiri Kosina
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
usbcore: registered new interface driver usbhid
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
usbhid: USB HID core driver
adrv9009 spi1.0: adrv9009_probe : enter
mmc0: SDHCI controller on e0100000.mmc [e0100000.mmc] using ADMA
hmc7044 spi1.2: PLL1: Holdover, CLKIN1 @ 40000000 Hz, PFD: 320 kHz - PLL2: Locked @ 2949.120000 MHz
jesd204: /axi/spi@e0006000/hmc7044@2,jesd204:0,parent=spi1.2: Using as SYSREF provider
axi_adxcvr 44a60000.axi-adxcvr-rx: AXI-ADXCVR-RX (16.01.a) using CPLL on GTX2 at 0x44A60000. Number of lanes: 2.
axi_adxcvr 44a80000.axi-adxcvr-tx: AXI-ADXCVR-TX (16.01.a) using QPLL on GTX2 at 0x44A80000. Number of lanes: 2.
axi-jesd204-rx 44aa0000.axi-jesd204-rx: AXI-JESD204-RX (1.02.a) at 0x44AA0000. Encoder 8b10b, width 4/0, lanes 2, jesd204-fsm.
axi-jesd204-tx 44a90000.axi-jesd204-tx: AXI-JESD204-TX (1.01.a) at 0x44A90000. Encoder 8b10b, width 4/0, lanes 2, jesd204-fsm.
fpga_manager fpga0: Xilinx Zynq FPGA Manager registered
usbcore: registered new interface driver snd-usb-audio
NET: Registered protocol family 10
Segment Routing with IPv6
sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
NET: Registered protocol family 17
NET: Registered protocol family 36
Registering SWP/SWPB emulation handler
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 35, base_baud = 3125000) is a xuartps
printk: console [ttyPS0] enabled
printk: console [ttyPS0] enabled
printk: bootconsole [earlycon0] disabled
printk: bootconsole [earlycon0] disabled
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
adrv9009 spi1.0: adrv9009_probe : enter
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[0] transition initialized -> probed
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[1] transition initialized -> probed
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[0] transition probed -> idle
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[1] transition probed -> idle
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[0] transition idle -> device_init
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[1] transition idle -> device_init
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[0] transition device_init -> link_init
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[1] transition device_init -> link_init
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[0] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[1] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[0] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[1] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[0] transition link_pre_setup -> clk_sync_stage1
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[1] transition link_pre_setup -> clk_sync_stage1
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[0] transition clk_sync_stage1 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[1] transition clk_sync_stage1 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[0] transition clk_sync_stage2 -> clk_sync_stage3
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[1] transition clk_sync_stage2 -> clk_sync_stage3
jesd204: /fpga-axi@0/axi-jesd204-rx@44aa0000,jesd204:2,parent=44aa0000.axi-jesd204-rx: Possible instantiation for multiple chips; HDL lanes 2, Link[1] lanes 1
jesd204: /fpga-axi@0/axi-jesd204-tx@44a90000,jesd204:3,parent=44a90000.axi-jesd204-tx: Possible instantiation for multiple chips; HDL lanes 2, Link[0] lanes 1
axi_adxcvr 44a80000.axi-adxcvr-tx: QPLL TX Error: 0
axi_adxcvr 44a80000.axi-adxcvr-tx: QPLL TX Error: 0
axi-jesd204-tx 44a90000.axi-jesd204-tx: axi_jesd204_tx_jesd204_link_setup: Link0 enable lane clock failed (-5)
jesd204: /fpga-axi@0/axi-jesd204-tx@44a90000,jesd204:3,parent=44a90000.axi-jesd204-tx: JESD204[0] In link_setup got error from cb: -5 (ignoring!)
adrv9009 spi1.0: ADIHAL_resetHw
adrv9009 spi1.0: ERROR: 346: TALISE_verifySpiReadWrite(): Cannot read from a low SPI address
adrv9009 spi1.0: adrv9009_jesd204_link_setup:5805 (ret 10)
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[0] In link_setup got error from cb: -14 (ignoring!)
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[0] transition clk_sync_stage3 -> link_setup
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[1] transition clk_sync_stage3 -> link_setup
adrv9009 spi1.0: adrv9009_jesd204_setup_stage1:5861 Unexpected MCS sync status (0x0)
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[0] In opt_setup_stage1 got error from cb: -14 (ignoring!)
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[0] transition link_setup -> opt_setup_stage1
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[1] transition link_setup -> opt_setup_stage1
adrv9009 spi1.0: adrv9009_jesd204_setup_stage2:5891 Unexpected MCS sync status (0x0)
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[0] In opt_setup_stage2 got error from cb: -14 (ignoring!)
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[0] transition opt_setup_stage1 -> opt_setup_stage2
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[1] transition opt_setup_stage1 -> opt_setup_stage2
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[0] transition opt_setup_stage2 -> opt_setup_stage3
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[1] transition opt_setup_stage2 -> opt_setup_stage3
random: fast init done
adrv9009 spi1.0: ERROR: 179: ARM Mailbox Busy. Command not executed in TALISE_sendArmCommand()
adrv9009 spi1.0: adrv9009_jesd204_setup_stage4:6040 (ret 5)
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[0] In opt_setup_stage4 got error from cb: -14 (ignoring!)
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[0] transition opt_setup_stage3 -> opt_setup_stage4
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[1] transition opt_setup_stage3 -> opt_setup_stage4
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[0] transition opt_setup_stage4 -> opt_setup_stage5
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[1] transition opt_setup_stage4 -> opt_setup_stage5
axi_adxcvr 44a60000.axi-adxcvr-rx: CPLL RX Error: 0
axi_adxcvr 44a60000.axi-adxcvr-rx: CPLL RX Error: 0
axi-jesd204-rx 44aa0000.axi-jesd204-rx: axi_jesd204_rx_jesd204_clks_enable: Link1 enable lane clock failed (-5)
jesd204: /fpga-axi@0/axi-jesd204-rx@44aa0000,jesd204:2,parent=44aa0000.axi-jesd204-rx: JESD204[1] In clocks_enable got error from cb: -5 (ignoring!)
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[0] transition opt_setup_stage5 -> clocks_enable
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[1] transition opt_setup_stage5 -> clocks_enable
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[0] transition clocks_enable -> link_enable
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[1] transition clocks_enable -> link_enable
axi-jesd204-rx 44aa0000.axi-jesd204-rx: axi_jesd204_rx_jesd204_link_running: Link1 status failed (RESET)
jesd204: /fpga-axi@0/axi-jesd204-rx@44aa0000,jesd204:2,parent=44aa0000.axi-jesd204-rx: JESD204[1] In link_running got error from cb: -1 (ignoring!)
axi-jesd204-tx 44a90000.axi-jesd204-tx: axi_jesd204_tx_jesd204_link_running: Link0 status failed (WAIT)
jesd204: /fpga-axi@0/axi-jesd204-tx@44a90000,jesd204:3,parent=44a90000.axi-jesd204-tx: JESD204[0] In link_running got error from cb: -1 (ignoring!)
adrv9009 spi1.0: Link0 TAL_DEFRAMER_A deframerStatus 0x8
adrv9009 spi1.0: Link1 TAL_FRAMER_A framerStatus 0x0
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[0] transition link_enable -> link_running
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[1] transition link_enable -> link_running
adrv9009 spi1.0: ERROR: 180: Device not in radioOff/IDLE state. Error in TALISE_enableTrackingCals()
adrv9009 spi1.0: adrv9009_jesd204_post_running_stage:6141 (ret 5)
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[0] In opt_post_running_stage got error from cb: -14 (ignoring!)
adrv9009 spi1.0: ERROR: 32: TALISE_gpIntHandler(): AUXCLK PLL is not locked
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[0] transition link_running -> opt_post_running_stage
adrv9009 spi1.0: AUX PLL lock detect reset
adrv9009 spi1.0: (null)
jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[1] transition link_running -> opt_post_running_stage
adrv9009 spi1.0: (null)
adrv9009 spi1.0: (null)
adrv9009 spi1.0: (null)
adrv9009 spi1.0: GP Interrupt Status 0x5 Action: ERR_RESET_FULL
cf_axi_dds 44a14000.axi-adrv9009-tx-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.00.b) at 0x44A14000 mapped to 0x(ptrval), probed DDS AD9371
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
cf_axi_adc 44a00000.axi-adrv9009-rx-hpc: ADI AIM (10.00.b) at 0x44A00000 mapped to 0x(ptrval), probed ADC ADRV9009 as MASTER
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
ALSA device list:
  No soundcards found.
Warning: unable to open an initial console.
Freeing unused kernel memory: 44032K
Run /init as init process
udevd[77]: starting version 3.2.9
random: udevd: uninitialized urandom read (16 bytes read)
random: udevd: uninitialized urandom read (16 bytes read)
random: udevd: uninitialized urandom read (16 bytes read)
udevd[78]: starting eudev-3.2.9
urandom_read: 2 callbacks suppressed
random: dd: uninitialized urandom read (512 bytes read)
samplemodule: loading out-of-tree module taints kernel.
<1>Hello module world : DRIVER !!
<1>Module parameters were (0xdeadbeef) and "default"
<1>Config_of ok.
Sorry, registering the character device  failed with
macb e000b000.ethernet eth0: PHY [e000b000.ethernet-ffffffff:00] driver [Marvell 88E1510] (irq=POLL)
macb e000b000.ethernet eth0: configuring for phy/rgmii-id link mode
macb e000b000.ethernet eth0: Link is Up - 1Gbps/Full - flow control tx
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
random: dbus-uuidgen: uninitialized urandom read (12 bytes read)
random: dbus-uuidgen: uninitialized urandom read (8 bytes read)
random: dbus-daemon: uninitialized urandom read (12 bytes read)
random: crng init done
random: 1 urandom warning(s) missed due to ratelimiting

root@ETRX_petalinux:~#

root@ETRX_petalinux:~# cat /sys/kernel/debug/clk/clk_summary
                                 enable  prepare  protect                                duty
   clock                          count    count    count        rate   accuracy phase  cycle  nshot
----------------------------------------------------------------------------------------------------
 spi1.0-tx_sampl_clk                  1        1        0    61440000          0     0  50000        0
 spi1.0-obs_sampl_clk                 0        0        0   122880000          0     0  50000        0
 spi1.0-rx_sampl_clk                  0        0        0    61440000          0     0  50000        0
 hmc7044_out9_FPGA_SYSREF_RX_AB       0        0        0     1920000          0     0  50000        0
 hmc7044_out8_FPGA_SYSREF_TX_OBS_AB       0        0        0     1920000          0     0  50000        0
 hmc7044_out7_CORE_CLK_RX_AB          2        2        0   122880000          0     0  50000        0
 hmc7044_out6_CORE_CLK_TX_OBS_AB       1        1        0   122880000          0     0  50000        0
 hmc7044_out5_JESD_REFCLK_RX_AB       1        1        0   245760000          0     0  50000        0
    rx_out_clk                        0        0        0   245760000          0     0  50000        0
    rx_gt_clk                         0        0        0     4915200          0     0  50000        0
 hmc7044_out4_JESD_REFCLK_TX_OBS_AB       1        1        0   245760000          0     0  50000        0
    tx_out_clk                        0        0        0   245760000          0     0  50000        0
    tx_gt_clk                         0        0        0     4915200          0     0  50000        0
 hmc7044_out3_DEV_SYSREF_B            0        0        0     1920000          0     0  50000        0
 hmc7044_out2_DEV_REFCLK_B            0        0        0   245760000          0     0  50000        0
 hmc7044_out1_DEV_SYSREF_A            0        0        0     1920000          0     0  50000        0
 hmc7044_out0_DEV_REFCLK_A            1        1        0   245760000          0     0  50000        0
 adrv9009_ext_refclk                  0        0        0    12288000          0     0  50000        0
 audio_clock                          0        0        0    12288000          0     0  50000        0
 ps_clk                               3        3        0    33333333          0     0  50000        0
    iopll_int                         1        1        0   999999990          0     0  50000        0
       iopll                          9        9        0   999999990          0     0  50000        0
          dbg_mux                     1        1        0   999999990          0     0  50000        0
             dbg_div                  1        1        0    66666666          0     0  50000        0
                dbg_emio_mux          1        1        0    66666666          0     0  50000        0
                   dbg_trc            1        1        0    66666666          0     0  50000        0
          can_mux                     0        0        0   999999990          0     0  50000        0
             can_div0                 0        0        0    40000000          0     0  50000        0
                can_div1              0        0        0     8000000          0     0  50000        0
                   can1_gate          0        0        0     8000000          0     0  50000        0
                      can1            0        0        0     8000000          0     0  50000        0
                   can0_gate          0        0        0     8000000          0     0  50000        0
                      can0            0        0        0     8000000          0     0  50000        0
          gem1_mux                    0        0        0   999999990          0     0  50000        0
             gem1_div0                0        0        0    16666667          0     0  50000        0
                gem1_div1             0        0        0    16666667          0     0  50000        0
                   gem1_emio_mux       0        0        0    16666667          0     0  50000        0
                      gem1            0        0        0    16666667          0     0  50000        0
          gem0_mux                    1        1        0   999999990          0     0  50000        0
             gem0_div0                1        1        0   124999999          0     0  50000        0
                gem0_div1             1        1        0   124999999          0     0  50000        0
                   gem0_emio_mux       1        1        0   124999999          0     0  50000        0
                      gem0            1        1        0   124999999          0     0  50000        0
          spi0_mux                    0        0        0   999999990          0     0  50000        0
             spi0_div                 0        0        0   166666665          0     0  50000        0
                spi1                  0        0        0   166666665          0     0  50000        0
                spi0                  0        0        0   166666665          0     0  50000        0
          uart0_mux                   1        1        0   999999990          0     0  50000        0
             uart0_div                1        1        0    50000000          0     0  50000        0
                uart1                 1        1        0    50000000          0     0  50000        0
                uart0                 0        0        0    50000000          0     0  50000        0
          sdio0_mux                   1        1        0   999999990          0     0  50000        0
             sdio0_div                1        1        0    50000000          0     0  50000        0
                sdio1                 0        0        0    50000000          0     0  50000        0
                sdio0                 1        1        0    50000000          0     0  50000        0
          pcap_mux                    1        1        0   999999990          0     0  50000        0
             pcap_div                 1        1        0   199999998          0     0  50000        0
                pcap                  1        2        0   199999998          0     0  50000        0
          fclk3_mux                   1        1        0   999999990          0     0  50000        0
             fclk3_div0               1        1        0    41666667          0     0  50000        0
                fclk3_div1            1        1        0    41666667          0     0  50000        0
                   fclk3              1        1        0    41666667          0     0  50000        0
          fclk2_mux                   1        1        0   999999990          0     0  50000        0
             fclk2_div0               1        1        0   499999995          0     0  50000        0
                fclk2_div1            1        1        0   249999998          0     0  50000        0
                   fclk2              1        1        0   249999998          0     0  50000        0
          fclk1_mux                   1        1        0   999999990          0     0  50000        0
             fclk1_div0               1        1        0   199999998          0     0  50000        0
                fclk1_div1            1        1        0   199999998          0     0  50000        0
                   fclk1              4        4        0   199999998          0     0  50000        0
          fclk0_mux                   1        1        0   999999990          0     0  50000        0
             fclk0_div0               1        1        0   199999998          0     0  50000        0
                fclk0_div1            1        1        0    99999999          0     0  50000        0
                   fclk0              2        2        0    99999999          0     0  50000        0
    ddrpll_int                        1        1        0  1066666656          0     0  50000        0
       ddrpll                         3        3        0  1066666656          0     0  50000        0
          dci_div0                    1        1        0    71111111          0     0  50000        0
             dci_div1                 1        1        0    10158731          0     0  50000        0
                dci                   1        1        0    10158731          0     0  50000        0
          ddr3x_div                   1        1        0   533333328          0     0  50000        0
             ddr3x                    1        1        0   533333328          0     0  50000        0
          ddr2x_div                   1        1        0   355555552          0     0  50000        0
             ddr2x                    1        1        0   355555552          0     0  50000        0
    armpll_int                        1        1        0  1599999984          0     0  50000        0
       armpll                         2        2        0  1599999984          0     0  50000        0
          smc_mux                     0        0        0  1599999984          0     0  50000        0
             smc_div                  0        0        0    26666667          0     0  50000        0
                smc                   0        0        0    26666667          0     0  50000        0
          lqspi_mux                   1        1        0  1599999984          0     0  50000        0
             lqspi_div                1        1        0    40000000          0     0  50000        0
                lqspi                 2        1        0    40000000          0     0  50000        0
          cpu_mux                     1        1        0  1599999984          0     0  50000        0
             cpu_div                  3        3        0   799999992          0     0  50000        0
                cpu_1x_div            1        1        0   133333332          0     0  50000        0
                   cpu_1x             9       10        0   133333332          0     0  50000        0
                      smc_aper        0        0        0   133333332          0     0  50000        0
                      lqspi_aper       2        1        0   133333332          0     0  50000        0
                      gpio_aper       1        1        0   133333332          0     0  50000        0
                      uart1_aper       1        1        0   133333332          0     0  50000        0
                      uart0_aper       0        0        0   133333332          0     0  50000        0
                      i2c1_aper       0        0        0   133333332          0     0  50000        0
                      i2c0_aper       0        1        0   133333332          0     0  50000        0
                      can1_aper       0        0        0   133333332          0     0  50000        0
                      can0_aper       0        0        0   133333332          0     0  50000        0
                      spi1_aper       0        0        0   133333332          0     0  50000        0
                      spi0_aper       0        0        0   133333332          0     0  50000        0
                      sdio1_aper       0        0        0   133333332          0     0  50000        0
                      sdio0_aper       1        1        0   133333332          0     0  50000        0
                      gem1_aper       0        0        0   133333332          0     0  50000        0
                      gem0_aper       2        2        0   133333332          0     0  50000        0
                      usb1_aper       0        0        0   133333332          0     0  50000        0
                      usb0_aper       0        0        0   133333332          0     0  50000        0
                      dbg_apb         1        1        0   133333332          0     0  50000        0
                      swdt            1        1        0   133333332          0     0  50000        0
                cpu_2x_div            1        1        0   266666664          0     0  50000        0
                   cpu_2x             1        2        0   266666664          0     0  50000        0
                      dma             0        1        0   266666664          0     0  50000        0
                cpu_3or2x_div         1        1        0   399999996          0     0  50000        0
                   cpu_3or2x          2        2        0   399999996          0     0  50000        0
                cpu_6or4x             0        0        0   799999992          0     0  50000        0
 can1_mio_mux                         0        0        0           0          0     0  50000        0
 can0_mio_mux                         0        0        0           0          0     0  50000        0

Regards,

Salah



Regards
[edited by: fadsalah_etelm at 4:21 PM (GMT -5) on 8 Dec 2021]
Parents
  • There seems to be lot's of different issues -


    axi_adxcvr 44a80000.axi-adxcvr-tx: QPLL TX Error: 0
    axi_adxcvr 44a80000.axi-adxcvr-tx: QPLL TX Error: 0
    axi-jesd204-tx 44a90000.axi-jesd204-tx: axi_jesd204_tx_jesd204_link_setup: Link0 enable lane clock failed (-5)

    QPLL doesn't lock - we've seen that before, can you check REFCLK and Link/Device clocks?

    adrv9009 spi1.0: ADIHAL_resetHw

    adrv9009 spi1.0: ERROR: 346: TALISE_verifySpiReadWrite(): Cannot read from a low SPI address

    SPI communication issue, Can you check RESET GPIO, DEV_CLK and if both are present your SPI signals?

    adrv9009 spi1.0: adrv9009_jesd204_link_setup:5805 (ret 10)
    adrv9009 spi1.0: adrv9009_jesd204_setup_stage1:5861 Unexpected MCS sync status (0x0)

    This could be caused by previous, SPI issues  or by the fact that the ADRV9009 doesn't receive a SYSREF when expecting one.

    Please check SYSREF pulses being issued.

     

    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:1,parent=spi1.0: JESD204[0] In opt_setup_stage1 got error from cb: -14 (ignoring!)
    adrv9009 spi1.0: ERROR: 179: ARM Mailbox Busy. Command not executed in TALISE_sendArmCommand()
    adrv9009 spi1.0: adrv9009_jesd204_setup_stage4:6040 (ret 5)

    SPI communication issue, likely due to pervious errors.

    axi_adxcvr 44a60000.axi-adxcvr-rx: CPLL RX Error: 0

    axi_adxcvr 44a60000.axi-adxcvr-rx: CPLL RX Error: 0

    CPLL doesn't lock - can you check CPLL REFCLK and Link/Device clocks?


    cf_axi_dds 44a14000.axi-adrv9009-tx-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.00.b) at 0x44A14000 mapped to 0x(ptrval), probed DDS AD9371

    AD9371? Can you remove the spibus-connected attributes and add a DMA?

    jesd_status should show and messure the clocks but in your case they are missing completely.

    Can you cleanup your devicetree and post it again?

    -Michael

  • Update,

    After fixing clkgen in device tree, clock error disapeared. JESD link is now enabled but stuck in CGS.

    Still having SPI errors :

    adrv9009 spi1.0: ADIHAL_resetHw
    adrv9009 spi1.0: ERROR: 346: TALISE_verifySpiReadWrite(): Cannot read from a low SPI address
    adrv9009 spi1.0: adrv9009_jesd204_link_setup:5805 (ret 10)

    Full boot log and device tree 

    
    Starting kernel ...
    
    Booting Linux on physical CPU 0x0
    Linux version 5.10.0-xilinx-v2021.1 (oe-user@oe-host) (arm-xilinx-linux-gnueabi-gcc (GCC) 10.2.0, GNU ld (GNU Binutils) 2.35.1) #1 SMP PREEMPT Thu Nov 18 14:55:54 UTC 2021
    CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
    CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
    OF: fdt: Machine model: Xilinx ZC706 board
    printk: bootconsole [earlycon0] enabled
    Memory policy: Data cache writealloc
    INITRD: 0x00800000+0x01000000 overlaps in-use memory region - disabling initrd
    cma: Reserved 128 MiB at 0x38000000
    Zone ranges:
      Normal   [mem 0x0000000000000000-0x000000002fffffff]
      HighMem  [mem 0x0000000030000000-0x000000003fffffff]
    Movable zone start for each node
    Early memory node ranges
      node   0: [mem 0x0000000000000000-0x000000003fffffff]
    Initmem setup node 0 [mem 0x0000000000000000-0x000000003fffffff]
    percpu: Embedded 15 pages/cpu s30028 r8192 d23220 u61440
    Built 1 zonelists, mobility grouping on.  Total pages: 260416
    Kernel command line: console=ttyPS0,115200n8 root=/dev/ram rw initrd=0x00800000,16M earlyprintk mtdparts=physmap-flash.0:512K(nor-fsbl),512K(nor-u-boot),5M(nor-linux),9M(nor-user),1M(nor-scratch),-(nor-rootfs)
    Dentry cache hash table entries: 131072 (order: 7, 524288 bytes, linear)
    Inode-cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
    mem auto-init: stack:off, heap alloc:off, heap free:off
    Memory: 825596K/1048576K available (10240K kernel code, 852K rwdata, 7196K rodata, 44032K init, 168K bss, 91908K reserved, 131072K cma-reserved, 131072K highmem)
    rcu: Preemptible hierarchical RCU implementation.
    rcu:    RCU event tracing is enabled.
    rcu:    RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
            Trampoline variant of Tasks RCU enabled.
    rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
    rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
    NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
    efuse mapped to (ptrval)
    slcr mapped to (ptrval)
    L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
    L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
    L2C-310 erratum 769419 enabled
    L2C-310 enabling early BRESP for Cortex-A9
    L2C-310 full line of zeros enabled for Cortex-A9
    L2C-310 ID prefetch enabled, offset 1 lines
    L2C-310 dynamic clock gating enabled, standby mode enabled
    L2C-310 cache controller enabled, 8 ways, 512 kB
    L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
    random: get_random_bytes called from start_kernel+0x33c/0x4e8 with crng_init=0
    zynq_clock_init: clkc starts at (ptrval)
    Zynq clock init
    ps_clk frequency not specified, using 33 MHz.
    sched_clock: 64 bits at 399MHz, resolution 2ns, wraps every 4398046511103ns
    clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x5c4093a7d1, max_idle_ns: 440795210635 ns
    Switching to timer-based delay loop, resolution 2ns
    clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 447945978 ns
    timer #0 at (ptrval), irq=25
    Console: colour dummy device 80x30
    Calibrating delay loop (skipped), value calculated using timer frequency.. 799.99 BogoMIPS (lpj=3999999)
    pid_max: default: 32768 minimum: 301
    Mount-cache hash table entries: 2048 (order: 1, 8192 bytes, linear)
    Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes, linear)
    CPU: Testing write buffer coherency: ok
    CPU0: Spectre v2: using BPIALL workaround
    CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
    Setting up static identity map for 0x100000 - 0x100060
    rcu: Hierarchical SRCU implementation.
    smp: Bringing up secondary CPUs ...
    CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
    CPU1: Spectre v2: using BPIALL workaround
    smp: Brought up 1 node, 2 CPUs
    SMP: Total of 2 processors activated (1599.99 BogoMIPS).
    CPU: All CPU(s) started in SVC mode.
    devtmpfs: initialized
    VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
    clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
    futex hash table entries: 512 (order: 3, 32768 bytes, linear)
    pinctrl core: initialized pinctrl subsystem
    NET: Registered protocol family 16
    DMA: preallocated 256 KiB pool for atomic coherent allocations
    thermal_sys: Registered thermal governor 'step_wise'
    cpuidle: using governor ladder
    hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
    hw-breakpoint: maximum watchpoint size is 4 bytes.
    zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0x(ptrval)
    SCSI subsystem initialized
    usbcore: registered new interface driver usbfs
    usbcore: registered new interface driver hub
    usbcore: registered new device driver usb
    mc: Linux media interface: v0.10
    videodev: Linux video capture interface: v2.00
    jesd204: created con: id=0, topo=0, link=0, /axi/spi@e0006000/hmc7044@2 <-> /fpga-axi@0/axi-adxcvr-tx@44a80000
    jesd204: created con: id=1, topo=0, link=1, /axi/spi@e0006000/hmc7044@2 <-> /fpga-axi@0/axi-adxcvr-rx@44a60000
    jesd204: created con: id=2, topo=0, link=0, /fpga-axi@0/axi-adxcvr-tx@44a80000 <-> /fpga-axi@0/axi-jesd204-tx@44a90000
    jesd204: created con: id=3, topo=0, link=1, /fpga-axi@0/axi-adxcvr-rx@44a60000 <-> /fpga-axi@0/axi-jesd204-rx@44aa0000
    jesd204: created con: id=4, topo=0, link=1, /fpga-axi@0/axi-jesd204-rx@44aa0000 <-> /axi/spi@e0006000/adrv9009-phy@0
    jesd204: created con: id=5, topo=0, link=0, /fpga-axi@0/axi-jesd204-tx@44a90000 <-> /axi/spi@e0006000/adrv9009-phy@0
    jesd204: /axi/spi@e0006000/adrv9009-phy@0: JESD204[0] transition uninitialized -> initialized
    jesd204: /axi/spi@e0006000/adrv9009-phy@0: JESD204[1] transition uninitialized -> initialized
    jesd204: found 6 devices and 1 topologies
    FPGA manager framework
    Advanced Linux Sound Architecture Driver Initialized.
    clocksource: Switched to clocksource arm_global_timer
    NET: Registered protocol family 2
    tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes, linear)
    TCP established hash table entries: 8192 (order: 3, 32768 bytes, linear)
    TCP bind hash table entries: 8192 (order: 4, 65536 bytes, linear)
    TCP: Hash tables configured (established 8192 bind 8192)
    UDP hash table entries: 512 (order: 2, 16384 bytes, linear)
    UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear)
    NET: Registered protocol family 1
    hw perfevents: no interrupt-affinity property for /pmu@f8891000, guessing.
    hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
    workingset: timestamp_bits=14 max_order=18 bucket_order=4
    bounce: pool size: 64 pages
    io scheduler mq-deadline registered
    io scheduler kyber registered
    zynq-pinctrl 700.pinctrl: zynq pinctrl initialized
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-241330
    dma-pl330 f8003000.dmac:        DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
    brd: module loaded
    loop: module loaded
    Registered mathworks_ip class
    spi-nor spi0.0: unrecognized JEDEC id bytes: 00 00 00 00 00 00
    MACsec IEEE 802.1AE
    libphy: Fixed MDIO Bus: probed
    tun: Universal TUN/TAP device driver, 1.6
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    libphy: MACB_mii_bus: probed
    macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 38 (1a:78:ea:d8:70:54)
    usbcore: registered new interface driver asix
    usbcore: registered new interface driver ax88179_178a
    usbcore: registered new interface driver cdc_ether
    usbcore: registered new interface driver net1080
    usbcore: registered new interface driver cdc_subset
    usbcore: registered new interface driver zaurus
    usbcore: registered new interface driver cdc_ncm
    ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
    usbcore: registered new interface driver uas
    usbcore: registered new interface driver usb-storage
    usbcore: registered new interface driver usbserial_generic
    usbserial: USB Serial support registered for generic
    usbcore: registered new interface driver ftdi_sio
    usbserial: USB Serial support registered for FTDI USB Serial Device
    usbcore: registered new interface driver upd78f0730
    usbserial: USB Serial support registered for upd78f0730
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    udc-core: couldn't find an available UDC - added [g_mass_storage] to list of pending drivers
    i2c /dev entries driver
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    cdns-i2c e0004000.i2c: 400 kHz mmio e0004000 irq 32
    pca954x 0-0074: probe failed
    usbcore: registered new interface driver uvcvideo
    USB Video Class driver (1.1.1)
    gspca_main: v2.14.0 registered
    cdns-wdt f8005000.watchdog: Xilinx Watchdog Timer with timeout 10s
    Xilinx Zynq CpuIdle Driver started
    sdhci: Secure Digital Host Controller Interface driver
    sdhci: Copyright(c) Pierre Ossman
    sdhci-pltfm: SDHCI platform and OF driver helper
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    ledtrig-cpu: registered to indicate activity on CPUs
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    hid: raw HID events driver (C) Jiri Kosina
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    usbcore: registered new interface driver usbhid
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    usbhid: USB HID core driver
    adrv9009 spi1.0: adrv9009_probe : enter
    mmc0: SDHCI controller on e0100000.mmc [e0100000.mmc] using ADMA
    hmc7044 spi1.2: PLL1: Holdover, CLKIN0 @ 40000000 Hz, PFD: 320 kHz - PLL2: Locked @ 2949.120000 MHz
    jesd204: /axi/spi@e0006000/hmc7044@2,jesd204:1,parent=spi1.2: Using as SYSREF provider
    axi_adxcvr 44a60000.axi-adxcvr-rx: AXI-ADXCVR-RX (16.01.a) using CPLL on GTX2 at 0x44A60000. Number of lanes: 2.
    axi_adxcvr 44a80000.axi-adxcvr-tx: AXI-ADXCVR-TX (16.01.a) using QPLL on GTX2 at 0x44A80000. Number of lanes: 2.
    fpga_manager fpga0: Xilinx Zynq FPGA Manager registered
    usbcore: registered new interface driver snd-usb-audio
    NET: Registered protocol family 10
    Segment Routing with IPv6
    sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
    NET: Registered protocol family 17
    NET: Registered protocol family 36
    Registering SWP/SWPB emulation handler
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 35, base_baud = 3125000) is a xuartps
    printk: console [ttyPS0] enabled
    printk: console [ttyPS0] enabled
    printk: bootconsole [earlycon0] disabled
    printk: bootconsole [earlycon0] disabled
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    adrv9009 spi1.0: adrv9009_probe : enter
    cf_axi_dds 44a14000.axi-adrv9009-tx-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.00.b) at 0x44A14000 mapped to 0x(ptrval), probed DDS AD9371
    axi-jesd204-rx 44aa0000.axi-jesd204-rx: AXI-JESD204-RX (1.02.a) at 0x44AA0000. Encoder 8b10b, width 4/0, lanes 2, jesd204-fsm.
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition initialized -> probed
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition initialized -> probed
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition probed -> idle
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition probed -> idle
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition idle -> device_init
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition idle -> device_init
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition device_init -> link_init
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition device_init -> link_init
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_init -> link_supported
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_init -> link_supported
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_supported -> link_pre_setup
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_supported -> link_pre_setup
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_pre_setup -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_pre_setup -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition clk_sync_stage1 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition clk_sync_stage1 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition clk_sync_stage2 -> clk_sync_stage3
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition clk_sync_stage2 -> clk_sync_stage3
    adrv9009 spi1.0: ADIHAL_resetHw
    adrv9009 spi1.0: ERROR: 346: TALISE_verifySpiReadWrite(): Cannot read from a low SPI address
    adrv9009 spi1.0: adrv9009_jesd204_link_setup:5805 (ret 10)
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] In link_setup got error from cb: -14 (ignoring!)
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition clk_sync_stage3 -> link_setup
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition clk_sync_stage3 -> link_setup
    adrv9009 spi1.0: adrv9009_jesd204_setup_stage1:5861 Unexpected MCS sync status (0x0)
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] In opt_setup_stage1 got error from cb: -14 (ignoring!)
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_setup -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_setup -> opt_setup_stage1
    adrv9009 spi1.0: adrv9009_jesd204_setup_stage2:5891 Unexpected MCS sync status (0x0)
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] In opt_setup_stage2 got error from cb: -14 (ignoring!)
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage1 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage1 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage2 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage2 -> opt_setup_stage3
    random: fast init done
    adrv9009 spi1.0: ERROR: 179: ARM Mailbox Busy. Command not executed in TALISE_sendArmCommand()
    adrv9009 spi1.0: adrv9009_jesd204_setup_stage4:6040 (ret 5)
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] In opt_setup_stage4 got error from cb: -14 (ignoring!)
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage3 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage3 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage4 -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage4 -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage5 -> clocks_enable
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage5 -> clocks_enable
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition clocks_enable -> link_enable
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition clocks_enable -> link_enable
    axi-jesd204-rx 44aa0000.axi-jesd204-rx: axi_jesd204_rx_jesd204_link_running: Link1 status failed (CGS)
    jesd204: /fpga-axi@0/axi-jesd204-rx@44aa0000,jesd204:2,parent=44aa0000.axi-jesd204-rx: JESD204[1] In link_running got error from cb: -1 (ignoring!)
    axi-jesd204-tx 44a90000.axi-jesd204-tx: axi_jesd204_tx_jesd204_link_running: Link0 status failed (CGS)
    jesd204: /fpga-axi@0/axi-jesd204-tx@44a90000,jesd204:3,parent=44a90000.axi-jesd204-tx: JESD204[0] In link_running got error from cb: -1 (ignoring!)
    adrv9009 spi1.0: Link0 TAL_DEFRAMER_A deframerStatus 0x8
    adrv9009 spi1.0: Link1 TAL_FRAMER_A framerStatus 0x0
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_enable -> link_running
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_enable -> link_running
    adrv9009 spi1.0: ERROR: 180: Device not in radioOff/IDLE state. Error in TALISE_enableTrackingCals()
    adrv9009 spi1.0: adrv9009_jesd204_post_running_stage:6141 (ret 5)
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] In opt_post_running_stage got error from cb: -14 (ignoring!)
    adrv9009 spi1.0: ERROR: 32: TALISE_gpIntHandler(): AUXCLK PLL is not locked
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_running -> opt_post_running_stage
    adrv9009 spi1.0: AUX PLL lock detect reset
    adrv9009 spi1.0: ARM Command Wait TimeOut
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_running -> opt_post_running_stage
    adrv9009 spi1.0: (null)
    adrv9009 spi1.0: (null)
    axi-jesd204-tx 44a90000.axi-jesd204-tx: AXI-JESD204-TX (1.01.a) at 0x44A90000. Encoder 8b10b, width 4/0, lanes 2, jesd204-fsm.
    adrv9009 spi1.0: GP Interrupt Status 0x5 Action: ERR_RESET_FULL
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    cf_axi_adc 44a00000.axi-adrv9009-rx-hpc: ADI AIM (10.00.b) at 0x44A00000 mapped to 0x(ptrval), probed ADC ADRV9009 as MASTER
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    ALSA device list:
      No soundcards found.
    Warning: unable to open an initial console.
    Freeing unused kernel memory: 44032K
    Run /init as init process
    udevd[77]: starting version 3.2.9
    random: udevd: uninitialized urandom read (16 bytes read)
    random: udevd: uninitialized urandom read (16 bytes read)
    random: udevd: uninitialized urandom read (16 bytes read)
    udevd[78]: starting eudev-3.2.9
    urandom_read: 2 callbacks suppressed
    random: dd: uninitialized urandom read (512 bytes read)
    samplemodule: loading out-of-tree module taints kernel.
    <1>Hello module world : DRIVER !!
    <1>Module parameters were (0xdeadbeef) and "default"
    <1>Config_of ok.
    Sorry, registering the character device  failed with
    macb e000b000.ethernet eth0: PHY [e000b000.ethernet-ffffffff:00] driver [Marvell 88E1510] (irq=POLL)
    macb e000b000.ethernet eth0: configuring for phy/rgmii-id link mode
    random: dbus-uuidgen: uninitialized urandom read (12 bytes read)
    random: dbus-uuidgen: uninitialized urandom read (8 bytes read)
    random: dbus-daemon: uninitialized urandom read (12 bytes read)
    random: crng init done
    random: 1 urandom warning(s) missed due to ratelimiting
    
    root@ETRX_petalinux:~#

    #include <dt-bindings/iio/frequency/ad9528.h>
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    
    / {
    	clocks {
    		adrv9009_clkin: clock@0 {
    			compatible = "fixed-clock";
    
    			clock-frequency = <12288000>;
    			clock-output-names = "adrv9009_ext_refclk";
    			#clock-cells = <0>;
    		};
    	};
    };
    
    &fmc_spi {
    
    //	clk0_ad9528: ad9528-1@0 {
    //		compatible = "adi,ad9528";
    //		reg = <0>;
    //
    //		#address-cells = <1>;
    //		#size-cells = <0>;
    //
    //		spi-max-frequency = <10000000>;
    //		//adi,spi-3wire-enable;
    //
    //		clock-output-names = "ad9528-1_out0", "ad9528-1_out1", "ad9528-1_out2",
    //			"ad9528-1_out3", "ad9528-1_out4", "ad9528-1_out5", "ad9528-1_out6",
    //			"ad9528-1_out7", "ad9528-1_out8", "ad9528-1_out9", "ad9528-1_out10",
    //			"ad9528-1_out11", "ad9528-1_out12", "ad9528-1_out13";
    //		#clock-cells = <1>;
    //
    //		adi,vcxo-freq = <122880000>;
    //
    //		adi,refa-enable;
    //		adi,refa-diff-rcv-enable;
    //		adi,refa-r-div = <1>;
    //		adi,osc-in-cmos-neg-inp-enable;
    //
    //		/* PLL1 config */
    //		adi,pll1-feedback-div = <4>;
    //		adi,pll1-charge-pump-current-nA = <5000>;
    //
    //		/* PLL2 config */
    //		adi,pll2-vco-div-m1 = <3>; /* use 5 for 184320000 output device clock */
    //		adi,pll2-n2-div = <10>; /* N / M1 */
    //		adi,pll2-r1-div = <1>;
    //		adi,pll2-charge-pump-current-nA = <805000>;
    //
    //		/* SYSREF config */
    //		adi,sysref-src = <SYSREF_SRC_INTERNAL>;
    //		adi,sysref-pattern-mode = <SYSREF_PATTERN_CONTINUOUS>;
    //		adi,sysref-k-div = <512>;
    //		adi,sysref-request-enable;
    //		adi,sysref-nshot-mode = <SYSREF_NSHOT_4_PULSES>;
    //		adi,sysref-request-trigger-mode = <SYSREF_LEVEL_HIGH>;
    //
    //		adi,rpole2 = <RPOLE2_900_OHM>;
    //		adi,rzero = <RZERO_1850_OHM>;
    //		adi,cpole1 = <CPOLE1_16_PF>;
    //
    //		adi,status-mon-pin0-function-select = <1>; /* PLL1 & PLL2 Locked */
    //		adi,status-mon-pin1-function-select = <7>; /* REFA Correct */
    //
    //		ad9528_0_c13: channel@13 {
    //			reg = <13>;
    //			adi,extended-name = "DEV_CLK";
    //			adi,driver-mode = <DRIVER_MODE_LVDS>;
    //			adi,divider-phase = <0>;
    //			adi,channel-divider = <10>;
    //			adi,signal-source = <SOURCE_VCO>;
    //		};
    //
    //		ad9528_0_c1: channel@1 {
    //			reg = <1>;
    //			adi,extended-name = "FMC_CLK";
    //			adi,driver-mode = <DRIVER_MODE_LVDS>;
    //			adi,divider-phase = <0>;
    //			adi,channel-divider = <10>;
    //			adi,signal-source = <SOURCE_VCO>;
    //		};
    //
    //		ad9528_0_c12: channel@12 {
    //			reg = <12>;
    //			adi,extended-name = "DEV_SYSREF";
    //			adi,driver-mode = <DRIVER_MODE_LVDS>;
    //			adi,divider-phase = <0>;
    //			adi,channel-divider = <10>;
    //			adi,signal-source = <SOURCE_SYSREF_VCO>;
    //		};
    //
    //		ad9528_0_c3: channel@3 {
    //			reg = <3>;
    //			adi,extended-name = "FMC_SYSREF";
    //			adi,driver-mode = <DRIVER_MODE_LVDS>;
    //			adi,divider-phase = <0>;
    //			adi,channel-divider = <10>;
    //			adi,signal-source = <SOURCE_SYSREF_VCO>;
    //		};
    //	};
    
    	is-decoded-cs = <1>;
    
    	trx0_adrv9009: adrv9009-phy@0 {
    		compatible = "adrv9009";
    		reg = <0>; //ADRV A SPI CS 0
    
    		#address-cells = <1>;
    		#size-cells = <0>;
    
    		/* SPI Setup */
    		spi-max-frequency = <25000000>;
    
    		interrupt-parent = <&gpio0>;
    		interrupts = <105 IRQ_TYPE_EDGE_RISING>;
    
    		/* Clocks */
    		clocks = <&axi_adrv9009_rx_jesd>, <&axi_adrv9009_tx_jesd>,
    			<&hmc7044 0>, <&hmc7044 5>, <&hmc7044 1>, <&hmc7044 8>,
    			<&hmc7044 4>;
    
    		clock-names = "jesd_rx_clk", "jesd_tx_clk",
    			"dev_clk", "fmc_clk", "sysref_dev_clk",
    			"sysref_fmc_clk", "fmc2_clk";
    
    
    		clock-output-names = "rx_sampl_clk", "rx_os_sampl_clk", "tx_sampl_clk";
    		#clock-cells = <1>;
    
    		/* JESD204 */
    
    		/* JESD204 RX */
    		adi,jesd204-framer-a-bank-id = <1>;
    		adi,jesd204-framer-a-device-id = <0>;
    		adi,jesd204-framer-a-lane0-id = <0>;
    		adi,jesd204-framer-a-m = <4>;
    		adi,jesd204-framer-a-k = <32>;
    		adi,jesd204-framer-a-f = <4>;
    		adi,jesd204-framer-a-np = <16>;
    		adi,jesd204-framer-a-scramble = <1>;
    		adi,jesd204-framer-a-external-sysref = <1>;
    		adi,jesd204-framer-a-serializer-lanes-enabled = <0x03>;
    		adi,jesd204-framer-a-serializer-lane-crossbar = <0xE4>;
    		adi,jesd204-framer-a-lmfc-offset = <31>;
    		adi,jesd204-framer-a-new-sysref-on-relink = <0>;
    		adi,jesd204-framer-a-syncb-in-select = <0>;
    		adi,jesd204-framer-a-over-sample = <0>;
    		adi,jesd204-framer-a-syncb-in-lvds-mode = <1>;
    		adi,jesd204-framer-a-syncb-in-lvds-pn-invert = <0>;
    		adi,jesd204-framer-a-enable-manual-lane-xbar = <0>;
    
    		/* JESD204 OBS */
    		adi,jesd204-framer-b-bank-id = <0>;
    		adi,jesd204-framer-b-device-id = <0>;
    		adi,jesd204-framer-b-lane0-id = <0>;
    		adi,jesd204-framer-b-m = <0>;
    		adi,jesd204-framer-b-k = <32>;
    		adi,jesd204-framer-b-f = <2>;
    		adi,jesd204-framer-b-np = <16>;
    		adi,jesd204-framer-b-scramble = <1>;
    		adi,jesd204-framer-b-external-sysref = <1>;
    		adi,jesd204-framer-b-serializer-lanes-enabled = <0x00>;
    		adi,jesd204-framer-b-serializer-lane-crossbar = <0xE4>;
    		adi,jesd204-framer-b-lmfc-offset = <31>;
    		adi,jesd204-framer-b-new-sysref-on-relink = <0>;
    		adi,jesd204-framer-b-syncb-in-select = <1>;
    		adi,jesd204-framer-b-over-sample = <0>;
    		adi,jesd204-framer-b-syncb-in-lvds-mode = <1>;
    		adi,jesd204-framer-b-syncb-in-lvds-pn-invert = <0>;
    		adi,jesd204-framer-b-enable-manual-lane-xbar = <0>;
    
    		/* JESD204 TX */
    		adi,jesd204-deframer-a-bank-id = <0>;
    		adi,jesd204-deframer-a-device-id = <0>;
    		adi,jesd204-deframer-a-lane0-id = <0>;
    		adi,jesd204-deframer-a-m = <4>;
    		adi,jesd204-deframer-a-k = <16>;
    		adi,jesd204-deframer-a-scramble = <1>;
    		adi,jesd204-deframer-a-external-sysref = <1>;
    		adi,jesd204-deframer-a-deserializer-lanes-enabled = <0x03>;
    		adi,jesd204-deframer-a-deserializer-lane-crossbar = <0xE4>;
    		adi,jesd204-deframer-a-lmfc-offset = <7>;
    		adi,jesd204-deframer-a-new-sysref-on-relink = <0>;
    		adi,jesd204-deframer-a-syncb-out-select = <0>;
    		adi,jesd204-deframer-a-np = <16>;
    		adi,jesd204-deframer-a-syncb-out-lvds-mode = <1>;
    		adi,jesd204-deframer-a-syncb-out-lvds-pn-invert = <0>;
    		adi,jesd204-deframer-a-syncb-out-cmos-slew-rate = <0>;
    		adi,jesd204-deframer-a-syncb-out-cmos-drive-level = <0>;
    		adi,jesd204-deframer-a-enable-manual-lane-xbar = <0>;
    
    		adi,jesd204-ser-amplitude = <15>;
    		adi,jesd204-ser-pre-emphasis = <1>;
    		adi,jesd204-ser-invert-lane-polarity = <0x3>;
    		adi,jesd204-des-invert-lane-polarity = <0x3>;
    		adi,jesd204-des-eq-setting = <1>;
    		adi,jesd204-sysref-lvds-mode = <1>;
    		adi,jesd204-sysref-lvds-pn-invert = <0>;
    
    		/* RX */
    
    		adi,rx-profile-rx-fir-gain_db = <(-6)>;
    		adi,rx-profile-rx-fir-num-fir-coefs = <48>;
    		//adi,rx-profile-rx-fir-coefs = /bits/ 16 <(-8) (-22) (32) (50) (-68) (-106) (141) (199) (-258) (-352) (430) (572) (-691) (-903) (1069) (1392) (-1644) (-2172) (2569) (3574) (-4364) (-7129) (9355) (31095) (31095) (9355) (-7129) (-4364) (3574) (2569) (-2172) (-1644) (1392) (1069) (-903) (-691) (572) (430) (-352) (-258) (199) (141) (-106) (-68) (50) (32) (-22) (-8)>;
     		//adi,rx-profile-rx-fir-coefs = /bits/ 16 < (3) ( 6) ( 9) ( 8) ( 0) ( -19) ( -44) ( -64) ( -60) ( -17) ( 68) ( 175) ( 258) ( 256) ( 122) ( -146) ( -484) ( -758) ( -804) ( -495) ( 178) ( 1058) ( 1828) ( 2098) ( 1547) ( 97) ( -1975) (  -4030) ( -5196) ( -4624) ( -1784) ( 3286) ( 9894) ( 16805) ( 22544) ( 25799) ( 25799) ( 22544) ( 16805) ( 9894) ( 3286) ( -1784) ( -4624) ( -5196) ( -4030) ( -1975) ( 97) ( 1547) ( 2098) ( 1828) ( 1058) ( 178) ( -495) ( -804) ( -758) ( -484) ( -146) ( 122) ( 256) ( 258) ( 175) ( 68) ( -17) ( -60) ( -64) ( -44) ( -19) ( 0) ( 8) ( 9) ( 6) ( 3) >;
    		adi,rx-profile-rx-fir-coefs = /bits/ 16 <(-9) (-18) (31) (42) (-65) (-89) (132) (168) (-240) (-298) (396) (486) (-632) (-770) (968) (1163) (-1530) (-1862) (2369) (3051) (-4066) (-5983) (9689) (29830) (29830) (9689) (-5983) (-4066) (3051) (2369) (-1862) (-1530) (1163) (968) (-770) (-632) (486) (396) (-298) (-240) (168) (132) (-89) (-65) (42) (31) (-18) (-9)>;
    		
    		adi,rx-profile-rx-fir-decimation = <2>;
    		adi,rx-profile-rx-dec5-decimation = <4>;
    		adi,rx-profile-rhb1-decimation = <2>;
    		adi,rx-profile-rx-output-rate_khz = <122880>;
    		adi,rx-profile-rf-bandwidth_hz = <100000000>;
    		adi,rx-profile-rx-bbf3d-bcorner_khz = <100000>;
    		adi,rx-profile-rx-adc-profile = /bits/ 16 <265 146 181 90 1280 366 1257 27 1258 17 718 39 48 46 27 161 0 0 0 0 40 0 7 6 42 0 7 6 42 0 25 27 0 0 25 27 0 0 165 44 31 905>;
    		adi,rx-profile-rx-ddc-mode = <0>;
    
    		adi,rx-nco-shifter-band-a-input-band-width_khz = <0>;
    		adi,rx-nco-shifter-band-a-input-center-freq_khz = <0>;
    		adi,rx-nco-shifter-band-a-nco1-freq_khz = <0>;
    		adi,rx-nco-shifter-band-a-nco2-freq_khz = <0>;
    		adi,rx-nco-shifter-band-binput-band-width_khz = <0>;
    		adi,rx-nco-shifter-band-binput-center-freq_khz = <0>;
    		adi,rx-nco-shifter-band-bnco1-freq_khz = <0>;
    		adi,rx-nco-shifter-band-bnco2-freq_khz = <0>;
    
    		adi,rx-gain-control-gain-mode = <0>;
    		adi,rx-gain-control-rx1-gain-index = <255>;
    		adi,rx-gain-control-rx2-gain-index = <255>;
    		adi,rx-gain-control-rx1-max-gain-index = <255>;
    		adi,rx-gain-control-rx1-min-gain-index = <195>;
    		adi,rx-gain-control-rx2-max-gain-index = <255>;
    		adi,rx-gain-control-rx2-min-gain-index = <195>;
    
    		adi,rx-settings-framer-sel = <0>;
    		adi,rx-settings-rx-channels = <3>;
    
    		/* ORX */
    
    		adi,orx-profile-rx-fir-gain_db = <(-6)>;
    		adi,orx-profile-rx-fir-num-fir-coefs = <48>;
    		adi,orx-profile-rx-fir-coefs = /bits/ 16  <(-9) (-18) (31) (42) (-65) (-89) (132) (168) (-240) (-298) (396) (486) (-632) (-770) (968) (1163) (-1530) (-1862) (2369) (3051) (-4066) (-5983) (9689) (29830) (29830) (9689) (-5983) (-4066) (3051) (2369) (-1862) (-1530) (1163) (968) (-770) (-632) (486) (396) (-298) (-240) (168) (132) (-89) (-65) (42) (31) (-18) (-9)>;
    		adi,orx-profile-rx-fir-decimation = <2>;
    		adi,orx-profile-rx-dec5-decimation = <4>;
    		adi,orx-profile-rhb1-decimation = <2>;
    		adi,orx-profile-orx-output-rate_khz = <122880>;
    		adi,orx-profile-rf-bandwidth_hz = <100000000>;
    		adi,orx-profile-rx-bbf3d-bcorner_khz = <225000>;
    		adi,orx-profile-orx-low-pass-adc-profile = /bits/ 16  <265 146 181 90 1280 366 1257 27 1258 17 718 39 48 46 27 161 0 0 0 0 40 0 7 6 42 0 7 6 42 0 25 27 0 0 25 27 0 0 165 44 31 905>;
    		adi,orx-profile-orx-band-pass-adc-profile = /bits/ 16  <265 146 181 90 1280 366 1257 27 1258 17 718 39 48 46 27 161 0 0 0 0 40 0 7 6 42 0 7 6 42 0 25 27 0 0 25 27 0 0 165 44 31 905>;
    		adi,orx-profile-orx-ddc-mode = <0>;
    		adi,orx-profile-orx-merge-filter = /bits/ 16  <0 0 0 0 0 0 0 0 0 0 0 0>;
    
    		adi,orx-gain-control-gain-mode = <0>;
    		adi,orx-gain-control-orx1-gain-index = <255>;
    		adi,orx-gain-control-orx2-gain-index = <255>;
    		adi,orx-gain-control-orx1-max-gain-index = <255>;
    		adi,orx-gain-control-orx1-min-gain-index = <195>;
    		adi,orx-gain-control-orx2-max-gain-index = <255>;
    		adi,orx-gain-control-orx2-min-gain-index = <195>;
    
    		adi,obs-settings-framer-sel = <1>;
    		adi,obs-settings-obs-rx-channels-enable = <3>;
    		adi,obs-settings-obs-rx-lo-source = <0>;
    
    		/* TX */
    
    		adi,tx-profile-tx-fir-gain_db = <6>;
    		adi,tx-profile-tx-fir-num-fir-coefs = <80>;
    		adi,tx-profile-tx-fir-coefs = /bits/ 16  <(0) (0) (0) (1) (0) (-3) (1) (7) (-3) (-13) (7) (25) (-14) (-42) (27) (69) (-46) (-107) (74) (160) (-115) (-229) (184) (336) (-264) (-468) (382) (653) (-538) (-904) (754) (1269) (-1056) (-1842) (1486) (2879) (-2031) (-4846) (3816) (16221) (16221) (3816) (-4846) (-2031) (2879) (1486) (-1842) (-1056) (1269) (754) (-904) (-538) (653) (382) (-468) (-264) (336) (184) (-229) (-115) (160) (74) (-107) (-46) (69) (27) (-42) (-14) (25) (7) (-13) (-3) (7) (1) (-3) (0) (1) (0) (0) (0)>;
    		//adi,tx-profile-tx-fir-coefs = /bits/ 16  < (0) ( -1) ( 1) ( -1) ( -3) ( 11) ( -14) ( 12) ( 20) ( -72) ( 85) ( -69) ( -88) ( 302) ( -340) ( 264) ( 284) ( -952) ( 1010) ( -755) ( -723) ( 2372) ( -2338) ( 1721) ( 1515) ( -4823) ( 4385) ( -3190) ( -2583) ( 8316) ( -6637) ( 5054) ( 3611) ( -12551) ( 7717) ( -7242) ( -3574) ( 19348) ( 8) ( 21575) ( 21575) ( 8) ( 19348) ( -3574) ( -7242) ( 7717) ( -12551) ( 3611) ( 5054) ( -6637) ( 8316) ( -2583) ( -3190) ( 4385) ( -4823) ( 1515) ( 1721) ( -2338) ( 2372) ( -723) ( -755) ( 1010) ( -952) ( 284) ( 264) ( -340) ( 302) ( -88) ( -69) ( 85) ( -72) ( 20) ( 12) ( -14) ( 11) ( -3) ( -1) ( 1) ( -1) ( 0)>;
    		adi,tx-profile-dac-div = <1>;
    
    		adi,tx-profile-tx-fir-interpolation = <2>;
    		adi,tx-profile-thb1-interpolation = <2>;
    		adi,tx-profile-thb2-interpolation = <2>;
    		adi,tx-profile-thb3-interpolation = <2>;
    		adi,tx-profile-tx-int5-interpolation = <1>;
    		adi,tx-profile-tx-input-rate_khz = <122880>;
    		adi,tx-profile-primary-sig-bandwidth_hz = <50000000>;
    		adi,tx-profile-rf-bandwidth_hz = <100000000>;
    		adi,tx-profile-tx-dac3d-bcorner_khz = <187000>;
    		adi,tx-profile-tx-bbf3d-bcorner_khz = <56000>;
    		adi,tx-profile-loop-back-adc-profile = /bits/ 16 <265 146 181 90 1280 366 1257 27 1258 17 718 39 48 46 27 161 0 0 0 0 40 0 7 6 42 0 7 6 42 0 25 27 0 0 25 27 0 0 165 44 31 905>;
    
    		adi,tx-settings-deframer-sel = <0>;
    		adi,tx-settings-tx-channels = <3>;
    		adi,tx-settings-tx-atten-step-size = <0>;
    		adi,tx-settings-tx1-atten_md-b = <10000>;
    		adi,tx-settings-tx2-atten_md-b = <10000>;
    		adi,tx-settings-dis-tx-data-if-pll-unlock = <2>;
    
    		/* Clocks */
    
    		adi,dig-clocks-device-clock_khz = <245760>;
    		adi,dig-clocks-clk-pll-vco-freq_khz = <9830400>;
    		adi,dig-clocks-clk-pll-hs-div = <1>;
    		adi,dig-clocks-rf-pll-use-external-lo = <0>;
    		adi,dig-clocks-rf-pll-phase-sync-mode = <0>;
    
    		/* AGC */
    
    		adi,rxagc-peak-agc-under-range-low-interval_ns = <205>;
    		adi,rxagc-peak-agc-under-range-mid-interval = <2>;
    		adi,rxagc-peak-agc-under-range-high-interval = <4>;
    		adi,rxagc-peak-apd-high-thresh = <39>;
    		adi,rxagc-peak-apd-low-gain-mode-high-thresh = <36>;
    		adi,rxagc-peak-apd-low-thresh = <23>;
    		adi,rxagc-peak-apd-low-gain-mode-low-thresh = <19>;
    		adi,rxagc-peak-apd-upper-thresh-peak-exceeded-cnt = <6>;
    		adi,rxagc-peak-apd-lower-thresh-peak-exceeded-cnt = <3>;
    		adi,rxagc-peak-apd-gain-step-attack = <4>;
    		adi,rxagc-peak-apd-gain-step-recovery = <2>;
    		adi,rxagc-peak-enable-hb2-overload = <1>;
    		adi,rxagc-peak-hb2-overload-duration-cnt = <1>;
    		adi,rxagc-peak-hb2-overload-thresh-cnt = <4>;
    		adi,rxagc-peak-hb2-high-thresh = <181>;
    		adi,rxagc-peak-hb2-under-range-low-thresh = <45>;
    		adi,rxagc-peak-hb2-under-range-mid-thresh = <90>;
    		adi,rxagc-peak-hb2-under-range-high-thresh = <128>;
    		adi,rxagc-peak-hb2-upper-thresh-peak-exceeded-cnt = <6>;
    		adi,rxagc-peak-hb2-lower-thresh-peak-exceeded-cnt = <3>;
    		adi,rxagc-peak-hb2-gain-step-high-recovery = <2>;
    		adi,rxagc-peak-hb2-gain-step-low-recovery = <4>;
    		adi,rxagc-peak-hb2-gain-step-mid-recovery = <8>;
    		adi,rxagc-peak-hb2-gain-step-attack = <4>;
    		adi,rxagc-peak-hb2-overload-power-mode = <1>;
    		adi,rxagc-peak-hb2-ovrg-sel = <0>;
    		adi,rxagc-peak-hb2-thresh-config = <3>;
    
    		adi,rxagc-power-power-enable-measurement = <1>;
    		adi,rxagc-power-power-use-rfir-out = <1>;
    		adi,rxagc-power-power-use-bbdc2 = <0>;
    		adi,rxagc-power-under-range-high-power-thresh = <9>;
    		adi,rxagc-power-under-range-low-power-thresh = <2>;
    		adi,rxagc-power-under-range-high-power-gain-step-recovery = <4>;
    		adi,rxagc-power-under-range-low-power-gain-step-recovery = <4>;
    		adi,rxagc-power-power-measurement-duration = <5>;
    		adi,rxagc-power-rx1-tdd-power-meas-duration = <5>;
    		adi,rxagc-power-rx1-tdd-power-meas-delay = <1>;
    		adi,rxagc-power-rx2-tdd-power-meas-duration = <5>;
    		adi,rxagc-power-rx2-tdd-power-meas-delay = <1>;
    		adi,rxagc-power-upper0-power-thresh = <2>;
    		adi,rxagc-power-upper1-power-thresh = <0>;
    		adi,rxagc-power-power-log-shift = <0>;
    
    		adi,rxagc-agc-peak-wait-time = <4>;
    		adi,rxagc-agc-rx1-max-gain-index = <255>;
    		adi,rxagc-agc-rx1-min-gain-index = <195>;
    		adi,rxagc-agc-rx2-max-gain-index = <255>;
    		adi,rxagc-agc-rx2-min-gain-index = <195>;
    		adi,rxagc-agc-gain-update-counter_us = <250>;
    		adi,rxagc-agc-rx1-attack-delay = <10>;
    		adi,rxagc-agc-rx2-attack-delay = <10>;
    		adi,rxagc-agc-slow-loop-settling-delay = <16>;
    		adi,rxagc-agc-low-thresh-prevent-gain = <0>;
    		adi,rxagc-agc-change-gain-if-thresh-high = <1>;
    		adi,rxagc-agc-peak-thresh-gain-control-mode = <1>;
    		adi,rxagc-agc-reset-on-rxon = <0>;
    		adi,rxagc-agc-enable-sync-pulse-for-gain-counter = <0>;
    		adi,rxagc-agc-enable-ip3-optimization-thresh = <0>;
    		adi,rxagc-ip3-over-range-thresh = <31>;
    		adi,rxagc-ip3-over-range-thresh-index = <246>;
    		adi,rxagc-ip3-peak-exceeded-cnt = <4>;
    		adi,rxagc-agc-enable-fast-recovery-loop = <0>;
    
    
    		/* Misc */
    
    		adi,aux-dac-enables = <0x00>; /* Mask */
    
    		adi,aux-dac-vref0 = <3>;
    		adi,aux-dac-resolution0 = <0>;
    		adi,aux-dac-values0 = <0>;
    		adi,aux-dac-vref1 = <3>;
    		adi,aux-dac-resolution1 = <0>;
    		adi,aux-dac-values1 = <0>;
    		adi,aux-dac-vref2 = <3>;
    		adi,aux-dac-resolution2 = <0>;
    		adi,aux-dac-values2 = <0>;
    		adi,aux-dac-vref3 = <3>;
    		adi,aux-dac-resolution3 = <0>;
    		adi,aux-dac-values3 = <0>;
    		adi,aux-dac-vref4 = <3>;
    		adi,aux-dac-resolution4 = <0>;
    		adi,aux-dac-values4 = <0>;
    		adi,aux-dac-vref5 = <3>;
    		adi,aux-dac-resolution5 = <0>;
    		adi,aux-dac-values5 = <0>;
    		adi,aux-dac-vref6 = <3>;
    		adi,aux-dac-resolution6 = <0>;
    		adi,aux-dac-values6 = <0>;
    		adi,aux-dac-vref7 = <3>;
    		adi,aux-dac-resolution7 = <0>;
    		adi,aux-dac-values7 = <0>;
    		adi,aux-dac-vref8 = <3>;
    		adi,aux-dac-resolution8 = <0>;
    		adi,aux-dac-values8 = <0>;
    		adi,aux-dac-vref9 = <3>;
    		adi,aux-dac-resolution9 = <0>;
    		adi,aux-dac-values9 = <0>;
    		adi,aux-dac-vref10 = <3>;
    		adi,aux-dac-resolution10 = <0>;
    		adi,aux-dac-values10 = <0>;
    		adi,aux-dac-vref11 = <3>;
    		adi,aux-dac-resolution11 = <0>;
    		adi,aux-dac-values11 = <0>;
    
    		adi,arm-gpio-config-orx1-tx-sel0-pin-gpio-pin-sel = <0>;
    		adi,arm-gpio-config-orx1-tx-sel0-pin-polarity = <0>;
    		adi,arm-gpio-config-orx1-tx-sel0-pin-enable = <0>;
    
    		adi,arm-gpio-config-orx1-tx-sel1-pin-gpio-pin-sel = <0>;
    		adi,arm-gpio-config-orx1-tx-sel1-pin-polarity = <0>;
    		adi,arm-gpio-config-orx1-tx-sel1-pin-enable = <0>;
    		adi,arm-gpio-config-orx2-tx-sel0-pin-gpio-pin-sel = <0>;
    		adi,arm-gpio-config-orx2-tx-sel0-pin-polarity = <0>;
    		adi,arm-gpio-config-orx2-tx-sel0-pin-enable = <0>;
    
    		adi,arm-gpio-config-orx2-tx-sel1-pin-gpio-pin-sel = <0>;
    		adi,arm-gpio-config-orx2-tx-sel1-pin-polarity = <0>;
    		adi,arm-gpio-config-orx2-tx-sel1-pin-enable = <0>;
    		adi,arm-gpio-config-en-tx-tracking-cals-gpio-pin-sel = <0>;
    		adi,arm-gpio-config-en-tx-tracking-cals-polarity = <0>;
    		adi,arm-gpio-config-en-tx-tracking-cals-enable = <0>;
    
    		adi,orx-lo-cfg-disable-aux-pll-relocking = <0>;
    		adi,orx-lo-cfg-gpio-select = <19>;
    
    		adi,fhm-config-fhm-gpio-pin = <0>;
    		adi,fhm-config-fhm-min-freq_mhz = <100>;
    		adi,fhm-config-fhm-max-freq_mhz = <100>;
    
    		adi,fhm-mode-fhm-enable = <0>;
    		adi,fhm-mode-enable-mcs-sync = <0>;
    		adi,fhm-mode-fhm-trigger-mode = <0>;
    		adi,fhm-mode-fhm-exit-mode = <0>;
    		adi,fhm-mode-fhm-init-frequency_hz = <2450000000>;
    
    		adi,rx1-gain-ctrl-pin-inc-step = <1>;
    		adi,rx1-gain-ctrl-pin-dec-step = <1>;
    		adi,rx1-gain-ctrl-pin-rx-gain-inc-pin = <0>;
    		adi,rx1-gain-ctrl-pin-rx-gain-dec-pin = <1>;
    		adi,rx1-gain-ctrl-pin-enable = <0>;
    
    		adi,rx2-gain-ctrl-pin-inc-step = <1>;
    		adi,rx2-gain-ctrl-pin-dec-step = <1>;
    		adi,rx2-gain-ctrl-pin-rx-gain-inc-pin = <3>;
    		adi,rx2-gain-ctrl-pin-rx-gain-dec-pin = <4>;
    		adi,rx2-gain-ctrl-pin-enable = <0>;
    
    		adi,tx1-atten-ctrl-pin-step-size = <0>;
    		adi,tx1-atten-ctrl-pin-tx-atten-inc-pin = <4>;
    		adi,tx1-atten-ctrl-pin-tx-atten-dec-pin = <5>;
    		adi,tx1-atten-ctrl-pin-enable = <0>;
    
    		adi,tx2-atten-ctrl-pin-step-size = <0>;
    		adi,tx2-atten-ctrl-pin-tx-atten-inc-pin = <6>;
    		adi,tx2-atten-ctrl-pin-tx-atten-dec-pin = <7>;
    		adi,tx2-atten-ctrl-pin-enable = <0>;
    
    		adi,tx-pa-protection-avg-duration = <3>;
    		adi,tx-pa-protection-tx-atten-step = <2>;
    		adi,tx-pa-protection-tx1-power-threshold = <4096>;
    		adi,tx-pa-protection-tx2-power-threshold = <4096>;
    		adi,tx-pa-protection-peak-count = <4>;
    		adi,tx-pa-protection-tx1-peak-threshold = <130>;
    		adi,tx-pa-protection-tx2-peak-threshold = <130>;
    	};	
    
    	hmc7044: hmc7044@2 {
    		#address-cells = <1>;
    		#size-cells = <0>;		
    		#clock-cells = <1>;
    
    		compatible = "adi,hmc7044";
    		reg = <2>; // SPI CS 2
    		//spi-max-frequency = <10000000>;
    		spi-max-frequency = <100000>;
    		adi,sync-pin-mode = <1>;
    		adi,pll1-clkin-frequencies = <40000000 0 0 0>;
    		adi,pll1-ref-prio-ctrl = <0xE4>; /* prefer CLKIN0 */
    
    		adi,pll1-loop-bandwidth = <200>;
    
    		adi,vcxo-frequency = <122880000>;
    
    		adi,pll2-output-frequency = <2949120000>;
    
    		adi,sysref-timer-divider = <3840>;
    		adi,pulse-generator-mode = <0>;
    
    		adi,clkin0-buffer-mode = <0x0D>;
    		adi,clkin1-buffer-mode = <0x0D>;
    		adi,clkin2-buffer-mode = <0x0D>;
    		adi,clkin3-buffer-mode = <0x0D>;		
    		adi,oscin-buffer-mode = <0x07>;
    
    		adi,gpi-controls = <0x00 0x00 0x00 0x11>;
    		adi,gpo-controls = <0x1f 0x2b 0x00 0x00>;
    
    		clock-output-names = 
    			"hmc7044_out0_DEV_REFCLK_A", "hmc7044_out1_DEV_SYSREF_A",
    			"hmc7044_out2_DEV_REFCLK_B", "hmc7044_out3_DEV_SYSREF_B",
    			"hmc7044_out4_JESD_REFCLK_TX_OBS_AB", "hmc7044_out5_JESD_REFCLK_RX_AB",
    			"hmc7044_out6_CORE_CLK_TX_OBS_AB", "hmc7044_out7_CORE_CLK_RX_AB",
    			"hmc7044_out8_FPGA_SYSREF_TX_OBS_AB","hmc7044_out9_FPGA_SYSREF_RX_AB",
    			"hmc7044_out10", "hmc7044_out11",
    			"hmc7044_out12", "hmc7044_out13";				
    
    		hmc7044_c0: channel@0 {
    			reg = <0>;
    			adi,extended-name = "DEV_REFCLK_A";
    			adi,divider = <12>;	// 245760000
    			adi,driver-mode = <2>;	// LVDS
    			adi,coarse-digital-delay = <15>;
    		};
    		hmc7044_c1: channel@1 {
    			reg = <1>;
    			adi,extended-name = "DEV_SYSREF_A";
    			adi,divider = <3840>;	// 768000
    			adi,driver-mode = <1>;	// LVPECL  
    			adi,startup-mode-dynamic-enable;
    			adi,high-performance-mode-disable;
    			adi,driver-impedance-mode = <1>;
    			adi,force-mute-enable;
    			adi,control0-rb4-enable;
    		};
    		hmc7044_c2: channel@2 {
    			reg = <2>;
    			adi,extended-name = "DEV_REFCLK_B";
    			adi,divider = <12>;	// 245760000
    			adi,driver-mode = <2>;	// LVDS
    			adi,coarse-digital-delay = <15>;
    		};
    		hmc7044_c3: channel@3 {
    			reg = <3>;
    			adi,extended-name = "DEV_SYSREF_B";
    			adi,divider = <3840>;	// 768000
    			adi,driver-mode = <1>;	// LVPECL
    			adi,startup-mode-dynamic-enable;
    			adi,high-performance-mode-disable;
    			adi,driver-impedance-mode = <0>;
    			adi,force-mute-enable;
    			adi,control0-rb4-enable;
    		};
    		hmc7044_c4: channel@4 {
    			reg = <4>;
    			adi,extended-name = "JESD_REFCLK_TX_OBS_AB";
    			adi,divider = <12>;	// 245760000
    			adi,driver-mode = <2>;	// LVDS
    		};
    		hmc7044_c5: channel@5 {
    			reg = <5>;
    			adi,extended-name = "JESD_REFCLK_RX_AB";
    			adi,divider = <12>;	// 245760000
    			adi,driver-mode = <2>;	// LVDS
    		};
    //		hmc7044_c6: channel@6 {
    //			reg = <6>;
    //			adi,extended-name = "CORE_CLK_TX_OBS_AB";
    //			adi,divider = <24>;	// 122880000
    //			adi,driver-mode = <0>;	// 
    //		};
    //		hmc7044_c7: channel@7 {
    //			reg = <7>;
    //			adi,extended-name = "CORE_CLK_RX_AB";
    //			adi,divider = <12>;	// 245760000
    //			adi,driver-mode = <0>;	// LVDS
    //		};
    		hmc7044_c8: channel@8 {
    			reg = <8>;
    			adi,extended-name = "FPGA_SYSREF_TX_OBS_AB";
    			adi,divider = <3840>;	// 768000
    			adi,driver-mode = <1>;	// 
    			adi,startup-mode-dynamic-enable;
    			adi,high-performance-mode-disable;
    			adi,force-mute-enable;
    			adi,control0-rb4-enable;
    		};
    		hmc7044_c9: channel@9 {
    			reg = <9>;
    			adi,extended-name = "FPGA_SYSREF_RX_AB";
    			adi,divider = <3840>;	// 768000
    			adi,driver-mode = <1>;	// LVDS
    			adi,startup-mode-dynamic-enable;
    			adi,high-performance-mode-disable;
    			adi,force-mute-enable;
    			adi,control0-rb4-enable;
    		};
    
    	};
    
    };
    
    // SPDX-License-Identifier: GPL-2.0
    /*
     * Analog Devices ADRV9009
     * https://wiki.analog.com/resources/eval/user-guides/adrv9009
     * https://wiki.analog.com/resources/tools-software/linux-drivers/iio-transceiver/adrv9009
     * https://wiki.analog.com/resources/tools-software/linux-software/adrv9009_advanced_plugin
     *
     * hdl_project: <adrv9009/zc706>
     * board_revision: <>
     *
     * Copyright (C) 2019 Analog Devices Inc.
     */
    #include "zynq-zc706.dtsi"
    //#include "zynq-7000.dtsi"
    //#include "zc706.dtsi"
    
    #include "zynq-zc706-adv7511_mod.dtsi"
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/jesd204/adxcvr.h>
    
    //&i2c_mux {
    //	i2c@5 { /* HPC IIC */
    //		#address-cells = <1>;
    //		#size-cells = <0>;
    //		reg = <5>;
    //
    //		eeprom@50 {
    //			compatible = "at24,24c02";
    //			reg = <0x50>;
    //		};
    //
    //		eeprom@54 {
    //			compatible = "at24,24c02";
    //			reg = <0x54>;
    //		};
    //
    //		ad7291@2f {
    //			compatible = "adi,ad7291";
    //			reg = <0x2f>;
    //		};
    //	};
    //};
    
    &fpga_axi {
    	rx_dma: rx-dmac@7c400000 {
    		compatible = "adi,axi-dmac-1.00.a";
    		reg = <0x7c400000 0x10000>;
    		#dma-cells = <1>;
    		interrupt-parent = <&intc>;
    		interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
    		clocks = <&clkc 16>;
    
    		adi,channels {
    			#size-cells = <0>;
    			#address-cells = <1>;
    
    			dma-channel@0 {
    				reg = <0>;
    				adi,source-bus-width = <64>;
    				adi,source-bus-type = <2>;
    				adi,destination-bus-width = <64>;
    				adi,destination-bus-type = <0>;
    			};
    		};
    	};
    
    //	rx_obs_dma: rx-obs-dmac@7c440000  {
    //		compatible = "adi,axi-dmac-1.00.a";
    //		reg = <0x7c440000  0x10000>;
    //		#dma-cells = <1>;
    //		interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
    //		clocks = <&clkc 16>;
    //
    //		adi,channels {
    //			#size-cells = <0>;
    //			#address-cells = <1>;
    //
    //			dma-channel@0 {
    //				reg = <0>;
    //				adi,source-bus-width = <128>;
    //				adi,source-bus-type = <2>;
    //				adi,destination-bus-width = <64>;
    //				adi,destination-bus-type = <0>;
    //			};
    //		};
    //	};
    
    //	tx_dma: tx-dmac@7c420000 {
    //		compatible = "adi,axi-dmac-1.00.a";
    //		reg = <0x7c420000 0x10000>;
    //		#dma-cells = <1>;
    //		//interrupt-parent = <&axi_intc>;
    //		interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
    //		clocks = <&clkc 16>;
    //
    //		adi,channels {
    //			#size-cells = <0>;
    //			#address-cells = <1>;
    //
    //			dma-channel@0 {
    //				reg = <0>;
    //				adi,source-bus-width = <64>;
    //				adi,source-bus-type = <0>;
    //				adi,destination-bus-width = <64>;
    //				adi,destination-bus-type = <1>;
    //			};
    //		};
    //	};
    
    	axi_adrv9009_core_rx: axi-adrv9009-rx-hpc@44a00000 {
    		compatible = "adi,axi-adrv9009-rx-1.0";
    		reg = <0x44a00000 0x8000>;
    		dmas = <&rx_dma 0>;
    		dma-names = "rx";
    		spibus-connected = <&trx0_adrv9009>;
    		adi,axi-decimation-core-available;
    		decimation-gpios = <&gpio0 115 GPIO_ACTIVE_HIGH>;
    	};
    
    //	axi_adrv9009_core_rx_obs: axi-adrv9009-rx-obs-hpc@44a08000 {
    //		compatible = "adi,axi-adrv9009-obs-1.0";
    //		reg = <0x44a08000 0x1000>;
    //		dmas = <&rx_obs_dma 0>;
    //		dma-names = "rx";
    //		clocks = <&trx0_adrv9009 1>;
    //		clock-names = "sampl_clk";
    //	};
    
    	axi_adrv9009_core_tx: axi-adrv9009-tx-hpc@44a14000 {
    		compatible = "adi,axi-adrv9009-tx-1.0";
    		reg = <0x44a14000 0x4000>;
    		//dmas = <&tx_dma 0>;
    		//dma-names = "tx";
    		clocks = <&trx0_adrv9009 2>;
    		clock-names = "sampl_clk";
    		spibus-connected = <&trx0_adrv9009>;
    		adi,axi-pl-fifo-enable;
    		adi,axi-interpolation-core-available;
    		interpolation-gpios = <&gpio0 116 GPIO_ACTIVE_HIGH>;
    	};
    
    	axi_adrv9009_rx_jesd: axi-jesd204-rx@44aa0000 {
    		compatible = "adi,axi-jesd204-rx-1.0";
    		reg = <0x44aa0000 0x1000>;
    		interrupt-parent = <&intc>;
    		interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
    
    		clocks = <&clkc 16>, <&axi_rx_clkgen>, <&axi_adrv9009_adxcvr_rx 0>;
    		//clocks = <&clkc 16>, <&hmc7044 1>, <&axi_adrv9009_adxcvr_rx 0>;
    		clock-names = "s_axi_aclk", "device_clk", "lane_clk";
    
    		#clock-cells = <0>;
    		clock-output-names = "jesd_rx_lane_clk";
    
    		adi,octets-per-frame = <4>;
    		adi,frames-per-multiframe = <32>;
    	};
    
    	axi_adrv9009_tx_jesd: axi-jesd204-tx@44a90000 {
    		compatible = "adi,axi-jesd204-tx-1.0";
    		reg = <0x44a90000 0x1000>;
    		interrupt-parent = <&intc>;
    		interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>;
    
    		clocks = <&clkc 16>, <&axi_tx_clkgen>, <&axi_adrv9009_adxcvr_tx 0>;
    		//clocks = <&clkc 16>, <&hmc7044 1>, <&axi_adrv9009_adxcvr_tx 0>;
    		clock-names = "s_axi_aclk", "device_clk", "lane_clk";
    
    		#clock-cells = <0>;
    		clock-output-names = "jesd_tx_lane_clk";
    
    		adi,octets-per-frame = <2>;
    		adi,frames-per-multiframe = <32>;
    		adi,converter-resolution = <16>;
    		adi,bits-per-sample = <16>;
    		adi,converters-per-device = <4>;
    		adi,control-bits-per-sample = <0>;
    	};
    
    //	axi_adrv9009_rx_os_jesd: axi-jesd204-rx-os@44ab0000 {
    //		compatible = "adi,axi-jesd204-rx-1.0";
    //		reg = <0x44ab0000 0x1000>;
    //
    //		interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
    //
    //		clocks = <&clkc 16>, <&axi_rx_os_clkgen>, <&axi_adrv9009_adxcvr_rx_os 0>;
    //		clock-names = "s_axi_aclk", "device_clk", "lane_clk";
    //
    //		#clock-cells = <0>;
    //		clock-output-names = "jesd_rx_os_lane_clk";
    //
    //		adi,octets-per-frame = <4>;
    //		adi,frames-per-multiframe = <32>;
    //	};
    
    	axi_tx_clkgen: axi-clkgen@43c00000  {
    		compatible = "adi,axi-clkgen-2.00.a";
    		reg = <0x43c00000 0x10000>;
    		#clock-cells = <0>;
    		clocks = <&clkc 15>, <&hmc7044 4>;
    		clock-names = "s_axi_aclk", "clkin1";
    		clock-output-names = "axi_tx_clkgen";
    	};
    
    	axi_rx_clkgen: axi-clkgen@43c10000  {
    		compatible = "adi,axi-clkgen-2.00.a";
    		reg = <0x43c10000 0x10000>;
    		#clock-cells = <0>;
    		clocks = <&clkc 15>, <&hmc7044 4>;
    		clock-names = "s_axi_aclk", "clkin1";
    		clock-output-names = "axi_rx_clkgen";
    	};
    
    //	axi_rx_os_clkgen: axi-clkgen@43c20000  {
    //		compatible = "adi,axi-clkgen-2.00.a";
    //		reg = <0x43c20000 0x10000>;
    //		#clock-cells = <0>;
    //		clocks = <&clkc 15>, <&clk0_ad9528 1>;
    //		clock-names = "s_axi_aclk", "clkin1";
    //		clock-output-names = "axi_rx_os_clkgen";
    //	};
    
    	axi_adrv9009_adxcvr_rx: axi-adxcvr-rx@44a60000 {
    		#address-cells = <1>;
    		#size-cells = <0>;
    		compatible = "adi,axi-adxcvr-1.0";
    		reg = <0x44a60000 0x1000>;
    
    		//clocks = <&hmc7044 1>, <&axi_rx_clkgen 0>;
    		clocks = <&hmc7044 4>;
    		//clock-names = "conv", "div40";
    		clock-names = "conv";
    
    		#clock-cells = <1>;
    		clock-output-names = "rx_gt_clk", "rx_out_clk";
    
    		adi,sys-clk-select = <XCVR_CPLL>;
    		adi,out-clk-select = <XCVR_REFCLK>;
    		adi,use-lpm-enable;
    	};
    
    //	axi_adrv9009_adxcvr_rx_os: axi-adxcvr-rx-os@44a50000 {
    //		#address-cells = <1>;
    //		#size-cells = <0>;
    //		compatible = "adi,axi-adxcvr-1.0";
    //		reg = <0x44a50000 0x1000>;
    //
    //		clocks = <&clk0_ad9528 1>, <&axi_rx_os_clkgen>;
    //		clock-names = "conv", "div40";
    //
    //		#clock-cells = <1>;
    //		clock-output-names = "rx_os_gt_clk", "rx_os_out_clk";
    //
    //		adi,sys-clk-select = <XCVR_CPLL>;
    //		adi,out-clk-select = <XCVR_REFCLK>;
    //		adi,use-lpm-enable;
    //	};
    
    	axi_adrv9009_adxcvr_tx: axi-adxcvr-tx@44a80000 {
    		#address-cells = <1>;
    		#size-cells = <0>;
    		compatible = "adi,axi-adxcvr-1.0";
    		reg = <0x44a80000 0x1000>;
    
    		//clocks = <&hmc7044 1>, <&axi_tx_clkgen>;
    		clocks = <&hmc7044 4>;
    		//clock-names = "conv", "div40";
    		clock-names = "conv";
    
    		#clock-cells = <1>;
    		clock-output-names = "tx_gt_clk", "tx_out_clk";
    
    		adi,sys-clk-select = <XCVR_QPLL>;
    		adi,out-clk-select = <XCVR_REFCLK>;
    	};
    };
    
    &spi0 {
    	status = "okay";
    };
    
    #define fmc_spi spi0
    
    #include "adi-adrv9009_mod.dtsi"
    
    // adrv9009_dac_fifo_bypass_s 60   						// 114
    // ad9528_reset_b,       // 59 //hmc7044_reset_b        // 113 
    // ad9528_sysref_req,    // 58 //hmc7044_sysref_req     // 112
    // adrv9009_tx1_enable,    // 57						// 111
    // adrv9009_tx2_enable,    // 56                        // 110                                
    // adrv9009_rx1_enable,    // 55                        // 109                 
    // adrv9009_rx2_enable,    // 54                        // 108                 
    // adrv9009_test,          // 53                        // 107                 
    // adrv9009_reset_b,       // 52                        // 106                 
    // adrv9009_gpint,         // 51                        // 105                 
    // adrv9009_gpio_00,       // 50                        // 104                 
    // adrv9009_gpio_01,       // 49                        // 103                 
    // adrv9009_gpio_02,       // 48                        // 102                 
    // adrv9009_gpio_03,       // 47                        // 101                 
    // adrv9009_gpio_04,       // 46                        // 100                 
    // adrv9009_gpio_05,       // 45                        // 99                 
    // adrv9009_gpio_06,       // 44                                         
    // adrv9009_gpio_07,       // 43                                         
    // adrv9009_gpio_15,       // 42                                         
    // adrv9009_gpio_08,       // 41                                         
    // adrv9009_gpio_09,       // 40                                         
    // adrv9009_gpio_10,       // 39                                         
    // adrv9009_gpio_11,       // 38                                         
    // adrv9009_gpio_12,       // 37                                         
    // adrv9009_gpio_14,       // 36                                         
    // adrv9009_gpio_13,       // 35                                         
    // adrv9009_gpio_17,       // 34                                         
    // adrv9009_gpio_16,       // 33                                         
    // adrv9009_gpio_18}));    // 32 + 54
    
    //&trx0_adrv9009 {
    //	reset-gpios = <&gpio0 106 0>;
    //	test-gpios = <&gpio0 107 0>;
    //	sysref-req-gpios = <&gpio0 112 0>;
    //	rx2-enable-gpios = <&gpio0 108 0>;
    //	rx1-enable-gpios = <&gpio0 109 0>;
    //	tx2-enable-gpios = <&gpio0 110 0>;
    //	tx1-enable-gpios = <&gpio0 111 0>;
    //};
    
    //&hmc7044 {
    //	reset-gpios = <&gpio0 113 0>;
    //};
    
    &amba_pl{
    	samplemodule_instance: samplemodule {
    		compatible = "etelm,samplemodule";
    		reg = <0x40000000 0x20000>;
    		etelm,reg_gpio0 = <0x41200000 0x1000>;
    		etelm,mem_tx   = <0x40000000 0x20000>;
    		interrupt-parent = <&intc>;
    		interrupts = < 0 56 1 >;
    	};
    };

    /dts-v1/;
    #include "system-user.dtsi"
    
    &axi_adrv9009_core_tx {
    	plddrbypass-gpios = <&gpio0 114 0>;
    };
    
    #include <dt-bindings/iio/adc/adi,adrv9009.h>
    
    &trx0_adrv9009 {
    
    	reset-gpios = <&gpio0 106 0>;
    	test-gpios = <&gpio0 107 0>;
    	sysref-req-gpios = <&gpio0 112 0>;
    	rx2-enable-gpios = <&gpio0 108 0>;
    	rx1-enable-gpios = <&gpio0 109 0>;
    	tx2-enable-gpios = <&gpio0 110 0>;
    	tx1-enable-gpios = <&gpio0 111 0>;
    	
    	jesd204-device;
    	#jesd204-cells = <2>;
    	jesd204-top-device = <0>; /* This is the TOP device */
    	jesd204-link-ids = <DEFRAMER_LINK_TX FRAMER_LINK_RX>;
    	
    	jesd204-ignore-errors;
    
    	jesd204-inputs =
    		<&axi_adrv9009_rx_jesd 0 FRAMER_LINK_RX>,
    		//<&axi_adrv9009_rx_os_jesd 0 FRAMER_LINK_ORX>,
    		<&axi_adrv9009_tx_jesd 0 DEFRAMER_LINK_TX>;
    
    	/delete-property/ interrupts;
    };
    
    &axi_adrv9009_rx_jesd {
    	jesd204-device;
    	#jesd204-cells = <2>;
    	jesd204-inputs = <&axi_adrv9009_adxcvr_rx 0 FRAMER_LINK_RX>;
    };
    
    
    &axi_adrv9009_tx_jesd {
    	jesd204-device;
    	#jesd204-cells = <2>;
    	jesd204-inputs = <&axi_adrv9009_adxcvr_tx 0 DEFRAMER_LINK_TX>;
    };
    
    &axi_adrv9009_adxcvr_rx {
        jesd204-device;
    	#jesd204-cells = <2>;
    	jesd204-inputs =  <&hmc7044 0 FRAMER_LINK_RX>;
    	//clocks = <&hmc7044 1>; /* div40 is controlled by axi_adrv9009_rx_jesd */
    	//clock-names = "conv";
    };
    
    &axi_adrv9009_adxcvr_tx {
        jesd204-device;
    	#jesd204-cells = <2>;
    	jesd204-inputs =  <&hmc7044 0 DEFRAMER_LINK_TX>;
    	//clocks = <&hmc7044 1>; /* div40 is controlled by axi_adrv9009_tx_jesd */
    	//clock-names = "conv";
    };
    
    &hmc7044 {
    	reset-gpios = <&gpio0 113 0>;
    	jesd204-device;
    	#jesd204-cells = <2>;
    	jesd204-sysref-provider;
    
    	//adi,sysref-pattern-mode = <SYSREF_PATTERN_NSHOT>;
    	///delete-property/ adi,sysref-request-enable;
    };
     
    
    
    

    Regards,

    Salah

Reply
  • Update,

    After fixing clkgen in device tree, clock error disapeared. JESD link is now enabled but stuck in CGS.

    Still having SPI errors :

    adrv9009 spi1.0: ADIHAL_resetHw
    adrv9009 spi1.0: ERROR: 346: TALISE_verifySpiReadWrite(): Cannot read from a low SPI address
    adrv9009 spi1.0: adrv9009_jesd204_link_setup:5805 (ret 10)

    Full boot log and device tree 

    
    Starting kernel ...
    
    Booting Linux on physical CPU 0x0
    Linux version 5.10.0-xilinx-v2021.1 (oe-user@oe-host) (arm-xilinx-linux-gnueabi-gcc (GCC) 10.2.0, GNU ld (GNU Binutils) 2.35.1) #1 SMP PREEMPT Thu Nov 18 14:55:54 UTC 2021
    CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
    CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
    OF: fdt: Machine model: Xilinx ZC706 board
    printk: bootconsole [earlycon0] enabled
    Memory policy: Data cache writealloc
    INITRD: 0x00800000+0x01000000 overlaps in-use memory region - disabling initrd
    cma: Reserved 128 MiB at 0x38000000
    Zone ranges:
      Normal   [mem 0x0000000000000000-0x000000002fffffff]
      HighMem  [mem 0x0000000030000000-0x000000003fffffff]
    Movable zone start for each node
    Early memory node ranges
      node   0: [mem 0x0000000000000000-0x000000003fffffff]
    Initmem setup node 0 [mem 0x0000000000000000-0x000000003fffffff]
    percpu: Embedded 15 pages/cpu s30028 r8192 d23220 u61440
    Built 1 zonelists, mobility grouping on.  Total pages: 260416
    Kernel command line: console=ttyPS0,115200n8 root=/dev/ram rw initrd=0x00800000,16M earlyprintk mtdparts=physmap-flash.0:512K(nor-fsbl),512K(nor-u-boot),5M(nor-linux),9M(nor-user),1M(nor-scratch),-(nor-rootfs)
    Dentry cache hash table entries: 131072 (order: 7, 524288 bytes, linear)
    Inode-cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
    mem auto-init: stack:off, heap alloc:off, heap free:off
    Memory: 825596K/1048576K available (10240K kernel code, 852K rwdata, 7196K rodata, 44032K init, 168K bss, 91908K reserved, 131072K cma-reserved, 131072K highmem)
    rcu: Preemptible hierarchical RCU implementation.
    rcu:    RCU event tracing is enabled.
    rcu:    RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
            Trampoline variant of Tasks RCU enabled.
    rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
    rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
    NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
    efuse mapped to (ptrval)
    slcr mapped to (ptrval)
    L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
    L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
    L2C-310 erratum 769419 enabled
    L2C-310 enabling early BRESP for Cortex-A9
    L2C-310 full line of zeros enabled for Cortex-A9
    L2C-310 ID prefetch enabled, offset 1 lines
    L2C-310 dynamic clock gating enabled, standby mode enabled
    L2C-310 cache controller enabled, 8 ways, 512 kB
    L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
    random: get_random_bytes called from start_kernel+0x33c/0x4e8 with crng_init=0
    zynq_clock_init: clkc starts at (ptrval)
    Zynq clock init
    ps_clk frequency not specified, using 33 MHz.
    sched_clock: 64 bits at 399MHz, resolution 2ns, wraps every 4398046511103ns
    clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x5c4093a7d1, max_idle_ns: 440795210635 ns
    Switching to timer-based delay loop, resolution 2ns
    clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 447945978 ns
    timer #0 at (ptrval), irq=25
    Console: colour dummy device 80x30
    Calibrating delay loop (skipped), value calculated using timer frequency.. 799.99 BogoMIPS (lpj=3999999)
    pid_max: default: 32768 minimum: 301
    Mount-cache hash table entries: 2048 (order: 1, 8192 bytes, linear)
    Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes, linear)
    CPU: Testing write buffer coherency: ok
    CPU0: Spectre v2: using BPIALL workaround
    CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
    Setting up static identity map for 0x100000 - 0x100060
    rcu: Hierarchical SRCU implementation.
    smp: Bringing up secondary CPUs ...
    CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
    CPU1: Spectre v2: using BPIALL workaround
    smp: Brought up 1 node, 2 CPUs
    SMP: Total of 2 processors activated (1599.99 BogoMIPS).
    CPU: All CPU(s) started in SVC mode.
    devtmpfs: initialized
    VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
    clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
    futex hash table entries: 512 (order: 3, 32768 bytes, linear)
    pinctrl core: initialized pinctrl subsystem
    NET: Registered protocol family 16
    DMA: preallocated 256 KiB pool for atomic coherent allocations
    thermal_sys: Registered thermal governor 'step_wise'
    cpuidle: using governor ladder
    hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
    hw-breakpoint: maximum watchpoint size is 4 bytes.
    zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0x(ptrval)
    SCSI subsystem initialized
    usbcore: registered new interface driver usbfs
    usbcore: registered new interface driver hub
    usbcore: registered new device driver usb
    mc: Linux media interface: v0.10
    videodev: Linux video capture interface: v2.00
    jesd204: created con: id=0, topo=0, link=0, /axi/spi@e0006000/hmc7044@2 <-> /fpga-axi@0/axi-adxcvr-tx@44a80000
    jesd204: created con: id=1, topo=0, link=1, /axi/spi@e0006000/hmc7044@2 <-> /fpga-axi@0/axi-adxcvr-rx@44a60000
    jesd204: created con: id=2, topo=0, link=0, /fpga-axi@0/axi-adxcvr-tx@44a80000 <-> /fpga-axi@0/axi-jesd204-tx@44a90000
    jesd204: created con: id=3, topo=0, link=1, /fpga-axi@0/axi-adxcvr-rx@44a60000 <-> /fpga-axi@0/axi-jesd204-rx@44aa0000
    jesd204: created con: id=4, topo=0, link=1, /fpga-axi@0/axi-jesd204-rx@44aa0000 <-> /axi/spi@e0006000/adrv9009-phy@0
    jesd204: created con: id=5, topo=0, link=0, /fpga-axi@0/axi-jesd204-tx@44a90000 <-> /axi/spi@e0006000/adrv9009-phy@0
    jesd204: /axi/spi@e0006000/adrv9009-phy@0: JESD204[0] transition uninitialized -> initialized
    jesd204: /axi/spi@e0006000/adrv9009-phy@0: JESD204[1] transition uninitialized -> initialized
    jesd204: found 6 devices and 1 topologies
    FPGA manager framework
    Advanced Linux Sound Architecture Driver Initialized.
    clocksource: Switched to clocksource arm_global_timer
    NET: Registered protocol family 2
    tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes, linear)
    TCP established hash table entries: 8192 (order: 3, 32768 bytes, linear)
    TCP bind hash table entries: 8192 (order: 4, 65536 bytes, linear)
    TCP: Hash tables configured (established 8192 bind 8192)
    UDP hash table entries: 512 (order: 2, 16384 bytes, linear)
    UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear)
    NET: Registered protocol family 1
    hw perfevents: no interrupt-affinity property for /pmu@f8891000, guessing.
    hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
    workingset: timestamp_bits=14 max_order=18 bucket_order=4
    bounce: pool size: 64 pages
    io scheduler mq-deadline registered
    io scheduler kyber registered
    zynq-pinctrl 700.pinctrl: zynq pinctrl initialized
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-241330
    dma-pl330 f8003000.dmac:        DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
    brd: module loaded
    loop: module loaded
    Registered mathworks_ip class
    spi-nor spi0.0: unrecognized JEDEC id bytes: 00 00 00 00 00 00
    MACsec IEEE 802.1AE
    libphy: Fixed MDIO Bus: probed
    tun: Universal TUN/TAP device driver, 1.6
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    libphy: MACB_mii_bus: probed
    macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 38 (1a:78:ea:d8:70:54)
    usbcore: registered new interface driver asix
    usbcore: registered new interface driver ax88179_178a
    usbcore: registered new interface driver cdc_ether
    usbcore: registered new interface driver net1080
    usbcore: registered new interface driver cdc_subset
    usbcore: registered new interface driver zaurus
    usbcore: registered new interface driver cdc_ncm
    ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
    usbcore: registered new interface driver uas
    usbcore: registered new interface driver usb-storage
    usbcore: registered new interface driver usbserial_generic
    usbserial: USB Serial support registered for generic
    usbcore: registered new interface driver ftdi_sio
    usbserial: USB Serial support registered for FTDI USB Serial Device
    usbcore: registered new interface driver upd78f0730
    usbserial: USB Serial support registered for upd78f0730
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    udc-core: couldn't find an available UDC - added [g_mass_storage] to list of pending drivers
    i2c /dev entries driver
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    cdns-i2c e0004000.i2c: 400 kHz mmio e0004000 irq 32
    pca954x 0-0074: probe failed
    usbcore: registered new interface driver uvcvideo
    USB Video Class driver (1.1.1)
    gspca_main: v2.14.0 registered
    cdns-wdt f8005000.watchdog: Xilinx Watchdog Timer with timeout 10s
    Xilinx Zynq CpuIdle Driver started
    sdhci: Secure Digital Host Controller Interface driver
    sdhci: Copyright(c) Pierre Ossman
    sdhci-pltfm: SDHCI platform and OF driver helper
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    ledtrig-cpu: registered to indicate activity on CPUs
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    hid: raw HID events driver (C) Jiri Kosina
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    usbcore: registered new interface driver usbhid
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    usbhid: USB HID core driver
    adrv9009 spi1.0: adrv9009_probe : enter
    mmc0: SDHCI controller on e0100000.mmc [e0100000.mmc] using ADMA
    hmc7044 spi1.2: PLL1: Holdover, CLKIN0 @ 40000000 Hz, PFD: 320 kHz - PLL2: Locked @ 2949.120000 MHz
    jesd204: /axi/spi@e0006000/hmc7044@2,jesd204:1,parent=spi1.2: Using as SYSREF provider
    axi_adxcvr 44a60000.axi-adxcvr-rx: AXI-ADXCVR-RX (16.01.a) using CPLL on GTX2 at 0x44A60000. Number of lanes: 2.
    axi_adxcvr 44a80000.axi-adxcvr-tx: AXI-ADXCVR-TX (16.01.a) using QPLL on GTX2 at 0x44A80000. Number of lanes: 2.
    fpga_manager fpga0: Xilinx Zynq FPGA Manager registered
    usbcore: registered new interface driver snd-usb-audio
    NET: Registered protocol family 10
    Segment Routing with IPv6
    sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
    NET: Registered protocol family 17
    NET: Registered protocol family 36
    Registering SWP/SWPB emulation handler
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 35, base_baud = 3125000) is a xuartps
    printk: console [ttyPS0] enabled
    printk: console [ttyPS0] enabled
    printk: bootconsole [earlycon0] disabled
    printk: bootconsole [earlycon0] disabled
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    adrv9009 spi1.0: adrv9009_probe : enter
    cf_axi_dds 44a14000.axi-adrv9009-tx-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.00.b) at 0x44A14000 mapped to 0x(ptrval), probed DDS AD9371
    axi-jesd204-rx 44aa0000.axi-jesd204-rx: AXI-JESD204-RX (1.02.a) at 0x44AA0000. Encoder 8b10b, width 4/0, lanes 2, jesd204-fsm.
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition initialized -> probed
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition initialized -> probed
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition probed -> idle
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition probed -> idle
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition idle -> device_init
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition idle -> device_init
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition device_init -> link_init
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition device_init -> link_init
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_init -> link_supported
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_init -> link_supported
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_supported -> link_pre_setup
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_supported -> link_pre_setup
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_pre_setup -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_pre_setup -> clk_sync_stage1
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition clk_sync_stage1 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition clk_sync_stage1 -> clk_sync_stage2
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition clk_sync_stage2 -> clk_sync_stage3
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition clk_sync_stage2 -> clk_sync_stage3
    adrv9009 spi1.0: ADIHAL_resetHw
    adrv9009 spi1.0: ERROR: 346: TALISE_verifySpiReadWrite(): Cannot read from a low SPI address
    adrv9009 spi1.0: adrv9009_jesd204_link_setup:5805 (ret 10)
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] In link_setup got error from cb: -14 (ignoring!)
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition clk_sync_stage3 -> link_setup
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition clk_sync_stage3 -> link_setup
    adrv9009 spi1.0: adrv9009_jesd204_setup_stage1:5861 Unexpected MCS sync status (0x0)
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] In opt_setup_stage1 got error from cb: -14 (ignoring!)
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_setup -> opt_setup_stage1
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_setup -> opt_setup_stage1
    adrv9009 spi1.0: adrv9009_jesd204_setup_stage2:5891 Unexpected MCS sync status (0x0)
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] In opt_setup_stage2 got error from cb: -14 (ignoring!)
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage1 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage1 -> opt_setup_stage2
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage2 -> opt_setup_stage3
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage2 -> opt_setup_stage3
    random: fast init done
    adrv9009 spi1.0: ERROR: 179: ARM Mailbox Busy. Command not executed in TALISE_sendArmCommand()
    adrv9009 spi1.0: adrv9009_jesd204_setup_stage4:6040 (ret 5)
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] In opt_setup_stage4 got error from cb: -14 (ignoring!)
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage3 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage3 -> opt_setup_stage4
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage4 -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage4 -> opt_setup_stage5
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage5 -> clocks_enable
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage5 -> clocks_enable
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition clocks_enable -> link_enable
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition clocks_enable -> link_enable
    axi-jesd204-rx 44aa0000.axi-jesd204-rx: axi_jesd204_rx_jesd204_link_running: Link1 status failed (CGS)
    jesd204: /fpga-axi@0/axi-jesd204-rx@44aa0000,jesd204:2,parent=44aa0000.axi-jesd204-rx: JESD204[1] In link_running got error from cb: -1 (ignoring!)
    axi-jesd204-tx 44a90000.axi-jesd204-tx: axi_jesd204_tx_jesd204_link_running: Link0 status failed (CGS)
    jesd204: /fpga-axi@0/axi-jesd204-tx@44a90000,jesd204:3,parent=44a90000.axi-jesd204-tx: JESD204[0] In link_running got error from cb: -1 (ignoring!)
    adrv9009 spi1.0: Link0 TAL_DEFRAMER_A deframerStatus 0x8
    adrv9009 spi1.0: Link1 TAL_FRAMER_A framerStatus 0x0
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_enable -> link_running
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_enable -> link_running
    adrv9009 spi1.0: ERROR: 180: Device not in radioOff/IDLE state. Error in TALISE_enableTrackingCals()
    adrv9009 spi1.0: adrv9009_jesd204_post_running_stage:6141 (ret 5)
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] In opt_post_running_stage got error from cb: -14 (ignoring!)
    adrv9009 spi1.0: ERROR: 32: TALISE_gpIntHandler(): AUXCLK PLL is not locked
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_running -> opt_post_running_stage
    adrv9009 spi1.0: AUX PLL lock detect reset
    adrv9009 spi1.0: ARM Command Wait TimeOut
    jesd204: /axi/spi@e0006000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_running -> opt_post_running_stage
    adrv9009 spi1.0: (null)
    adrv9009 spi1.0: (null)
    axi-jesd204-tx 44a90000.axi-jesd204-tx: AXI-JESD204-TX (1.01.a) at 0x44A90000. Encoder 8b10b, width 4/0, lanes 2, jesd204-fsm.
    adrv9009 spi1.0: GP Interrupt Status 0x5 Action: ERR_RESET_FULL
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    cf_axi_adc 44a00000.axi-adrv9009-rx-hpc: ADI AIM (10.00.b) at 0x44A00000 mapped to 0x(ptrval), probed ADC ADRV9009 as MASTER
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    zynq-pinctrl 700.pinctrl: unsupported configuration parameter '18'
    ALSA device list:
      No soundcards found.
    Warning: unable to open an initial console.
    Freeing unused kernel memory: 44032K
    Run /init as init process
    udevd[77]: starting version 3.2.9
    random: udevd: uninitialized urandom read (16 bytes read)
    random: udevd: uninitialized urandom read (16 bytes read)
    random: udevd: uninitialized urandom read (16 bytes read)
    udevd[78]: starting eudev-3.2.9
    urandom_read: 2 callbacks suppressed
    random: dd: uninitialized urandom read (512 bytes read)
    samplemodule: loading out-of-tree module taints kernel.
    <1>Hello module world : DRIVER !!
    <1>Module parameters were (0xdeadbeef) and "default"
    <1>Config_of ok.
    Sorry, registering the character device  failed with
    macb e000b000.ethernet eth0: PHY [e000b000.ethernet-ffffffff:00] driver [Marvell 88E1510] (irq=POLL)
    macb e000b000.ethernet eth0: configuring for phy/rgmii-id link mode
    random: dbus-uuidgen: uninitialized urandom read (12 bytes read)
    random: dbus-uuidgen: uninitialized urandom read (8 bytes read)
    random: dbus-daemon: uninitialized urandom read (12 bytes read)
    random: crng init done
    random: 1 urandom warning(s) missed due to ratelimiting
    
    root@ETRX_petalinux:~#

    #include <dt-bindings/iio/frequency/ad9528.h>
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    
    / {
    	clocks {
    		adrv9009_clkin: clock@0 {
    			compatible = "fixed-clock";
    
    			clock-frequency = <12288000>;
    			clock-output-names = "adrv9009_ext_refclk";
    			#clock-cells = <0>;
    		};
    	};
    };
    
    &fmc_spi {
    
    //	clk0_ad9528: ad9528-1@0 {
    //		compatible = "adi,ad9528";
    //		reg = <0>;
    //
    //		#address-cells = <1>;
    //		#size-cells = <0>;
    //
    //		spi-max-frequency = <10000000>;
    //		//adi,spi-3wire-enable;
    //
    //		clock-output-names = "ad9528-1_out0", "ad9528-1_out1", "ad9528-1_out2",
    //			"ad9528-1_out3", "ad9528-1_out4", "ad9528-1_out5", "ad9528-1_out6",
    //			"ad9528-1_out7", "ad9528-1_out8", "ad9528-1_out9", "ad9528-1_out10",
    //			"ad9528-1_out11", "ad9528-1_out12", "ad9528-1_out13";
    //		#clock-cells = <1>;
    //
    //		adi,vcxo-freq = <122880000>;
    //
    //		adi,refa-enable;
    //		adi,refa-diff-rcv-enable;
    //		adi,refa-r-div = <1>;
    //		adi,osc-in-cmos-neg-inp-enable;
    //
    //		/* PLL1 config */
    //		adi,pll1-feedback-div = <4>;
    //		adi,pll1-charge-pump-current-nA = <5000>;
    //
    //		/* PLL2 config */
    //		adi,pll2-vco-div-m1 = <3>; /* use 5 for 184320000 output device clock */
    //		adi,pll2-n2-div = <10>; /* N / M1 */
    //		adi,pll2-r1-div = <1>;
    //		adi,pll2-charge-pump-current-nA = <805000>;
    //
    //		/* SYSREF config */
    //		adi,sysref-src = <SYSREF_SRC_INTERNAL>;
    //		adi,sysref-pattern-mode = <SYSREF_PATTERN_CONTINUOUS>;
    //		adi,sysref-k-div = <512>;
    //		adi,sysref-request-enable;
    //		adi,sysref-nshot-mode = <SYSREF_NSHOT_4_PULSES>;
    //		adi,sysref-request-trigger-mode = <SYSREF_LEVEL_HIGH>;
    //
    //		adi,rpole2 = <RPOLE2_900_OHM>;
    //		adi,rzero = <RZERO_1850_OHM>;
    //		adi,cpole1 = <CPOLE1_16_PF>;
    //
    //		adi,status-mon-pin0-function-select = <1>; /* PLL1 & PLL2 Locked */
    //		adi,status-mon-pin1-function-select = <7>; /* REFA Correct */
    //
    //		ad9528_0_c13: channel@13 {
    //			reg = <13>;
    //			adi,extended-name = "DEV_CLK";
    //			adi,driver-mode = <DRIVER_MODE_LVDS>;
    //			adi,divider-phase = <0>;
    //			adi,channel-divider = <10>;
    //			adi,signal-source = <SOURCE_VCO>;
    //		};
    //
    //		ad9528_0_c1: channel@1 {
    //			reg = <1>;
    //			adi,extended-name = "FMC_CLK";
    //			adi,driver-mode = <DRIVER_MODE_LVDS>;
    //			adi,divider-phase = <0>;
    //			adi,channel-divider = <10>;
    //			adi,signal-source = <SOURCE_VCO>;
    //		};
    //
    //		ad9528_0_c12: channel@12 {
    //			reg = <12>;
    //			adi,extended-name = "DEV_SYSREF";
    //			adi,driver-mode = <DRIVER_MODE_LVDS>;
    //			adi,divider-phase = <0>;
    //			adi,channel-divider = <10>;
    //			adi,signal-source = <SOURCE_SYSREF_VCO>;
    //		};
    //
    //		ad9528_0_c3: channel@3 {
    //			reg = <3>;
    //			adi,extended-name = "FMC_SYSREF";
    //			adi,driver-mode = <DRIVER_MODE_LVDS>;
    //			adi,divider-phase = <0>;
    //			adi,channel-divider = <10>;
    //			adi,signal-source = <SOURCE_SYSREF_VCO>;
    //		};
    //	};
    
    	is-decoded-cs = <1>;
    
    	trx0_adrv9009: adrv9009-phy@0 {
    		compatible = "adrv9009";
    		reg = <0>; //ADRV A SPI CS 0
    
    		#address-cells = <1>;
    		#size-cells = <0>;
    
    		/* SPI Setup */
    		spi-max-frequency = <25000000>;
    
    		interrupt-parent = <&gpio0>;
    		interrupts = <105 IRQ_TYPE_EDGE_RISING>;
    
    		/* Clocks */
    		clocks = <&axi_adrv9009_rx_jesd>, <&axi_adrv9009_tx_jesd>,
    			<&hmc7044 0>, <&hmc7044 5>, <&hmc7044 1>, <&hmc7044 8>,
    			<&hmc7044 4>;
    
    		clock-names = "jesd_rx_clk", "jesd_tx_clk",
    			"dev_clk", "fmc_clk", "sysref_dev_clk",
    			"sysref_fmc_clk", "fmc2_clk";
    
    
    		clock-output-names = "rx_sampl_clk", "rx_os_sampl_clk", "tx_sampl_clk";
    		#clock-cells = <1>;
    
    		/* JESD204 */
    
    		/* JESD204 RX */
    		adi,jesd204-framer-a-bank-id = <1>;
    		adi,jesd204-framer-a-device-id = <0>;
    		adi,jesd204-framer-a-lane0-id = <0>;
    		adi,jesd204-framer-a-m = <4>;
    		adi,jesd204-framer-a-k = <32>;
    		adi,jesd204-framer-a-f = <4>;
    		adi,jesd204-framer-a-np = <16>;
    		adi,jesd204-framer-a-scramble = <1>;
    		adi,jesd204-framer-a-external-sysref = <1>;
    		adi,jesd204-framer-a-serializer-lanes-enabled = <0x03>;
    		adi,jesd204-framer-a-serializer-lane-crossbar = <0xE4>;
    		adi,jesd204-framer-a-lmfc-offset = <31>;
    		adi,jesd204-framer-a-new-sysref-on-relink = <0>;
    		adi,jesd204-framer-a-syncb-in-select = <0>;
    		adi,jesd204-framer-a-over-sample = <0>;
    		adi,jesd204-framer-a-syncb-in-lvds-mode = <1>;
    		adi,jesd204-framer-a-syncb-in-lvds-pn-invert = <0>;
    		adi,jesd204-framer-a-enable-manual-lane-xbar = <0>;
    
    		/* JESD204 OBS */
    		adi,jesd204-framer-b-bank-id = <0>;
    		adi,jesd204-framer-b-device-id = <0>;
    		adi,jesd204-framer-b-lane0-id = <0>;
    		adi,jesd204-framer-b-m = <0>;
    		adi,jesd204-framer-b-k = <32>;
    		adi,jesd204-framer-b-f = <2>;
    		adi,jesd204-framer-b-np = <16>;
    		adi,jesd204-framer-b-scramble = <1>;
    		adi,jesd204-framer-b-external-sysref = <1>;
    		adi,jesd204-framer-b-serializer-lanes-enabled = <0x00>;
    		adi,jesd204-framer-b-serializer-lane-crossbar = <0xE4>;
    		adi,jesd204-framer-b-lmfc-offset = <31>;
    		adi,jesd204-framer-b-new-sysref-on-relink = <0>;
    		adi,jesd204-framer-b-syncb-in-select = <1>;
    		adi,jesd204-framer-b-over-sample = <0>;
    		adi,jesd204-framer-b-syncb-in-lvds-mode = <1>;
    		adi,jesd204-framer-b-syncb-in-lvds-pn-invert = <0>;
    		adi,jesd204-framer-b-enable-manual-lane-xbar = <0>;
    
    		/* JESD204 TX */
    		adi,jesd204-deframer-a-bank-id = <0>;
    		adi,jesd204-deframer-a-device-id = <0>;
    		adi,jesd204-deframer-a-lane0-id = <0>;
    		adi,jesd204-deframer-a-m = <4>;
    		adi,jesd204-deframer-a-k = <16>;
    		adi,jesd204-deframer-a-scramble = <1>;
    		adi,jesd204-deframer-a-external-sysref = <1>;
    		adi,jesd204-deframer-a-deserializer-lanes-enabled = <0x03>;
    		adi,jesd204-deframer-a-deserializer-lane-crossbar = <0xE4>;
    		adi,jesd204-deframer-a-lmfc-offset = <7>;
    		adi,jesd204-deframer-a-new-sysref-on-relink = <0>;
    		adi,jesd204-deframer-a-syncb-out-select = <0>;
    		adi,jesd204-deframer-a-np = <16>;
    		adi,jesd204-deframer-a-syncb-out-lvds-mode = <1>;
    		adi,jesd204-deframer-a-syncb-out-lvds-pn-invert = <0>;
    		adi,jesd204-deframer-a-syncb-out-cmos-slew-rate = <0>;
    		adi,jesd204-deframer-a-syncb-out-cmos-drive-level = <0>;
    		adi,jesd204-deframer-a-enable-manual-lane-xbar = <0>;
    
    		adi,jesd204-ser-amplitude = <15>;
    		adi,jesd204-ser-pre-emphasis = <1>;
    		adi,jesd204-ser-invert-lane-polarity = <0x3>;
    		adi,jesd204-des-invert-lane-polarity = <0x3>;
    		adi,jesd204-des-eq-setting = <1>;
    		adi,jesd204-sysref-lvds-mode = <1>;
    		adi,jesd204-sysref-lvds-pn-invert = <0>;
    
    		/* RX */
    
    		adi,rx-profile-rx-fir-gain_db = <(-6)>;
    		adi,rx-profile-rx-fir-num-fir-coefs = <48>;
    		//adi,rx-profile-rx-fir-coefs = /bits/ 16 <(-8) (-22) (32) (50) (-68) (-106) (141) (199) (-258) (-352) (430) (572) (-691) (-903) (1069) (1392) (-1644) (-2172) (2569) (3574) (-4364) (-7129) (9355) (31095) (31095) (9355) (-7129) (-4364) (3574) (2569) (-2172) (-1644) (1392) (1069) (-903) (-691) (572) (430) (-352) (-258) (199) (141) (-106) (-68) (50) (32) (-22) (-8)>;
     		//adi,rx-profile-rx-fir-coefs = /bits/ 16 < (3) ( 6) ( 9) ( 8) ( 0) ( -19) ( -44) ( -64) ( -60) ( -17) ( 68) ( 175) ( 258) ( 256) ( 122) ( -146) ( -484) ( -758) ( -804) ( -495) ( 178) ( 1058) ( 1828) ( 2098) ( 1547) ( 97) ( -1975) (  -4030) ( -5196) ( -4624) ( -1784) ( 3286) ( 9894) ( 16805) ( 22544) ( 25799) ( 25799) ( 22544) ( 16805) ( 9894) ( 3286) ( -1784) ( -4624) ( -5196) ( -4030) ( -1975) ( 97) ( 1547) ( 2098) ( 1828) ( 1058) ( 178) ( -495) ( -804) ( -758) ( -484) ( -146) ( 122) ( 256) ( 258) ( 175) ( 68) ( -17) ( -60) ( -64) ( -44) ( -19) ( 0) ( 8) ( 9) ( 6) ( 3) >;
    		adi,rx-profile-rx-fir-coefs = /bits/ 16 <(-9) (-18) (31) (42) (-65) (-89) (132) (168) (-240) (-298) (396) (486) (-632) (-770) (968) (1163) (-1530) (-1862) (2369) (3051) (-4066) (-5983) (9689) (29830) (29830) (9689) (-5983) (-4066) (3051) (2369) (-1862) (-1530) (1163) (968) (-770) (-632) (486) (396) (-298) (-240) (168) (132) (-89) (-65) (42) (31) (-18) (-9)>;
    		
    		adi,rx-profile-rx-fir-decimation = <2>;
    		adi,rx-profile-rx-dec5-decimation = <4>;
    		adi,rx-profile-rhb1-decimation = <2>;
    		adi,rx-profile-rx-output-rate_khz = <122880>;
    		adi,rx-profile-rf-bandwidth_hz = <100000000>;
    		adi,rx-profile-rx-bbf3d-bcorner_khz = <100000>;
    		adi,rx-profile-rx-adc-profile = /bits/ 16 <265 146 181 90 1280 366 1257 27 1258 17 718 39 48 46 27 161 0 0 0 0 40 0 7 6 42 0 7 6 42 0 25 27 0 0 25 27 0 0 165 44 31 905>;
    		adi,rx-profile-rx-ddc-mode = <0>;
    
    		adi,rx-nco-shifter-band-a-input-band-width_khz = <0>;
    		adi,rx-nco-shifter-band-a-input-center-freq_khz = <0>;
    		adi,rx-nco-shifter-band-a-nco1-freq_khz = <0>;
    		adi,rx-nco-shifter-band-a-nco2-freq_khz = <0>;
    		adi,rx-nco-shifter-band-binput-band-width_khz = <0>;
    		adi,rx-nco-shifter-band-binput-center-freq_khz = <0>;
    		adi,rx-nco-shifter-band-bnco1-freq_khz = <0>;
    		adi,rx-nco-shifter-band-bnco2-freq_khz = <0>;
    
    		adi,rx-gain-control-gain-mode = <0>;
    		adi,rx-gain-control-rx1-gain-index = <255>;
    		adi,rx-gain-control-rx2-gain-index = <255>;
    		adi,rx-gain-control-rx1-max-gain-index = <255>;
    		adi,rx-gain-control-rx1-min-gain-index = <195>;
    		adi,rx-gain-control-rx2-max-gain-index = <255>;
    		adi,rx-gain-control-rx2-min-gain-index = <195>;
    
    		adi,rx-settings-framer-sel = <0>;
    		adi,rx-settings-rx-channels = <3>;
    
    		/* ORX */
    
    		adi,orx-profile-rx-fir-gain_db = <(-6)>;
    		adi,orx-profile-rx-fir-num-fir-coefs = <48>;
    		adi,orx-profile-rx-fir-coefs = /bits/ 16  <(-9) (-18) (31) (42) (-65) (-89) (132) (168) (-240) (-298) (396) (486) (-632) (-770) (968) (1163) (-1530) (-1862) (2369) (3051) (-4066) (-5983) (9689) (29830) (29830) (9689) (-5983) (-4066) (3051) (2369) (-1862) (-1530) (1163) (968) (-770) (-632) (486) (396) (-298) (-240) (168) (132) (-89) (-65) (42) (31) (-18) (-9)>;
    		adi,orx-profile-rx-fir-decimation = <2>;
    		adi,orx-profile-rx-dec5-decimation = <4>;
    		adi,orx-profile-rhb1-decimation = <2>;
    		adi,orx-profile-orx-output-rate_khz = <122880>;
    		adi,orx-profile-rf-bandwidth_hz = <100000000>;
    		adi,orx-profile-rx-bbf3d-bcorner_khz = <225000>;
    		adi,orx-profile-orx-low-pass-adc-profile = /bits/ 16  <265 146 181 90 1280 366 1257 27 1258 17 718 39 48 46 27 161 0 0 0 0 40 0 7 6 42 0 7 6 42 0 25 27 0 0 25 27 0 0 165 44 31 905>;
    		adi,orx-profile-orx-band-pass-adc-profile = /bits/ 16  <265 146 181 90 1280 366 1257 27 1258 17 718 39 48 46 27 161 0 0 0 0 40 0 7 6 42 0 7 6 42 0 25 27 0 0 25 27 0 0 165 44 31 905>;
    		adi,orx-profile-orx-ddc-mode = <0>;
    		adi,orx-profile-orx-merge-filter = /bits/ 16  <0 0 0 0 0 0 0 0 0 0 0 0>;
    
    		adi,orx-gain-control-gain-mode = <0>;
    		adi,orx-gain-control-orx1-gain-index = <255>;
    		adi,orx-gain-control-orx2-gain-index = <255>;
    		adi,orx-gain-control-orx1-max-gain-index = <255>;
    		adi,orx-gain-control-orx1-min-gain-index = <195>;
    		adi,orx-gain-control-orx2-max-gain-index = <255>;
    		adi,orx-gain-control-orx2-min-gain-index = <195>;
    
    		adi,obs-settings-framer-sel = <1>;
    		adi,obs-settings-obs-rx-channels-enable = <3>;
    		adi,obs-settings-obs-rx-lo-source = <0>;
    
    		/* TX */
    
    		adi,tx-profile-tx-fir-gain_db = <6>;
    		adi,tx-profile-tx-fir-num-fir-coefs = <80>;
    		adi,tx-profile-tx-fir-coefs = /bits/ 16  <(0) (0) (0) (1) (0) (-3) (1) (7) (-3) (-13) (7) (25) (-14) (-42) (27) (69) (-46) (-107) (74) (160) (-115) (-229) (184) (336) (-264) (-468) (382) (653) (-538) (-904) (754) (1269) (-1056) (-1842) (1486) (2879) (-2031) (-4846) (3816) (16221) (16221) (3816) (-4846) (-2031) (2879) (1486) (-1842) (-1056) (1269) (754) (-904) (-538) (653) (382) (-468) (-264) (336) (184) (-229) (-115) (160) (74) (-107) (-46) (69) (27) (-42) (-14) (25) (7) (-13) (-3) (7) (1) (-3) (0) (1) (0) (0) (0)>;
    		//adi,tx-profile-tx-fir-coefs = /bits/ 16  < (0) ( -1) ( 1) ( -1) ( -3) ( 11) ( -14) ( 12) ( 20) ( -72) ( 85) ( -69) ( -88) ( 302) ( -340) ( 264) ( 284) ( -952) ( 1010) ( -755) ( -723) ( 2372) ( -2338) ( 1721) ( 1515) ( -4823) ( 4385) ( -3190) ( -2583) ( 8316) ( -6637) ( 5054) ( 3611) ( -12551) ( 7717) ( -7242) ( -3574) ( 19348) ( 8) ( 21575) ( 21575) ( 8) ( 19348) ( -3574) ( -7242) ( 7717) ( -12551) ( 3611) ( 5054) ( -6637) ( 8316) ( -2583) ( -3190) ( 4385) ( -4823) ( 1515) ( 1721) ( -2338) ( 2372) ( -723) ( -755) ( 1010) ( -952) ( 284) ( 264) ( -340) ( 302) ( -88) ( -69) ( 85) ( -72) ( 20) ( 12) ( -14) ( 11) ( -3) ( -1) ( 1) ( -1) ( 0)>;
    		adi,tx-profile-dac-div = <1>;
    
    		adi,tx-profile-tx-fir-interpolation = <2>;
    		adi,tx-profile-thb1-interpolation = <2>;
    		adi,tx-profile-thb2-interpolation = <2>;
    		adi,tx-profile-thb3-interpolation = <2>;
    		adi,tx-profile-tx-int5-interpolation = <1>;
    		adi,tx-profile-tx-input-rate_khz = <122880>;
    		adi,tx-profile-primary-sig-bandwidth_hz = <50000000>;
    		adi,tx-profile-rf-bandwidth_hz = <100000000>;
    		adi,tx-profile-tx-dac3d-bcorner_khz = <187000>;
    		adi,tx-profile-tx-bbf3d-bcorner_khz = <56000>;
    		adi,tx-profile-loop-back-adc-profile = /bits/ 16 <265 146 181 90 1280 366 1257 27 1258 17 718 39 48 46 27 161 0 0 0 0 40 0 7 6 42 0 7 6 42 0 25 27 0 0 25 27 0 0 165 44 31 905>;
    
    		adi,tx-settings-deframer-sel = <0>;
    		adi,tx-settings-tx-channels = <3>;
    		adi,tx-settings-tx-atten-step-size = <0>;
    		adi,tx-settings-tx1-atten_md-b = <10000>;
    		adi,tx-settings-tx2-atten_md-b = <10000>;
    		adi,tx-settings-dis-tx-data-if-pll-unlock = <2>;
    
    		/* Clocks */
    
    		adi,dig-clocks-device-clock_khz = <245760>;
    		adi,dig-clocks-clk-pll-vco-freq_khz = <9830400>;
    		adi,dig-clocks-clk-pll-hs-div = <1>;
    		adi,dig-clocks-rf-pll-use-external-lo = <0>;
    		adi,dig-clocks-rf-pll-phase-sync-mode = <0>;
    
    		/* AGC */
    
    		adi,rxagc-peak-agc-under-range-low-interval_ns = <205>;
    		adi,rxagc-peak-agc-under-range-mid-interval = <2>;
    		adi,rxagc-peak-agc-under-range-high-interval = <4>;
    		adi,rxagc-peak-apd-high-thresh = <39>;
    		adi,rxagc-peak-apd-low-gain-mode-high-thresh = <36>;
    		adi,rxagc-peak-apd-low-thresh = <23>;
    		adi,rxagc-peak-apd-low-gain-mode-low-thresh = <19>;
    		adi,rxagc-peak-apd-upper-thresh-peak-exceeded-cnt = <6>;
    		adi,rxagc-peak-apd-lower-thresh-peak-exceeded-cnt = <3>;
    		adi,rxagc-peak-apd-gain-step-attack = <4>;
    		adi,rxagc-peak-apd-gain-step-recovery = <2>;
    		adi,rxagc-peak-enable-hb2-overload = <1>;
    		adi,rxagc-peak-hb2-overload-duration-cnt = <1>;
    		adi,rxagc-peak-hb2-overload-thresh-cnt = <4>;
    		adi,rxagc-peak-hb2-high-thresh = <181>;
    		adi,rxagc-peak-hb2-under-range-low-thresh = <45>;
    		adi,rxagc-peak-hb2-under-range-mid-thresh = <90>;
    		adi,rxagc-peak-hb2-under-range-high-thresh = <128>;
    		adi,rxagc-peak-hb2-upper-thresh-peak-exceeded-cnt = <6>;
    		adi,rxagc-peak-hb2-lower-thresh-peak-exceeded-cnt = <3>;
    		adi,rxagc-peak-hb2-gain-step-high-recovery = <2>;
    		adi,rxagc-peak-hb2-gain-step-low-recovery = <4>;
    		adi,rxagc-peak-hb2-gain-step-mid-recovery = <8>;
    		adi,rxagc-peak-hb2-gain-step-attack = <4>;
    		adi,rxagc-peak-hb2-overload-power-mode = <1>;
    		adi,rxagc-peak-hb2-ovrg-sel = <0>;
    		adi,rxagc-peak-hb2-thresh-config = <3>;
    
    		adi,rxagc-power-power-enable-measurement = <1>;
    		adi,rxagc-power-power-use-rfir-out = <1>;
    		adi,rxagc-power-power-use-bbdc2 = <0>;
    		adi,rxagc-power-under-range-high-power-thresh = <9>;
    		adi,rxagc-power-under-range-low-power-thresh = <2>;
    		adi,rxagc-power-under-range-high-power-gain-step-recovery = <4>;
    		adi,rxagc-power-under-range-low-power-gain-step-recovery = <4>;
    		adi,rxagc-power-power-measurement-duration = <5>;
    		adi,rxagc-power-rx1-tdd-power-meas-duration = <5>;
    		adi,rxagc-power-rx1-tdd-power-meas-delay = <1>;
    		adi,rxagc-power-rx2-tdd-power-meas-duration = <5>;
    		adi,rxagc-power-rx2-tdd-power-meas-delay = <1>;
    		adi,rxagc-power-upper0-power-thresh = <2>;
    		adi,rxagc-power-upper1-power-thresh = <0>;
    		adi,rxagc-power-power-log-shift = <0>;
    
    		adi,rxagc-agc-peak-wait-time = <4>;
    		adi,rxagc-agc-rx1-max-gain-index = <255>;
    		adi,rxagc-agc-rx1-min-gain-index = <195>;
    		adi,rxagc-agc-rx2-max-gain-index = <255>;
    		adi,rxagc-agc-rx2-min-gain-index = <195>;
    		adi,rxagc-agc-gain-update-counter_us = <250>;
    		adi,rxagc-agc-rx1-attack-delay = <10>;
    		adi,rxagc-agc-rx2-attack-delay = <10>;
    		adi,rxagc-agc-slow-loop-settling-delay = <16>;
    		adi,rxagc-agc-low-thresh-prevent-gain = <0>;
    		adi,rxagc-agc-change-gain-if-thresh-high = <1>;
    		adi,rxagc-agc-peak-thresh-gain-control-mode = <1>;
    		adi,rxagc-agc-reset-on-rxon = <0>;
    		adi,rxagc-agc-enable-sync-pulse-for-gain-counter = <0>;
    		adi,rxagc-agc-enable-ip3-optimization-thresh = <0>;
    		adi,rxagc-ip3-over-range-thresh = <31>;
    		adi,rxagc-ip3-over-range-thresh-index = <246>;
    		adi,rxagc-ip3-peak-exceeded-cnt = <4>;
    		adi,rxagc-agc-enable-fast-recovery-loop = <0>;
    
    
    		/* Misc */
    
    		adi,aux-dac-enables = <0x00>; /* Mask */
    
    		adi,aux-dac-vref0 = <3>;
    		adi,aux-dac-resolution0 = <0>;
    		adi,aux-dac-values0 = <0>;
    		adi,aux-dac-vref1 = <3>;
    		adi,aux-dac-resolution1 = <0>;
    		adi,aux-dac-values1 = <0>;
    		adi,aux-dac-vref2 = <3>;
    		adi,aux-dac-resolution2 = <0>;
    		adi,aux-dac-values2 = <0>;
    		adi,aux-dac-vref3 = <3>;
    		adi,aux-dac-resolution3 = <0>;
    		adi,aux-dac-values3 = <0>;
    		adi,aux-dac-vref4 = <3>;
    		adi,aux-dac-resolution4 = <0>;
    		adi,aux-dac-values4 = <0>;
    		adi,aux-dac-vref5 = <3>;
    		adi,aux-dac-resolution5 = <0>;
    		adi,aux-dac-values5 = <0>;
    		adi,aux-dac-vref6 = <3>;
    		adi,aux-dac-resolution6 = <0>;
    		adi,aux-dac-values6 = <0>;
    		adi,aux-dac-vref7 = <3>;
    		adi,aux-dac-resolution7 = <0>;
    		adi,aux-dac-values7 = <0>;
    		adi,aux-dac-vref8 = <3>;
    		adi,aux-dac-resolution8 = <0>;
    		adi,aux-dac-values8 = <0>;
    		adi,aux-dac-vref9 = <3>;
    		adi,aux-dac-resolution9 = <0>;
    		adi,aux-dac-values9 = <0>;
    		adi,aux-dac-vref10 = <3>;
    		adi,aux-dac-resolution10 = <0>;
    		adi,aux-dac-values10 = <0>;
    		adi,aux-dac-vref11 = <3>;
    		adi,aux-dac-resolution11 = <0>;
    		adi,aux-dac-values11 = <0>;
    
    		adi,arm-gpio-config-orx1-tx-sel0-pin-gpio-pin-sel = <0>;
    		adi,arm-gpio-config-orx1-tx-sel0-pin-polarity = <0>;
    		adi,arm-gpio-config-orx1-tx-sel0-pin-enable = <0>;
    
    		adi,arm-gpio-config-orx1-tx-sel1-pin-gpio-pin-sel = <0>;
    		adi,arm-gpio-config-orx1-tx-sel1-pin-polarity = <0>;
    		adi,arm-gpio-config-orx1-tx-sel1-pin-enable = <0>;
    		adi,arm-gpio-config-orx2-tx-sel0-pin-gpio-pin-sel = <0>;
    		adi,arm-gpio-config-orx2-tx-sel0-pin-polarity = <0>;
    		adi,arm-gpio-config-orx2-tx-sel0-pin-enable = <0>;
    
    		adi,arm-gpio-config-orx2-tx-sel1-pin-gpio-pin-sel = <0>;
    		adi,arm-gpio-config-orx2-tx-sel1-pin-polarity = <0>;
    		adi,arm-gpio-config-orx2-tx-sel1-pin-enable = <0>;
    		adi,arm-gpio-config-en-tx-tracking-cals-gpio-pin-sel = <0>;
    		adi,arm-gpio-config-en-tx-tracking-cals-polarity = <0>;
    		adi,arm-gpio-config-en-tx-tracking-cals-enable = <0>;
    
    		adi,orx-lo-cfg-disable-aux-pll-relocking = <0>;
    		adi,orx-lo-cfg-gpio-select = <19>;
    
    		adi,fhm-config-fhm-gpio-pin = <0>;
    		adi,fhm-config-fhm-min-freq_mhz = <100>;
    		adi,fhm-config-fhm-max-freq_mhz = <100>;
    
    		adi,fhm-mode-fhm-enable = <0>;
    		adi,fhm-mode-enable-mcs-sync = <0>;
    		adi,fhm-mode-fhm-trigger-mode = <0>;
    		adi,fhm-mode-fhm-exit-mode = <0>;
    		adi,fhm-mode-fhm-init-frequency_hz = <2450000000>;
    
    		adi,rx1-gain-ctrl-pin-inc-step = <1>;
    		adi,rx1-gain-ctrl-pin-dec-step = <1>;
    		adi,rx1-gain-ctrl-pin-rx-gain-inc-pin = <0>;
    		adi,rx1-gain-ctrl-pin-rx-gain-dec-pin = <1>;
    		adi,rx1-gain-ctrl-pin-enable = <0>;
    
    		adi,rx2-gain-ctrl-pin-inc-step = <1>;
    		adi,rx2-gain-ctrl-pin-dec-step = <1>;
    		adi,rx2-gain-ctrl-pin-rx-gain-inc-pin = <3>;
    		adi,rx2-gain-ctrl-pin-rx-gain-dec-pin = <4>;
    		adi,rx2-gain-ctrl-pin-enable = <0>;
    
    		adi,tx1-atten-ctrl-pin-step-size = <0>;
    		adi,tx1-atten-ctrl-pin-tx-atten-inc-pin = <4>;
    		adi,tx1-atten-ctrl-pin-tx-atten-dec-pin = <5>;
    		adi,tx1-atten-ctrl-pin-enable = <0>;
    
    		adi,tx2-atten-ctrl-pin-step-size = <0>;
    		adi,tx2-atten-ctrl-pin-tx-atten-inc-pin = <6>;
    		adi,tx2-atten-ctrl-pin-tx-atten-dec-pin = <7>;
    		adi,tx2-atten-ctrl-pin-enable = <0>;
    
    		adi,tx-pa-protection-avg-duration = <3>;
    		adi,tx-pa-protection-tx-atten-step = <2>;
    		adi,tx-pa-protection-tx1-power-threshold = <4096>;
    		adi,tx-pa-protection-tx2-power-threshold = <4096>;
    		adi,tx-pa-protection-peak-count = <4>;
    		adi,tx-pa-protection-tx1-peak-threshold = <130>;
    		adi,tx-pa-protection-tx2-peak-threshold = <130>;
    	};	
    
    	hmc7044: hmc7044@2 {
    		#address-cells = <1>;
    		#size-cells = <0>;		
    		#clock-cells = <1>;
    
    		compatible = "adi,hmc7044";
    		reg = <2>; // SPI CS 2
    		//spi-max-frequency = <10000000>;
    		spi-max-frequency = <100000>;
    		adi,sync-pin-mode = <1>;
    		adi,pll1-clkin-frequencies = <40000000 0 0 0>;
    		adi,pll1-ref-prio-ctrl = <0xE4>; /* prefer CLKIN0 */
    
    		adi,pll1-loop-bandwidth = <200>;
    
    		adi,vcxo-frequency = <122880000>;
    
    		adi,pll2-output-frequency = <2949120000>;
    
    		adi,sysref-timer-divider = <3840>;
    		adi,pulse-generator-mode = <0>;
    
    		adi,clkin0-buffer-mode = <0x0D>;
    		adi,clkin1-buffer-mode = <0x0D>;
    		adi,clkin2-buffer-mode = <0x0D>;
    		adi,clkin3-buffer-mode = <0x0D>;		
    		adi,oscin-buffer-mode = <0x07>;
    
    		adi,gpi-controls = <0x00 0x00 0x00 0x11>;
    		adi,gpo-controls = <0x1f 0x2b 0x00 0x00>;
    
    		clock-output-names = 
    			"hmc7044_out0_DEV_REFCLK_A", "hmc7044_out1_DEV_SYSREF_A",
    			"hmc7044_out2_DEV_REFCLK_B", "hmc7044_out3_DEV_SYSREF_B",
    			"hmc7044_out4_JESD_REFCLK_TX_OBS_AB", "hmc7044_out5_JESD_REFCLK_RX_AB",
    			"hmc7044_out6_CORE_CLK_TX_OBS_AB", "hmc7044_out7_CORE_CLK_RX_AB",
    			"hmc7044_out8_FPGA_SYSREF_TX_OBS_AB","hmc7044_out9_FPGA_SYSREF_RX_AB",
    			"hmc7044_out10", "hmc7044_out11",
    			"hmc7044_out12", "hmc7044_out13";				
    
    		hmc7044_c0: channel@0 {
    			reg = <0>;
    			adi,extended-name = "DEV_REFCLK_A";
    			adi,divider = <12>;	// 245760000
    			adi,driver-mode = <2>;	// LVDS
    			adi,coarse-digital-delay = <15>;
    		};
    		hmc7044_c1: channel@1 {
    			reg = <1>;
    			adi,extended-name = "DEV_SYSREF_A";
    			adi,divider = <3840>;	// 768000
    			adi,driver-mode = <1>;	// LVPECL  
    			adi,startup-mode-dynamic-enable;
    			adi,high-performance-mode-disable;
    			adi,driver-impedance-mode = <1>;
    			adi,force-mute-enable;
    			adi,control0-rb4-enable;
    		};
    		hmc7044_c2: channel@2 {
    			reg = <2>;
    			adi,extended-name = "DEV_REFCLK_B";
    			adi,divider = <12>;	// 245760000
    			adi,driver-mode = <2>;	// LVDS
    			adi,coarse-digital-delay = <15>;
    		};
    		hmc7044_c3: channel@3 {
    			reg = <3>;
    			adi,extended-name = "DEV_SYSREF_B";
    			adi,divider = <3840>;	// 768000
    			adi,driver-mode = <1>;	// LVPECL
    			adi,startup-mode-dynamic-enable;
    			adi,high-performance-mode-disable;
    			adi,driver-impedance-mode = <0>;
    			adi,force-mute-enable;
    			adi,control0-rb4-enable;
    		};
    		hmc7044_c4: channel@4 {
    			reg = <4>;
    			adi,extended-name = "JESD_REFCLK_TX_OBS_AB";
    			adi,divider = <12>;	// 245760000
    			adi,driver-mode = <2>;	// LVDS
    		};
    		hmc7044_c5: channel@5 {
    			reg = <5>;
    			adi,extended-name = "JESD_REFCLK_RX_AB";
    			adi,divider = <12>;	// 245760000
    			adi,driver-mode = <2>;	// LVDS
    		};
    //		hmc7044_c6: channel@6 {
    //			reg = <6>;
    //			adi,extended-name = "CORE_CLK_TX_OBS_AB";
    //			adi,divider = <24>;	// 122880000
    //			adi,driver-mode = <0>;	// 
    //		};
    //		hmc7044_c7: channel@7 {
    //			reg = <7>;
    //			adi,extended-name = "CORE_CLK_RX_AB";
    //			adi,divider = <12>;	// 245760000
    //			adi,driver-mode = <0>;	// LVDS
    //		};
    		hmc7044_c8: channel@8 {
    			reg = <8>;
    			adi,extended-name = "FPGA_SYSREF_TX_OBS_AB";
    			adi,divider = <3840>;	// 768000
    			adi,driver-mode = <1>;	// 
    			adi,startup-mode-dynamic-enable;
    			adi,high-performance-mode-disable;
    			adi,force-mute-enable;
    			adi,control0-rb4-enable;
    		};
    		hmc7044_c9: channel@9 {
    			reg = <9>;
    			adi,extended-name = "FPGA_SYSREF_RX_AB";
    			adi,divider = <3840>;	// 768000
    			adi,driver-mode = <1>;	// LVDS
    			adi,startup-mode-dynamic-enable;
    			adi,high-performance-mode-disable;
    			adi,force-mute-enable;
    			adi,control0-rb4-enable;
    		};
    
    	};
    
    };
    
    // SPDX-License-Identifier: GPL-2.0
    /*
     * Analog Devices ADRV9009
     * https://wiki.analog.com/resources/eval/user-guides/adrv9009
     * https://wiki.analog.com/resources/tools-software/linux-drivers/iio-transceiver/adrv9009
     * https://wiki.analog.com/resources/tools-software/linux-software/adrv9009_advanced_plugin
     *
     * hdl_project: <adrv9009/zc706>
     * board_revision: <>
     *
     * Copyright (C) 2019 Analog Devices Inc.
     */
    #include "zynq-zc706.dtsi"
    //#include "zynq-7000.dtsi"
    //#include "zc706.dtsi"
    
    #include "zynq-zc706-adv7511_mod.dtsi"
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/jesd204/adxcvr.h>
    
    //&i2c_mux {
    //	i2c@5 { /* HPC IIC */
    //		#address-cells = <1>;
    //		#size-cells = <0>;
    //		reg = <5>;
    //
    //		eeprom@50 {
    //			compatible = "at24,24c02";
    //			reg = <0x50>;
    //		};
    //
    //		eeprom@54 {
    //			compatible = "at24,24c02";
    //			reg = <0x54>;
    //		};
    //
    //		ad7291@2f {
    //			compatible = "adi,ad7291";
    //			reg = <0x2f>;
    //		};
    //	};
    //};
    
    &fpga_axi {
    	rx_dma: rx-dmac@7c400000 {
    		compatible = "adi,axi-dmac-1.00.a";
    		reg = <0x7c400000 0x10000>;
    		#dma-cells = <1>;
    		interrupt-parent = <&intc>;
    		interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
    		clocks = <&clkc 16>;
    
    		adi,channels {
    			#size-cells = <0>;
    			#address-cells = <1>;
    
    			dma-channel@0 {
    				reg = <0>;
    				adi,source-bus-width = <64>;
    				adi,source-bus-type = <2>;
    				adi,destination-bus-width = <64>;
    				adi,destination-bus-type = <0>;
    			};
    		};
    	};
    
    //	rx_obs_dma: rx-obs-dmac@7c440000  {
    //		compatible = "adi,axi-dmac-1.00.a";
    //		reg = <0x7c440000  0x10000>;
    //		#dma-cells = <1>;
    //		interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
    //		clocks = <&clkc 16>;
    //
    //		adi,channels {
    //			#size-cells = <0>;
    //			#address-cells = <1>;
    //
    //			dma-channel@0 {
    //				reg = <0>;
    //				adi,source-bus-width = <128>;
    //				adi,source-bus-type = <2>;
    //				adi,destination-bus-width = <64>;
    //				adi,destination-bus-type = <0>;
    //			};
    //		};
    //	};
    
    //	tx_dma: tx-dmac@7c420000 {
    //		compatible = "adi,axi-dmac-1.00.a";
    //		reg = <0x7c420000 0x10000>;
    //		#dma-cells = <1>;
    //		//interrupt-parent = <&axi_intc>;
    //		interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
    //		clocks = <&clkc 16>;
    //
    //		adi,channels {
    //			#size-cells = <0>;
    //			#address-cells = <1>;
    //
    //			dma-channel@0 {
    //				reg = <0>;
    //				adi,source-bus-width = <64>;
    //				adi,source-bus-type = <0>;
    //				adi,destination-bus-width = <64>;
    //				adi,destination-bus-type = <1>;
    //			};
    //		};
    //	};
    
    	axi_adrv9009_core_rx: axi-adrv9009-rx-hpc@44a00000 {
    		compatible = "adi,axi-adrv9009-rx-1.0";
    		reg = <0x44a00000 0x8000>;
    		dmas = <&rx_dma 0>;
    		dma-names = "rx";
    		spibus-connected = <&trx0_adrv9009>;
    		adi,axi-decimation-core-available;
    		decimation-gpios = <&gpio0 115 GPIO_ACTIVE_HIGH>;
    	};
    
    //	axi_adrv9009_core_rx_obs: axi-adrv9009-rx-obs-hpc@44a08000 {
    //		compatible = "adi,axi-adrv9009-obs-1.0";
    //		reg = <0x44a08000 0x1000>;
    //		dmas = <&rx_obs_dma 0>;
    //		dma-names = "rx";
    //		clocks = <&trx0_adrv9009 1>;
    //		clock-names = "sampl_clk";
    //	};
    
    	axi_adrv9009_core_tx: axi-adrv9009-tx-hpc@44a14000 {
    		compatible = "adi,axi-adrv9009-tx-1.0";
    		reg = <0x44a14000 0x4000>;
    		//dmas = <&tx_dma 0>;
    		//dma-names = "tx";
    		clocks = <&trx0_adrv9009 2>;
    		clock-names = "sampl_clk";
    		spibus-connected = <&trx0_adrv9009>;
    		adi,axi-pl-fifo-enable;
    		adi,axi-interpolation-core-available;
    		interpolation-gpios = <&gpio0 116 GPIO_ACTIVE_HIGH>;
    	};
    
    	axi_adrv9009_rx_jesd: axi-jesd204-rx@44aa0000 {
    		compatible = "adi,axi-jesd204-rx-1.0";
    		reg = <0x44aa0000 0x1000>;
    		interrupt-parent = <&intc>;
    		interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
    
    		clocks = <&clkc 16>, <&axi_rx_clkgen>, <&axi_adrv9009_adxcvr_rx 0>;
    		//clocks = <&clkc 16>, <&hmc7044 1>, <&axi_adrv9009_adxcvr_rx 0>;
    		clock-names = "s_axi_aclk", "device_clk", "lane_clk";
    
    		#clock-cells = <0>;
    		clock-output-names = "jesd_rx_lane_clk";
    
    		adi,octets-per-frame = <4>;
    		adi,frames-per-multiframe = <32>;
    	};
    
    	axi_adrv9009_tx_jesd: axi-jesd204-tx@44a90000 {
    		compatible = "adi,axi-jesd204-tx-1.0";
    		reg = <0x44a90000 0x1000>;
    		interrupt-parent = <&intc>;
    		interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>;
    
    		clocks = <&clkc 16>, <&axi_tx_clkgen>, <&axi_adrv9009_adxcvr_tx 0>;
    		//clocks = <&clkc 16>, <&hmc7044 1>, <&axi_adrv9009_adxcvr_tx 0>;
    		clock-names = "s_axi_aclk", "device_clk", "lane_clk";
    
    		#clock-cells = <0>;
    		clock-output-names = "jesd_tx_lane_clk";
    
    		adi,octets-per-frame = <2>;
    		adi,frames-per-multiframe = <32>;
    		adi,converter-resolution = <16>;
    		adi,bits-per-sample = <16>;
    		adi,converters-per-device = <4>;
    		adi,control-bits-per-sample = <0>;
    	};
    
    //	axi_adrv9009_rx_os_jesd: axi-jesd204-rx-os@44ab0000 {
    //		compatible = "adi,axi-jesd204-rx-1.0";
    //		reg = <0x44ab0000 0x1000>;
    //
    //		interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
    //
    //		clocks = <&clkc 16>, <&axi_rx_os_clkgen>, <&axi_adrv9009_adxcvr_rx_os 0>;
    //		clock-names = "s_axi_aclk", "device_clk", "lane_clk";
    //
    //		#clock-cells = <0>;
    //		clock-output-names = "jesd_rx_os_lane_clk";
    //
    //		adi,octets-per-frame = <4>;
    //		adi,frames-per-multiframe = <32>;
    //	};
    
    	axi_tx_clkgen: axi-clkgen@43c00000  {
    		compatible = "adi,axi-clkgen-2.00.a";
    		reg = <0x43c00000 0x10000>;
    		#clock-cells = <0>;
    		clocks = <&clkc 15>, <&hmc7044 4>;
    		clock-names = "s_axi_aclk", "clkin1";
    		clock-output-names = "axi_tx_clkgen";
    	};
    
    	axi_rx_clkgen: axi-clkgen@43c10000  {
    		compatible = "adi,axi-clkgen-2.00.a";
    		reg = <0x43c10000 0x10000>;
    		#clock-cells = <0>;
    		clocks = <&clkc 15>, <&hmc7044 4>;
    		clock-names = "s_axi_aclk", "clkin1";
    		clock-output-names = "axi_rx_clkgen";
    	};
    
    //	axi_rx_os_clkgen: axi-clkgen@43c20000  {
    //		compatible = "adi,axi-clkgen-2.00.a";
    //		reg = <0x43c20000 0x10000>;
    //		#clock-cells = <0>;
    //		clocks = <&clkc 15>, <&clk0_ad9528 1>;
    //		clock-names = "s_axi_aclk", "clkin1";
    //		clock-output-names = "axi_rx_os_clkgen";
    //	};
    
    	axi_adrv9009_adxcvr_rx: axi-adxcvr-rx@44a60000 {
    		#address-cells = <1>;
    		#size-cells = <0>;
    		compatible = "adi,axi-adxcvr-1.0";
    		reg = <0x44a60000 0x1000>;
    
    		//clocks = <&hmc7044 1>, <&axi_rx_clkgen 0>;
    		clocks = <&hmc7044 4>;
    		//clock-names = "conv", "div40";
    		clock-names = "conv";
    
    		#clock-cells = <1>;
    		clock-output-names = "rx_gt_clk", "rx_out_clk";
    
    		adi,sys-clk-select = <XCVR_CPLL>;
    		adi,out-clk-select = <XCVR_REFCLK>;
    		adi,use-lpm-enable;
    	};
    
    //	axi_adrv9009_adxcvr_rx_os: axi-adxcvr-rx-os@44a50000 {
    //		#address-cells = <1>;
    //		#size-cells = <0>;
    //		compatible = "adi,axi-adxcvr-1.0";
    //		reg = <0x44a50000 0x1000>;
    //
    //		clocks = <&clk0_ad9528 1>, <&axi_rx_os_clkgen>;
    //		clock-names = "conv", "div40";
    //
    //		#clock-cells = <1>;
    //		clock-output-names = "rx_os_gt_clk", "rx_os_out_clk";
    //
    //		adi,sys-clk-select = <XCVR_CPLL>;
    //		adi,out-clk-select = <XCVR_REFCLK>;
    //		adi,use-lpm-enable;
    //	};
    
    	axi_adrv9009_adxcvr_tx: axi-adxcvr-tx@44a80000 {
    		#address-cells = <1>;
    		#size-cells = <0>;
    		compatible = "adi,axi-adxcvr-1.0";
    		reg = <0x44a80000 0x1000>;
    
    		//clocks = <&hmc7044 1>, <&axi_tx_clkgen>;
    		clocks = <&hmc7044 4>;
    		//clock-names = "conv", "div40";
    		clock-names = "conv";
    
    		#clock-cells = <1>;
    		clock-output-names = "tx_gt_clk", "tx_out_clk";
    
    		adi,sys-clk-select = <XCVR_QPLL>;
    		adi,out-clk-select = <XCVR_REFCLK>;
    	};
    };
    
    &spi0 {
    	status = "okay";
    };
    
    #define fmc_spi spi0
    
    #include "adi-adrv9009_mod.dtsi"
    
    // adrv9009_dac_fifo_bypass_s 60   						// 114
    // ad9528_reset_b,       // 59 //hmc7044_reset_b        // 113 
    // ad9528_sysref_req,    // 58 //hmc7044_sysref_req     // 112
    // adrv9009_tx1_enable,    // 57						// 111
    // adrv9009_tx2_enable,    // 56                        // 110                                
    // adrv9009_rx1_enable,    // 55                        // 109                 
    // adrv9009_rx2_enable,    // 54                        // 108                 
    // adrv9009_test,          // 53                        // 107                 
    // adrv9009_reset_b,       // 52                        // 106                 
    // adrv9009_gpint,         // 51                        // 105                 
    // adrv9009_gpio_00,       // 50                        // 104                 
    // adrv9009_gpio_01,       // 49                        // 103                 
    // adrv9009_gpio_02,       // 48                        // 102                 
    // adrv9009_gpio_03,       // 47                        // 101                 
    // adrv9009_gpio_04,       // 46                        // 100                 
    // adrv9009_gpio_05,       // 45                        // 99                 
    // adrv9009_gpio_06,       // 44                                         
    // adrv9009_gpio_07,       // 43                                         
    // adrv9009_gpio_15,       // 42                                         
    // adrv9009_gpio_08,       // 41                                         
    // adrv9009_gpio_09,       // 40                                         
    // adrv9009_gpio_10,       // 39                                         
    // adrv9009_gpio_11,       // 38                                         
    // adrv9009_gpio_12,       // 37                                         
    // adrv9009_gpio_14,       // 36                                         
    // adrv9009_gpio_13,       // 35                                         
    // adrv9009_gpio_17,       // 34                                         
    // adrv9009_gpio_16,       // 33                                         
    // adrv9009_gpio_18}));    // 32 + 54
    
    //&trx0_adrv9009 {
    //	reset-gpios = <&gpio0 106 0>;
    //	test-gpios = <&gpio0 107 0>;
    //	sysref-req-gpios = <&gpio0 112 0>;
    //	rx2-enable-gpios = <&gpio0 108 0>;
    //	rx1-enable-gpios = <&gpio0 109 0>;
    //	tx2-enable-gpios = <&gpio0 110 0>;
    //	tx1-enable-gpios = <&gpio0 111 0>;
    //};
    
    //&hmc7044 {
    //	reset-gpios = <&gpio0 113 0>;
    //};
    
    &amba_pl{
    	samplemodule_instance: samplemodule {
    		compatible = "etelm,samplemodule";
    		reg = <0x40000000 0x20000>;
    		etelm,reg_gpio0 = <0x41200000 0x1000>;
    		etelm,mem_tx   = <0x40000000 0x20000>;
    		interrupt-parent = <&intc>;
    		interrupts = < 0 56 1 >;
    	};
    };

    /dts-v1/;
    #include "system-user.dtsi"
    
    &axi_adrv9009_core_tx {
    	plddrbypass-gpios = <&gpio0 114 0>;
    };
    
    #include <dt-bindings/iio/adc/adi,adrv9009.h>
    
    &trx0_adrv9009 {
    
    	reset-gpios = <&gpio0 106 0>;
    	test-gpios = <&gpio0 107 0>;
    	sysref-req-gpios = <&gpio0 112 0>;
    	rx2-enable-gpios = <&gpio0 108 0>;
    	rx1-enable-gpios = <&gpio0 109 0>;
    	tx2-enable-gpios = <&gpio0 110 0>;
    	tx1-enable-gpios = <&gpio0 111 0>;
    	
    	jesd204-device;
    	#jesd204-cells = <2>;
    	jesd204-top-device = <0>; /* This is the TOP device */
    	jesd204-link-ids = <DEFRAMER_LINK_TX FRAMER_LINK_RX>;
    	
    	jesd204-ignore-errors;
    
    	jesd204-inputs =
    		<&axi_adrv9009_rx_jesd 0 FRAMER_LINK_RX>,
    		//<&axi_adrv9009_rx_os_jesd 0 FRAMER_LINK_ORX>,
    		<&axi_adrv9009_tx_jesd 0 DEFRAMER_LINK_TX>;
    
    	/delete-property/ interrupts;
    };
    
    &axi_adrv9009_rx_jesd {
    	jesd204-device;
    	#jesd204-cells = <2>;
    	jesd204-inputs = <&axi_adrv9009_adxcvr_rx 0 FRAMER_LINK_RX>;
    };
    
    
    &axi_adrv9009_tx_jesd {
    	jesd204-device;
    	#jesd204-cells = <2>;
    	jesd204-inputs = <&axi_adrv9009_adxcvr_tx 0 DEFRAMER_LINK_TX>;
    };
    
    &axi_adrv9009_adxcvr_rx {
        jesd204-device;
    	#jesd204-cells = <2>;
    	jesd204-inputs =  <&hmc7044 0 FRAMER_LINK_RX>;
    	//clocks = <&hmc7044 1>; /* div40 is controlled by axi_adrv9009_rx_jesd */
    	//clock-names = "conv";
    };
    
    &axi_adrv9009_adxcvr_tx {
        jesd204-device;
    	#jesd204-cells = <2>;
    	jesd204-inputs =  <&hmc7044 0 DEFRAMER_LINK_TX>;
    	//clocks = <&hmc7044 1>; /* div40 is controlled by axi_adrv9009_tx_jesd */
    	//clock-names = "conv";
    };
    
    &hmc7044 {
    	reset-gpios = <&gpio0 113 0>;
    	jesd204-device;
    	#jesd204-cells = <2>;
    	jesd204-sysref-provider;
    
    	//adi,sysref-pattern-mode = <SYSREF_PATTERN_NSHOT>;
    	///delete-property/ adi,sysref-request-enable;
    };
     
    
    
    

    Regards,

    Salah

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