AD9173 kernel driver dual link, direct clocking

Hi,

we have designed a board with a zynq ultrascale xczu4cg-fbvb900-1-e, 1x AD9173 12GHz dual DAC, 4x AD9680 500MHz dual ADC and a LTC6952 clock distribution.

Clocks:

  • 500MHz ADC clock
  • 12GHz DAC clock (through multipliers)
  • 500MHz FPGA RX & TX refclk
  • 10MHz sysref clocks

As starting point I want only test the AD9173 by using the dac_fmc_ebz project to test with the following configuration:

  • 12x interpolation in JESD Mode 8
  • dual link
  • single channel
  • 8x10Gbit/s
  • L=8, M=4, S=1, N=16

Now the device gets probed but the link is not up, as reported by jesd_status:

  (DEVICES) Found 1 JESD204 Link Layer peripherals

  (0): 84a90000.axi-jesd204-tx  [*]

  (STATUS)
  Link is                 disabled
  Link Status
  Measured Link Clock     off
  Reported Link Clock     500.000
  Lane rate
  Lane rate / 40
  LMFC rate
  SYSREF captured
  SYSREF alignment error
  SYNC~

I already realised, that the ad9173 kernel driver is not prepared for dual link (JESD Mode 8) and direct clocking (PLL always on), so I have modified ad9172.c, see attached patch. Also I realised, that the fixed-clock source in the device tree cannot be set to 12000000000 Hz, because of int32 restriction in the clock framework, so I have instantiated the 500MHz DAC refclk and did a x24 hack in the ad9172.c to have it 12G. Maybe you have a better idea?

Can you please have a look why it does not work? there is a message in dmesg: ad9172 spi2.0: 4 lanes @ 10000000 kBps, but dual link JESD mode 8 results in 8 lanes? Also it gives an error in the ad9172.c in the function clk_prepare_enable(st->conv.clk[CLK_DATA]);, so I have commented it out.

Can you please have a look into the attached files? Thanks!

Andreas

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[    0.000000] Linux version 4.19.0-g62d2f6580111-dirty (zta1@kalkulator-VirtualBox) (gcc version 7.2.0 (GCC)) #54 SMP Wed Nov 24 15:56:06 CET 2021
[    0.000000] Machine model: Enclustra XU8 SOM
[    0.000000] efi: Getting EFI parameters from FDT:
[    0.000000] efi: UEFI not found.
[    0.000000] cma: Reserved 256 MiB at 0x0000000070000000
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv1.1 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs
[    0.000000] psci: MIGRATE_INFO_TYPE not supported.
[    0.000000] psci: SMC Calling Convention v1.1
[    0.000000] random: get_random_bytes called from start_kernel+0xa8/0x414 with crng_init=0
[    0.000000] percpu: Embedded 22 pages/cpu @(____ptrval____) s51864 r8192 d30056 u90112
[    0.000000] Detected VIPT I-cache on CPU0
[    0.000000] CPU features: enabling workaround for ARM erratum 845719
[    0.000000] Speculative Store Bypass Disable mitigation not required
[    0.000000] CPU features: detected: Kernel page table isolation (KPTI)
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 517120
[    0.000000] Kernel command line: console=ttyPS0,115200 rw earlyprintk rootwait root=/dev/mmcblk1p2
[    0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)
[    0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)
[    0.000000] Memory: 1775728K/2097152K available (13308K kernel code, 1572K rwdata, 10684K rodata, 896K init, 339K bss, 59280K reserved, 262144K cma-reserved)
[    0.000000] rcu: Hierarchical RCU implementation.
[    0.000000] rcu:     RCU event tracing is enabled.
[    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=2.
[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] GIC: Adjusting CPU interface base to 0x00000000f902f000
[    0.000000] GIC: Using split EOI/Deactivate mode
[    0.000000] arch_timer: cp15 timer(s) running at 99.99MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x170f8de2d3, max_idle_ns: 440795206112 ns
[    0.000003] sched_clock: 56 bits at 99MHz, resolution 10ns, wraps every 4398046511101ns
[    0.000234] Console: colour dummy device 80x25
[    0.000252] Calibrating delay loop (skipped), value calculated using timer frequency.. 199.98 BogoMIPS (lpj=399960)
[    0.000261] pid_max: default: 32768 minimum: 301
[    0.000364] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)
[    0.000374] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)
[    0.001049] ASID allocator initialised with 32768 entries
[    0.001100] rcu: Hierarchical SRCU implementation.
[    0.001388] EFI services will not be available.
[    0.001465] smp: Bringing up secondary CPUs ...
[    0.001737] Detected VIPT I-cache on CPU1
[    0.001766] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
[    0.001824] smp: Brought up 1 node, 2 CPUs
[    0.001833] SMP: Total of 2 processors activated.
[    0.001839] CPU features: detected: 32-bit EL0 Support
[    0.002941] CPU: All CPU(s) started at EL2
[    0.002952] alternatives: patching kernel code
[    0.003789] devtmpfs: initialized
[    0.007963] Registered cp15_barrier emulation handler
[    0.007971] Registered setend emulation handler
[    0.008074] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[    0.008086] futex hash table entries: 512 (order: 3, 32768 bytes)
[    0.012938] xor: measuring software checksum speed
[    0.052024]    8regs     :  2302.000 MB/sec
[    0.092054]    8regs_prefetch:  2052.000 MB/sec
[    0.132083]    32regs    :  2830.000 MB/sec
[    0.172113]    32regs_prefetch:  2381.000 MB/sec
[    0.172117] xor: using function: 32regs (2830.000 MB/sec)
[    0.172127] pinctrl core: initialized pinctrl subsystem
[    0.172740] NET: Registered protocol family 16
[    0.172993] audit: initializing netlink subsys (disabled)
[    0.173436] vdso: 2 pages (1 code @ (____ptrval____), 1 data @ (____ptrval____))
[    0.173443] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[    0.173740] audit: type=2000 audit(0.172:1): state=initialized audit_enabled=0 res=1
[    0.174602] DMA: preallocated 256 KiB pool for atomic allocations
[    0.193498] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
[    0.260369] raid6: int64x1  gen()   391 MB/s
[    0.328337] raid6: int64x1  xor()   433 MB/s
[    0.396410] raid6: int64x2  gen()   673 MB/s
[    0.464464] raid6: int64x2  xor()   592 MB/s
[    0.532481] raid6: int64x4  gen()  1032 MB/s
[    0.600556] raid6: int64x4  xor()   734 MB/s
[    0.668642] raid6: int64x8  gen()   973 MB/s
[    0.736649] raid6: int64x8  xor()   741 MB/s
[    0.804748] raid6: neonx1   gen()   721 MB/s
[    0.872757] raid6: neonx1   xor()   832 MB/s
[    0.940830] raid6: neonx2   gen()  1156 MB/s
[    1.008861] raid6: neonx2   xor()  1186 MB/s
[    1.076912] raid6: neonx4   gen()  1503 MB/s
[    1.144972] raid6: neonx4   xor()  1426 MB/s
[    1.213018] raid6: neonx8   gen()  1646 MB/s
[    1.281063] raid6: neonx8   xor()  1524 MB/s
[    1.281067] raid6: using algorithm neonx8 gen() 1646 MB/s
[    1.281071] raid6: .... xor() 1524 MB/s, rmw enabled
[    1.281075] raid6: using neon recovery algorithm
[    1.281871] SCSI subsystem initialized
[    1.282028] usbcore: registered new interface driver usbfs
[    1.282059] usbcore: registered new interface driver hub
[    1.282087] usbcore: registered new device driver usb
[    1.282233] media: Linux media interface: v0.10
[    1.282259] videodev: Linux video capture interface: v2.00
[    1.282309] pps_core: LinuxPPS API ver. 1 registered
[    1.282313] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    1.282326] PTP clock support registered
[    1.282347] EDAC MC: Ver: 3.0.0
[    1.283696] zynqmp-ipi-mbox mailbox@ff990400: Probed ZynqMP IPI Mailbox driver.
[    1.283985] jesd204: found 0 devices and 0 topologies
[    1.284023] FPGA manager framework
[    1.284183] Advanced Linux Sound Architecture Driver Initialized.
[    1.284446] Bluetooth: Core ver 2.22
[    1.284469] NET: Registered protocol family 31
[    1.284473] Bluetooth: HCI device and connection manager initialized
[    1.284481] Bluetooth: HCI socket layer initialized
[    1.284486] Bluetooth: L2CAP socket layer initialized
[    1.284515] Bluetooth: SCO socket layer initialized
[    1.284928] clocksource: Switched to clocksource arch_sys_counter
[    1.284999] VFS: Disk quotas dquot_6.6.0
[    1.285039] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[    1.292022] NET: Registered protocol family 2
[    1.292434] tcp_listen_portaddr_hash hash table entries: 1024 (order: 2, 16384 bytes)
[    1.292461] TCP established hash table entries: 16384 (order: 5, 131072 bytes)
[    1.292566] TCP bind hash table entries: 16384 (order: 6, 262144 bytes)
[    1.292758] TCP: Hash tables configured (established 16384 bind 16384)
[    1.292814] UDP hash table entries: 1024 (order: 3, 32768 bytes)
[    1.292855] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)
[    1.292983] NET: Registered protocol family 1
[    1.293388] RPC: Registered named UNIX socket transport module.
[    1.293393] RPC: Registered udp transport module.
[    1.293397] RPC: Registered tcp transport module.
[    1.293401] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    1.294036] hw perfevents: no interrupt-affinity property for /pmu, guessing.
[    1.294136] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available
[    1.294857] Initialise system trusted keyrings
[    1.294947] workingset: timestamp_bits=62 max_order=19 bucket_order=0
[    1.295563] NFS: Registering the id_resolver key type
[    1.295574] Key type id_resolver registered
[    1.295578] Key type id_legacy registered
[    1.295587] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[    1.295603] jffs2: version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
[    2.371615] NET: Registered protocol family 38
[    2.427957] Key type asymmetric registered
[    2.427963] Asymmetric key parser 'x509' registered
[    2.427996] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
[    2.428002] io scheduler noop registered
[    2.428007] io scheduler deadline registered
[    2.428032] io scheduler cfq registered (default)
[    2.428037] io scheduler mq-deadline registered
[    2.428041] io scheduler kyber registered
[    2.468298] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[    2.471566] cacheinfo: Unable to detect cache hierarchy for CPU 0
[    2.476643] brd: module loaded
[    2.480853] loop: module loaded
[    2.481049] Registered mathworks_ip class
[    2.481757] mtdoops: mtd device (mtddev=name/number) must be supplied
[    2.483091] libphy: Fixed MDIO Bus: probed
[    2.484238] tun: Universal TUN/TAP device driver, 1.6
[    2.487403] CAN device driver interface
[    2.488257] usbcore: registered new interface driver asix
[    2.488283] usbcore: registered new interface driver ax88179_178a
[    2.488308] usbcore: registered new interface driver cdc_ether
[    2.488332] usbcore: registered new interface driver net1080
[    2.488358] usbcore: registered new interface driver cdc_subset
[    2.488383] usbcore: registered new interface driver zaurus
[    2.488418] usbcore: registered new interface driver cdc_ncm
[    2.489091] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    2.489097] ehci-pci: EHCI PCI platform driver
[    2.489347] usbcore: registered new interface driver uas
[    2.489382] usbcore: registered new interface driver usb-storage
[    2.489441] usbcore: registered new interface driver usbserial_generic
[    2.489464] usbserial: USB Serial support registered for generic
[    2.489486] usbcore: registered new interface driver ftdi_sio
[    2.489505] usbserial: USB Serial support registered for FTDI USB Serial Device
[    2.489529] usbcore: registered new interface driver upd78f0730
[    2.489549] usbserial: USB Serial support registered for upd78f0730
[    2.492358] rtc_zynqmp ffa60000.rtc: rtc core: registered ffa60000.rtc as rtc0
[    2.492432] i2c /dev entries driver
[    2.494226] usbcore: registered new interface driver uvcvideo
[    2.494230] USB Video Class driver (1.1.1)
[    2.496280] Bluetooth: HCI UART driver ver 2.3
[    2.496289] Bluetooth: HCI UART protocol H4 registered
[    2.496294] Bluetooth: HCI UART protocol BCSP registered
[    2.496323] Bluetooth: HCI UART protocol LL registered
[    2.496327] Bluetooth: HCI UART protocol ATH3K registered
[    2.496346] Bluetooth: HCI UART protocol Three-wire (H5) registered
[    2.496410] Bluetooth: HCI UART protocol Intel registered
[    2.496428] Bluetooth: HCI UART protocol QCA registered
[    2.496467] usbcore: registered new interface driver bcm203x
[    2.496496] usbcore: registered new interface driver bpa10x
[    2.496527] usbcore: registered new interface driver bfusb
[    2.496561] usbcore: registered new interface driver btusb
[    2.496566] Bluetooth: Generic Bluetooth SDIO driver ver 0.1
[    2.496609] usbcore: registered new interface driver ath3k
[    2.497009] EDAC MC0: Giving out device to module 1 controller synps_ddr_controller: DEV synps_edac (INTERRUPT)
[    2.497175] EDAC DEVICE0: Giving out device to module edac controller cache_err: DEV edac (POLLED)
[    2.497336] EDAC DEVICE1: Giving out device to module zynqmp-ocm-edac controller zynqmp_ocm: DEV ff960000.memory-controller (INTERRUPT)
[    2.497764] sdhci: Secure Digital Host Controller Interface driver
[    2.497768] sdhci: Copyright(c) Pierre Ossman
[    2.497771] sdhci-pltfm: SDHCI platform and OF driver helper
[    2.499466] ledtrig-cpu: registered to indicate activity on CPUs
[    2.499538] zynqmp_firmware_probe Platform Management API v1.1
[    2.499544] zynqmp_firmware_probe Trustzone version v1.0
[    2.502457] zynqmp-pinctrl firmware:zynqmp-firmware:pinctrl: zynqmp pinctrl initialized
[    2.524580] zynqmp_clk_mux_get_parent() getparent failed for clock: lpd_wdt, ret = -22
[    2.525202] alg: No test for xilinx-zynqmp-aes (zynqmp-aes)
[    2.525229] zynqmp_aes zynqmp_aes: AES Successfully Registered
[    2.525229]
[    2.525390] alg: No test for xilinx-keccak-384 (zynqmp-keccak-384)
[    2.525543] alg: No test for xilinx-zynqmp-rsa (zynqmp-rsa)
[    2.525744] usbcore: registered new interface driver usbhid
[    2.525748] usbhid: USB HID core driver
[    2.534612] axi_sysid 85000000.axi-sysid-0: [dac_fmc_ebz] [AD9173 - 08] on [zcu102] git <98b878707f7efa3c5ce248cc533f1e870b90b6d0> clean [2021-11-16 11:27:53] UTC
[    2.534943] fpga_manager fpga0: Xilinx ZynqMP FPGA Manager registered
[    2.535832] usbcore: registered new interface driver snd-usb-audio
[    2.537570] pktgen: Packet Generator for packet performance testing. Version: 2.75
[    2.539384] Initializing XFRM netlink socket
[    2.539457] NET: Registered protocol family 10
[    2.539824] Segment Routing with IPv6
[    2.539907] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[    2.540244] NET: Registered protocol family 17
[    2.540256] NET: Registered protocol family 15
[    2.540272] bridge: filtering via arp/ip/ip6tables is no longer available by default. Update your scripts to load br_netfilter if you need this.
[    2.540845] can: controller area network core (rev 20170425 abi 9)
[    2.540877] NET: Registered protocol family 29
[    2.540882] can: raw protocol (rev 20170425)
[    2.540887] can: broadcast manager protocol (rev 20170425 t)
[    2.540894] can: netlink gateway (rev 20170425) max_hops=1
[    2.541008] Bluetooth: RFCOMM TTY layer initialized
[    2.541016] Bluetooth: RFCOMM socket layer initialized
[    2.541032] Bluetooth: RFCOMM ver 1.11
[    2.541040] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
[    2.541044] Bluetooth: BNEP filters: protocol multicast
[    2.541051] Bluetooth: BNEP socket layer initialized
[    2.541055] Bluetooth: HIDP (Human Interface Emulation) ver 1.2
[    2.541061] Bluetooth: HIDP socket layer initialized
[    2.541167] 9pnet: Installing 9P2000 support
[    2.541178] NET: Registered protocol family 36
[    2.541194] Key type dns_resolver registered
[    2.541675] registered taskstats version 1
[    2.541680] Loading compiled-in X.509 certificates
[    2.542022] Btrfs loaded, crc32c=crc32c-generic
[    2.548092] ff000000.serial: ttyPS0 at MMIO 0xff000000 (irq = 33, base_baud = 6249999) is a xuartps
[    3.843564] console [ttyPS0] enabled
[    3.847982] of-fpga-region fpga-full: FPGA Region probed
[    3.854185] xilinx-zynqmp-dma fd500000.dma: ZynqMP DMA driver Probe success
[    3.861291] xilinx-zynqmp-dma fd510000.dma: ZynqMP DMA driver Probe success
[    3.868389] xilinx-zynqmp-dma fd520000.dma: ZynqMP DMA driver Probe success
[    3.875490] xilinx-zynqmp-dma fd530000.dma: ZynqMP DMA driver Probe success
[    3.882593] xilinx-zynqmp-dma fd540000.dma: ZynqMP DMA driver Probe success
[    3.889695] xilinx-zynqmp-dma fd550000.dma: ZynqMP DMA driver Probe success
[    3.896795] xilinx-zynqmp-dma fd560000.dma: ZynqMP DMA driver Probe success
[    3.903898] xilinx-zynqmp-dma fd570000.dma: ZynqMP DMA driver Probe success
[    3.911145] zynqmp_pll_disable() clock disable failed for rpll_int, ret = -13
[    3.928530] HMC703: Start Probing
[    3.928542] HMC703: Devicetree Parsing...
[    3.932396] HMC703: Finished Probing
[    3.937780] AD9173: channel-interpolation=1 dac-interpolation=12 jesd-subclass=0 jesd-dual-link-mode=1 jesd-link-mode=8 dac-rate-khz=12000000
[    3.954929] m25p80 spi0.0: non-uniform erase sector maps are not supported yet.
[    3.962268] m25p80 spi0.0: s25fl512s (65536 Kbytes)
[    3.967165] 6 fixed-partitions partitions found on MTD device spi0.0
[    3.973516] Creating 6 MTD partitions on "spi0.0":
[    3.978301] 0x000000000000-0x000000900000 : "qspi-bootimage"
[    3.984406] 0x000000900000-0x000002780000 : "qspi-kernel"
[    3.990201] 0x000001780000-0x000001800000 : "qspi-device-tree"
[    3.996420] 0x000003f80000-0x000004000000 : "qspi-bootargs"
[    4.002395] 0x000001800000-0x000001880000 : "qspi-bootscript"
[    4.008614] 0x000001880000-0x000003f80000 : "qspi-rootfs"
[    4.015209] zynqmp-pinctrl firmware:zynqmp-firmware:pinctrl: zynqmp_pinconf_cfg_set failed: pin 26 param 1 value 0
[    4.025963] macb ff0b0000.ethernet: Not enabling partial store and forward
[    4.033360] libphy: MACB_mii_bus: probed
[    4.110118] Micrel KSZ9031 Gigabit PHY ff0b0000.ethernet-ffffffff:03: attached PHY driver [Micrel KSZ9031 Gigabit PHY] (mii_bus:phy_addr=ff0b0000.ethernet-ffffffff:03, irq=POLL)
[    4.125935] macb ff0b0000.ethernet eth0: Cadence GEM rev 0x50070106 at 0xff0b0000 irq 20 (20:b0:f7:05:21:c8)
[    4.136063] xilinx-axipmon ffa00000.perf-monitor: Probed Xilinx APM
[    4.142596] xilinx-axipmon fd0b0000.perf-monitor: Probed Xilinx APM
[    4.149089] xilinx-axipmon fd490000.perf-monitor: Probed Xilinx APM
[    4.155576] xilinx-axipmon ffa10000.perf-monitor: Probed Xilinx APM
[    4.162999] dwc3-of-simple ff9d0000.usb0: dwc3_simple_set_phydata: Can't find usb3-phy
[    4.171759] cdns-i2c ff020000.i2c: 400 kHz mmio ff020000 irq 22
[    4.210000] mmc0: SDHCI controller on ff160000.mmc [ff160000.mmc] using ADMA 64-bit
[    4.253489] mmc1: SDHCI controller on ff170000.mmc [ff170000.mmc] using ADMA 64-bit
[    4.267506] axi_adxcvr 84a60000.axi-adxcvr-tx: AXI-ADXCVR-TX (17.01.a) using QPLL on GTH4 at 0x84A60000. Number of lanes: 8.
[    4.279608] AD9173: channel-interpolation=1 dac-interpolation=12 jesd-subclass=0 jesd-dual-link-mode=1 jesd-link-mode=8 dac-rate-khz=12000000
[    4.295209] ad9172 spi2.0: AD916x DAC Chip ID: 4
[    4.299825] ad9172 spi2.0: AD916x DAC Product ID: 9173
[    4.304960] ad9172 spi2.0: AD916x DAC Product Grade: 0
[    4.310090] ad9172 spi2.0: AD916x DAC Product Revision: 2
[    4.315480] ad9172 spi2.0: AD916x Revision: 1.1.1
[    4.320177] ad9172 spi2.0: PLL Input rate 120000000
[    4.325256] random: fast init done
[    4.330225] mmc0: new HS200 MMC card at address 0001
[    4.335666] mmcblk0: mmc0:0001 IB2916 14.6 GiB
[    4.340538] mmcblk0boot0: mmc0:0001 IB2916 partition 1 4.00 MiB
[    4.346807] mmcblk0boot1: mmc0:0001 IB2916 partition 2 4.00 MiB
[    4.352822] mmcblk0rpmb: mmc0:0001 IB2916 partition 3 4.00 MiB, chardev (242:0)
[    4.361182]  mmcblk0: p1
[    4.460190] mmc1: new high speed SDHC card at address 0001
[    4.466127] mmcblk1: mmc1:0001 0016G 15.2 GiB
[    4.470911] ad9172 spi2.0: PLL lock status 0,  DLL lock status: 1
[    4.477050]  mmcblk1: p1 p2 p3
[    4.700979] ad9172 spi2.0: Serdes PLL Locked (stat: 3)
[    4.813219] ad9172 spi2.0: code_grp_sync: 0
[    4.817403] ad9172 spi2.0: frame_sync_stat: 0
[    4.821749] ad9172 spi2.0: good_checksum_stat: 0
[    4.826357] ad9172 spi2.0: init_lane_sync_stat: 0
[    4.831055] ad9172 spi2.0: 4 lanes @ 10000000 kBps
[    4.836429] ad9172 spi2.0: Probed.
[    4.841963] rtc_zynqmp ffa60000.rtc: setting system clock to 1970-01-01 08:37:08 UTC (31028)
[    4.850400] of_cfs_init
[    4.852852] of_cfs_init: OK
[    4.855770] cfg80211: Loading compiled-in X.509 certificates for regulatory database
[    4.993680] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
[    5.001087] ALSA device list:
[    5.004040]   No soundcards found.
[    5.007779] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
[    5.016385] cfg80211: failed to load regulatory.db
[    5.039655] EXT4-fs (mmcblk1p2): mounted filesystem with ordered data mode. Opts: (null)
[    5.047759] VFS: Mounted root (ext4 filesystem) on device 179:26.
[    5.061046] devtmpfs: mounted
[    5.064172] Freeing unused kernel memory: 896K
[    5.072944] Run /sbin/init as init process
Mount failed for selinuxfs on /sys/fs/selinux:  No such file or directory
[    5.311550] random: init: uninitialized urandom read (12 bytes read)
[    5.524603] random: mountall: uninitialized urandom read (12 bytes read)
 * Setting up X socket directories...                                    [ OK ]
 * STARTDISTCC is set to false in /etc/default/distcc
 * /usr/bin/distccd not starting
 * Starting IIO Daemon iiod                                              [ OK ]

Last login: Thu Jan  1 08:36:04 UTC 1970 on ttyPS0
Welcome to Linaro 14.04 (GNU/Linux 4.19.0-g62d2f6580111-dirty aarch64)

 * Documentation:  https://wiki.analog.com/ https://ez.analog.com/

New release '16.04.7 LTS' available.
Run 'do-release-upgrade' to upgrade to it.

root@analog:~#

diff --git a/drivers/iio/frequency/ad9172.c b/drivers/iio/frequency/ad9172.c
index 488954bd21ce..71fd10a28881 100644
--- a/drivers/iio/frequency/ad9172.c
+++ b/drivers/iio/frequency/ad9172.c
@@ -108,7 +108,8 @@ static int ad9172_setup(struct ad9172_state *st)
 	uint8_t pll_lock_status = 0, dll_lock_stat = 0;
 	int ret, i;
 	u64 dac_rate_Hz;
-	unsigned long dac_clkin_Hz, lane_rate_kHz;
+	u64 dac_clkin_Hz;
+	unsigned long lane_rate_kHz;
 	ad917x_jesd_link_stat_t link_status;
 	ad917x_handle_t *ad917x_h = &st->dac_h;
 	unsigned long pll_mult;
@@ -149,14 +150,14 @@ static int ad9172_setup(struct ad9172_state *st)
 	dev_info(dev, "AD916x Revision: %d.%d.%d\n",
 		 revision[0], revision[1], revision[2]);
 
-	dac_clkin_Hz = clk_get_rate(st->conv.clk[CLK_DAC]);
+	dac_clkin_Hz = clk_get_rate(st->conv.clk[CLK_DAC]) * 24;
 
-	dev_info(dev, "PLL Input rate %lu\n", dac_clkin_Hz);
+	dev_info(dev, "PLL Input rate %llu\n", dac_clkin_Hz);
 
 	pll_mult = DIV_ROUND_CLOSEST(st->dac_rate_khz, dac_clkin_Hz / 1000);
 
 	ret = ad917x_set_dac_clk(ad917x_h, (u64)dac_clkin_Hz * pll_mult,
-				 1, dac_clkin_Hz);
+				 0, dac_clkin_Hz);
 	if (ret != 0) {
 		dev_err(dev, "ad917x_set_dac_clk failed (%d)\n", ret);
 		return ret;
@@ -251,7 +252,7 @@ static int ad9172_setup(struct ad9172_state *st)
 		return ret;
 	}
 
-	ret = clk_prepare_enable(st->conv.clk[CLK_DATA]);
+	//ret = clk_prepare_enable(st->conv.clk[CLK_DATA]);
 	if (ret) {
 		dev_err(dev, "Failed to enable JESD204 link: %d\n", ret);
 		return ret;
@@ -819,6 +820,9 @@ static int ad9172_parse_dt(struct spi_device *spi, struct ad9172_state *st)
 	st->jesd_link_mode = 10;
 	of_property_read_u32(np, "adi,jesd-link-mode", &st->jesd_link_mode);
 
+	st->jesd_dual_link_mode = 1;
+	of_property_read_u32(np, "adi,jesd-dual-link-mode", &st->jesd_dual_link_mode);
+
 	st->jesd_subclass = 0;
 	of_property_read_u32(np, "adi,jesd-subclass", &st->jesd_subclass);
 
@@ -844,9 +848,12 @@ static int ad9172_parse_dt(struct spi_device *spi, struct ad9172_state *st)
 	else
 		st->sysref_coupling = COUPLING_AC;
 
+	printk("AD9173: channel-interpolation=%d dac-interpolation=%d jesd-subclass=%d jesd-dual-link-mode=%d jesd-link-mode=%d dac-rate-khz=%d\n",st->channel_interpolation, st->dac_interpolation, st->jesd_subclass, st->jesd_dual_link_mode, st->jesd_link_mode, st->dac_rate_khz);
+
 	/*Logic lane configuration*/
 	ret = of_property_read_u8_array(np,"adi,logic-lanes-mapping",
 				      st->logic_lanes, sizeof(st->logic_lanes));
+
 	if (ret)
 		for(i = 0; i < sizeof(st->logic_lanes); i++)
 			st->logic_lanes[i] = i;
/dts-v1/;

#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include "zynq-enclustra-qspi64-parts.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/jesd204/adxcvr.h>

/*
 * pg201-zynq-ultrascale-plus-processing-system.pdf (PG201 January 6, 2020), Table 2-1
 * * * * * * * * * * *
 * IRQ PL->PS
 * * * * * * * * * * *
 * 121  pl_ps_irq0[0]
 * 122  pl_ps_irq0[1]
 * 123  pl_ps_irq0[2]
 * 124  pl_ps_irq0[3]
 * 125  pl_ps_irq0[4]
 * 126  pl_ps_irq0[5]
 * 127  pl_ps_irq0[6]
 * 128  pl_ps_irq0[7]
 * * * * * * * * * * *
 * IRQ PS->PL
 * * * * * * * * * * *
 * 137  pl_ps_irq1[0]
 * 138  pl_ps_irq1[1]
 * 139  pl_ps_irq1[2]
 * 140  pl_ps_irq1[3]
 * 141  pl_ps_irq1[4]
 * 142  pl_ps_irq1[5]
 * 143  pl_ps_irq1[6]
 * 144  pl_ps_irq1[7]
 * * * * * * * * * * *
 * The IRQ Number in the devicetree
 * is determined as follows:
 * for pl_ps_irq_0: IRQ_devicetree = IRQ - 32
 * for pl_ps_irq_1: IRQ_devicetree = IRQ - 33
 */

#define USE_GEM0	1
#define USE_GEM1	0
#define ENCLUSTRA	0
#define SPI_ENABLED	1
#define SPI_PINCTRL	0


/ {
	model = "Enclustra XU8 SOM";
	compatible = "xlnx,zynqmp";

	aliases {
#if USE_GEM0
		ethernet0 = &gem0;
#endif
#if USE_GEM1
		ethernet1 = &gem1;
#endif
		gpio0 = &gpio;
		i2c0 = &i2c0;
		mmc0 = &sdhci1;
		//mmc1 = &sdhci0;
		rtc0 = &rtc;
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &dcc;
#if 0
		spi0 = &spi0;
		spi1 = &spi1;
#else
		spi1 = &spi0;
		spi2 = &spi1;
		spi0 = &qspi;
#endif
		usb0 = &usb0;
		//usb1 = &usb1;
	};

	cpus {
		/delete-node/ cpu@2;
		/delete-node/ cpu@3;
	};

	chosen {
		bootargs = "console=ttyPS0,115200n8 earlycon clk_ignore_unused cpuidle.off=1";
		stdout-path = "serial0:115200n8";
	};

	memory {
		device_type = "memory";
		//reg = <0x0 0x0 0x0 0x80000000>;
		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
	};
/*
	clocks {
		osc1g: clock {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency  = <1000000000>;
			clock-output-names = "clkin";
		};

		mult12clk: multiplier {
			compatible = "fixed-factor-clock";
			clocks = <&osc1g>;
			#clock-cells = <0>;
			div = <1>;
			mult = <12>;
		};
	};
*/
#if USE_GEM0
#if ENCLUSTRA
	mdio0 {
		compatible = "cdns,macb-mdio";
		reg = <0x0 0xff0b0000 0x0 0x1000>;
		clocks =  <&zynqmp_clk 45>, <&zynqmp_clk 45>, <&zynqmp_clk 49>;
		clock-names = "pclk", "tx_clk", "hclk";
		#address-cells = <1>;
		#size-cells = <0>;
		phy0: ethernet-phy@3 {
			reg = <3>;
			txc-skew-ps = <1800>;
			txen-skew-ps = <420>;
			txd0-skew-ps = <420>;
			txd1-skew-ps = <420>;
			txd2-skew-ps = <420>;
			txd3-skew-ps = <420>;
			rxc-skew-ps = <900>;
			rxdv-skew-ps = <420>;
			rxd0-skew-ps = <420>;
			rxd1-skew-ps = <420>;
			rxd2-skew-ps = <420>;
			rxd3-skew-ps = <420>;
		};
	};
#endif
#endif

#if USE_GEM1
	mdio1 {
		compatible = "cdns,macb-mdio";
		reg = <0x0 0xff0c0000 0x0 0x1000>;
		clocks =  <&zynqmp_clk 45>, <&zynqmp_clk 45>, <&zynqmp_clk 49>;
		clock-names = "pclk", "tx_clk", "hclk";
		#address-cells = <1>;
		#size-cells = <0>;
		phy1: ethernet-phy@3 {
			reg = <3>;
			txc-skew-ps = <1800>;
			txen-skew-ps = <420>;
			txd0-skew-ps = <420>;
			txd1-skew-ps = <420>;
			txd2-skew-ps = <420>;
			txd3-skew-ps = <420>;
			rxc-skew-ps = <1860>;
			rxdv-skew-ps = <420>;
			rxd0-skew-ps = <0>;
			rxd1-skew-ps = <0>;
			rxd2-skew-ps = <0>;
			rxd3-skew-ps = <0>;
		};
	};
#endif

	regulator_vref: fixedregulator@0 {
		compatible = "regulator-fixed";
		regulator-name = "VREF";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};
};

&fclk0 {
	status = "okay";
};

&fclk1 {
	status = "okay";
};

&dcc {
	status = "okay";
};

&fpd_dma_chan1 {
	status = "okay";
};

&fpd_dma_chan2 {
	status = "okay";
};

&fpd_dma_chan3 {
	status = "okay";
};

&fpd_dma_chan4 {
	status = "okay";
};

&fpd_dma_chan5 {
	status = "okay";
};

&fpd_dma_chan6 {
	status = "okay";
};

&fpd_dma_chan7 {
	status = "okay";
};

&fpd_dma_chan8 {
	status = "okay";
};

#if USE_GEM0
#if ENCLUSTRA
&gem0 {
	status = "okay";
	local-mac-address = [00 0a 35 00 02 90];
	phy = <&phy0>;
	phy-mode = "rgmii-id";
	phy-handle = <&phy0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gem0_default>;
};
#else
&gem0 {
	status = "okay";
	phy-handle = <&phy0>;
	phy-mode = "rgmii-id";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gem0_default>;
	phy0: phy@3 {
		reg = <3>;
		txc-skew-ps = <1800>;
		txen-skew-ps = <420>;
		txd0-skew-ps = <420>;
		txd1-skew-ps = <420>;
		txd2-skew-ps = <420>;
		txd3-skew-ps = <420>;
		rxc-skew-ps = <900>;
		rxdv-skew-ps = <420>;
		rxd0-skew-ps = <420>;
		rxd1-skew-ps = <420>;
		rxd2-skew-ps = <420>;
		rxd3-skew-ps = <420>;
	};
};
#endif
#endif

#if USE_GEM1
&gem1 {
	status = "okay";
	local-mac-address = [00 0a 35 00 02 91];
	phy = <&phy1>;
	phy-mode = "gmii-id";
	phy-handle = <&phy1>;
	pinctrl-names = "default";
};
#endif

/ {
	fpga_axi: fpga-axi@0 {
		interrupt-parent = <&gic>;
		compatible = "simple-bus";
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges = <0 0 0 0xffffffff>;


		tx_dma: tx-dmac@9c420000 {
			#dma-cells = <1>;
			compatible = "adi,axi-dmac-1.00.a";
			reg = <0x9c420000 0x10000>;
			interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&zynqmp_clk 71>;

			adi,channels {
				#size-cells = <0>;
				#address-cells = <1>;

				dma-channel@0 {
					reg = <0>;
					adi,source-bus-width = <128>;
					adi,source-bus-type = <0>;
					adi,destination-bus-width = <256>;
					adi,destination-bus-type = <1>;
					adi,cyclic;
				};
			};
		};

		axi_ad9173_core: axi-ad9173-hpc@84a04000 {
			compatible = "adi,axi-ad9173-1.0";
			reg = <0x84a04000 0x10000>;
			dmas = <&tx_dma 0>;
			dma-names = "tx";
			spibus-connected = <&dac0_ad9173>;
			adi,axi-pl-fifo-enable;
		};

		axi_ad9173_jesd: axi-jesd204-tx@84a90000 {
			compatible = "adi,axi-jesd204-tx-1.0";
			reg = <0x84a90000 0x4000>;

			interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&zynqmp_clk 71>, <&axi_ad9173_adxcvr 1>, <&axi_ad9173_adxcvr 0>;
			clock-names = "s_axi_aclk", "device_clk", "lane_clk";

			adi,octets-per-frame = <1>;
			adi,frames-per-multiframe = <32>;
			adi,converter-resolution = <16>;
			adi,bits-per-sample = <16>;
			adi,converters-per-device = <4>;

			#clock-cells = <0>;
			clock-output-names = "jesd_dac_lane_clk";
		};

		axi_ad9173_adxcvr: axi-adxcvr-tx@84a60000 {
			compatible = "adi,axi-adxcvr-1.0";
			reg = <0x84a60000 0x1000>;

			clocks = <&ltc6952 8>;
			clock-names = "conv";

			adi,sys-clk-select = <XCVR_QPLL>;
			adi,out-clk-select = <XCVR_REFCLK>;
			adi,use-lpm-enable;

			#clock-cells = <1>;
			clock-output-names = "dac_gt_clk", "tx_out_clk";
		};

		axi_sysid_0: axi-sysid-0@85000000 {
			compatible = "adi,axi-sysid-1.00.a";
			reg = <0x85000000 0x10000>;
		};

	};

};


&i2c0 {
	status = "okay";
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c0_default>;
	pinctrl-1 = <&pinctrl_i2c0_gpio>;
	scl-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
	sda-gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;

	/*
	eeprom@50 {
		compatible = "at24,24c02";
		reg = <0x50>;
	};

	eeprom@54 {
		compatible = "at24,24c02";
		reg = <0x54>;
	};

	ad7291@2f {
		compatible = "adi,ad7291";
		reg = <0x2f>;
	};
	*/

};

&pinctrl0 {
	status = "okay";

	pinctrl_i2c0_default: i2c0-default {
		mux {
			groups = "i2c0_2_grp";
			function = "i2c0";
		};

		conf {
			groups = "i2c0_2_grp";
			bias-pull-up;
			slew-rate = <SLEW_RATE_SLOW>;
			io-standard = <IO_STANDARD_LVCMOS18>;
		};
	};

	pinctrl_i2c0_gpio: i2c0-gpio {
		mux {
			groups = "gpio0_10_grp", "gpio0_11_grp";
			function = "gpio0";
		};

		conf {
			groups = "gpio0_10_grp", "gpio0_11_grp";
			slew-rate = <SLEW_RATE_SLOW>;
			io-standard = <IO_STANDARD_LVCMOS18>;
		};
	};

	pinctrl_uart0_default: uart0-default {
		mux {
			groups = "uart0_9_grp";
			function = "uart0";
		};

		conf {
			groups = "uart0_9_grp";
			slew-rate = <SLEW_RATE_SLOW>;
			io-standard = <IO_STANDARD_LVCMOS18>;
		};

		conf-rx {
			pins = "MIO38";
			bias-high-impedance;
		};

		conf-tx {
			pins = "MIO39";
			bias-disable;
		};
	};

	pinctrl_usb0_default: usb0-default {
		mux {
			groups = "usb0_0_grp";
			function = "usb0";
		};

		conf {
			groups = "usb0_0_grp";
			slew-rate = <SLEW_RATE_SLOW>;
			io-standard = <IO_STANDARD_LVCMOS18>;
		};

		conf-rx {
			pins = "MIO52", "MIO53", "MIO55";
			bias-high-impedance;
		};

		conf-tx {
			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
				   "MIO60", "MIO61", "MIO62", "MIO63";
			bias-disable;
		};
	};

#if USE_GEM0
#if ENCLUSTRA
	pinctrl_gem0_default: gem0-default {
		mux {
			function = "ethernet0";
			groups = "ethernet0_0_grp";
		};

		conf {
			groups = "ethernet0_0_grp";
			slew-rate = <SLEW_RATE_SLOW>;
			io-standard = <IO_STANDARD_LVCMOS18>;
		};

		conf-rx {
			pins = "MIO32", "MIO33", "MIO34", "MIO35", "MIO36", "MIO37";
			bias-high-impedance;
			low-power-disable;
		};

		conf-tx {
			pins = "MIO26", "MIO27", "MIO28", "MIO29", "MIO30", "MIO31";
			bias-disable;
			low-power-enable;
		};
	};
#else
	pinctrl_gem0_default: gem0-default {
		mux {
			function = "ethernet0";
			groups = "ethernet0_0_grp";
		};

		conf {
			groups = "ethernet0_0_grp";
			slew-rate = <SLEW_RATE_SLOW>;
			io-standard = <IO_STANDARD_LVCMOS18>;
		};

		conf-rx {
			pins = "MIO32", "MIO33", "MIO34", "MIO35", "MIO36", "MIO37";
			bias-high-impedance;
			low-power-disable;
		};

		conf-tx {
			pins = "MIO26", "MIO27", "MIO28", "MIO29", "MIO30", "MIO31";
			bias-disable;
			low-power-enable;
		};

		mux-mdio {
			function = "mdio0";
			groups = "mdio0_0_grp";
		};

		conf-mdio {
			groups = "mdio0_0_grp";
			slew-rate = <SLEW_RATE_SLOW>;
			io-standard = <IO_STANDARD_LVCMOS18>;
			bias-disable;
		};
	};
#endif
#endif

	pinctrl_sdhci0_default: sdhci0-default {
		mux {
			groups = "sdio0_0_grp";
			function = "sdio0";
		};

		conf {
			groups = "sdio0_0_grp";
			slew-rate = <SLEW_RATE_SLOW>;
			io-standard = <IO_STANDARD_LVCMOS18>;
			bias-disable;
		};
	};

	pinctrl_sdhci1_default: sdhci1-default {
		mux {
			groups = "sdio1_11_grp";
			function = "sdio1";
		};

		conf {
			groups = "sdio1_11_grp";
			slew-rate = <SLEW_RATE_SLOW>;
			io-standard = <IO_STANDARD_LVCMOS18>;
			bias-disable;
		};

		mux-cd {
			groups = "sdio1_cd_0_grp";
			function = "sdio1_cd";
		};

		conf-cd {
			groups = "sdio1_cd_0_grp";
			bias-high-impedance;
			bias-pull-up;
			slew-rate = <SLEW_RATE_SLOW>;
			io-standard = <IO_STANDARD_LVCMOS18>;
		};

	};

#if SPI_PINCTRL
	pinctrl_spi0_default: spi0-default {
		mux {
			groups = "spi0_0_grp";
			function = "spi0";
		};

		conf {
			groups = "spi0_0_grp";
			bias-disable;
			slew-rate = <SLEW_RATE_SLOW>;
			io-standard = <IO_STANDARD_LVCMOS18>;
		};

		mux-cs {
			groups = "spi0_ss_0_grp", "spi0_ss_1_grp",
							"spi0_ss_2_grp";
			function = "spi0_ss";
		};

		conf-cs {
			groups = "spi0_ss_0_grp", "spi0_ss_1_grp",
							"spi0_ss_2_grp";
			bias-disable;
		};
	};

	pinctrl_spi1_default: spi1-default {
		mux {
			groups = "spi1_3_grp";
			function = "spi1";
		};

		conf {
			groups = "spi1_3_grp";
			bias-disable;
			slew-rate = <SLEW_RATE_SLOW>;
			io-standard = <IO_STANDARD_LVCMOS18>;
		};

		mux-cs {
			groups = "spi1_ss_9_grp", "spi1_ss_10_grp",
							"spi1_ss_11_grp";
			function = "spi1_ss";
		};

		conf-cs {
			groups = "spi1_ss_9_grp", "spi1_ss_10_grp",
							"spi1_ss_11_grp";
			bias-disable;
		};
	};
#endif
};

&qspi {
	status = "okay";
	is-dual = <0>;
};

&rtc {
	status = "okay";
};

&sdhci1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sdhci1_default>;
	no-1-8-v;	/* for 1.0 silicon */
	wp-inverted;
	xlnx,mio_bank = <1>;
};

&sdhci0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sdhci0_default>;
	non-removable;
	disable-wp;
	xlnx,mio_bank = <0>;
};

&serdes {
	status = "okay";
};

&uart0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart0_default>;
};

/* ULPI SMSC USB3320 */
&usb0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb0_default>;
};

#if SPI_ENABLED
&spi0 {
	is-decoded-cs = <1>;
	num-cs = <8>;
	status = "okay";
#if SPI_PINCTRL
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi0_default>;
#endif
ltc6952: ltc6952@0 {
       compatible = "adi,ltc6952";
       reg = <0>;
       #address-cells = <1>;
       #size-cells = <0>;
       spi-max-frequency = <10000>;
       clock-output-names = "ltc6952_out0", "ltc6952_out1", "ltc6952_out2",
         "ltc6952_out3", "ltc6952_out4", "ltc6952_out5", "ltc6952_out6",
         "ltc6952_out7", "ltc6952_out8", "ltc6952_out9", "ltc6952_out10";
       #clock-cells = <1>;
       adi,vco-frequency-hz = <1000000000>;
       adi,ref-frequency-hz = <100000000>;
			 adi,charge-pump-microamp = <8020>;
       ltc6952_c0: channel@0 {
         reg = <0>;
         adi,extended-name = "DAC_SYSREF";
         adi,divider = <200>;
         adi,digital-delay = <100>;
         adi,analog-delay = <0>;
       };
       ltc6952_c1: channel@1 {
         reg = <1>;
         adi,extended-name = "CLK_ADC4";
         adi,divider = <2>;
				 adi,digital-delay = <100>;
         adi,analog-delay = <0>;
       };
			 ltc6952_c2: channel@2 {
         reg = <2>;
         adi,extended-name = "CLK_ADC3";
         adi,divider = <2>;
				 adi,digital-delay = <100>;
         adi,analog-delay = <0>;
       };
			 ltc6952_c3: channel@3 {
         reg = <3>;
         adi,extended-name = "CLK_ADC2";
         adi,divider = <2>;
				 adi,digital-delay = <100>;
         adi,analog-delay = <0>;
       };
			 ltc6952_c4: channel@4 {
         reg = <4>;
         adi,extended-name = "CLK_ADC1";
         adi,divider = <2>;
				 adi,digital-delay = <100>;
         adi,analog-delay = <0>;
       };
			 ltc6952_c5: channel@5 {
         reg = <5>;
         adi,extended-name = "FPGA_SYSREF";
         adi,divider = <200>;
				 adi,digital-delay = <100>;
         adi,analog-delay = <0>;
       };
			 ltc6952_c6: channel@6 {
         reg = <6>;
         adi,extended-name = "SYSREF_ADC_1-4";
         adi,divider = <200>;
				 adi,digital-delay = <100>;
         adi,analog-delay = <0>;
       };
			 ltc6952_c7: channel@7 {
         reg = <7>;
         adi,extended-name = "RefCLK_ADC";
         adi,divider = <2>;
				 adi,digital-delay = <100>;
         adi,analog-delay = <0>;
       };
			 ltc6952_c8: channel@8 {
         reg = <8>;
         adi,extended-name = "RefCLK_DAC";
         adi,divider = <2>;
				 adi,digital-delay = <100>;
         adi,analog-delay = <0>;
       };
			 ltc6952_c9: channel@9 {
         reg = <9>;
         adi,extended-name = "AUX_CLKout";
         adi,divider = <10>;
				 adi,digital-delay = <100>;
         adi,analog-delay = <0>;
       };
			 ltc6952_c10: channel@10 {
         reg = <10>;
         adi,extended-name = "CLKout";
         adi,divider = <2>;
				 adi,digital-delay = <100>;
         adi,analog-delay = <0>;
       };
     };

		 lo1_synth: hmc703@1 {
	 		#address-cells = <1>;
	 		#size-cells = <0>;
	 		compatible = "hmc703";
	 		reg = <1>;
	 		spi-max-frequency = <100000>;
	 		optional,unique-id = "hmc703";
	 		optional,CP-Current = <127>;
	 		optional,N-DIV-VCO = <20>;
	 		optional,R-DIV-REF = <2>;
	 	};

		ad5680: ad5680@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "ad5680";
			reg = <2>;
			spi-cpol;
			spi-max-frequency = <100000>;
		};

};

#define fmc_spi spi0



&spi1 {
	is-decoded-cs = <1>;
	num-cs = <8>;
	status = "okay";



	dac0_ad9173: ad9173@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "adi,ad9173";
		reg = <0>;
		spi-max-frequency = <1000000>;
		clocks = <&axi_ad9173_jesd>, <&ltc6952 0>, <&ltc6952 0>; //mult12clk
		clock-names = "jesd_dac_clk", "dac_clk", "dac_sysref";

		adi,dac-rate-khz = <12000000>;
		adi,jesd-link-mode = <8>;
		adi,jesd-dual-link-mode = <1>;

		adi,jesd-subclass = <0>;
		adi,dac-interpolation = <12>;
		adi,channel-interpolation = <1>;
		adi,clock-output-divider = <1>;
		adi,syncoutb-signal-type-lvds-enable;
		//adi,logic-lanes-mapping = [00 01 02 03 04 05 06 07];

	};

 };

#endif

/* enable SYSMON */
&xilinx_ams {
	status = "okay";
};

/* SYSMON (PS) */
&ams_ps {
	status = "okay";
};

/* SYSMON (PL) */
&ams_pl {
	status = "okay";
};

&gpio {
	status = "okay";
};

// #include "adi-daq2.dtsi"

//&adc0_ad9680 {
//	powerdown-gpios = <&gpio 120 0>; /* 42 + 78 */
//	fastdetect-a-gpios = <&gpio 113 0>; /* 35 */
//	fastdetect-b-gpios = <&gpio 114 0>; /* 36 */
//};

//&dac0_ad9144 {
//	txen-gpios = <&gpio 119 0>; /* 41 */
//	reset-gpios = <&gpio 118 0>; /* 40 */
//	irq-gpios = <&gpio 112 0>; /* 34 */
//};

//&clk0_ad9523 {
//	sync-gpios = <&gpio 116 0>; /* 38 */
//	status0-gpios = <&gpio 110 0>; /* 32 */
//	status1-gpios = <&gpio 111 0>; /* 33 */
//};

  • Hi Andreas,

    I'll let people smarter than me answer your question about JESD.

    About your 12 GHz clock - it looks like it is not possible to specify it in Device Tree, as you noticed. I'll see if I can come up with a patch that adds support for 64-bit in "assigned-clock-rates" and send it to the upstream developers.

    -Paul

  • Also it gives an error in the ad9172.c in the function clk_prepare_enable(st->conv.clk[CLK_DATA]);, so I have commented it out.

    If you do that things will never work.

    This clock controls the QPLL rate and ultimately turns it on. 

    The clock comes via the TX link layer core, but is provided by the adxcvr driver.

    When the lane rate is computed does it use 4 or 8 lanes?

    Can you read and post clk_summary?

    root@analog:~# cat /sys/kernel/debug/clk/clk_summary

    -Michael
     

  • Hi Michael

    Here the clock summary

    The 12GHz DAC clock is taken from the 12x multipliers connected to the 1GHz external vco from the LTC6952.

    I have measured all clocks on the board and they are ok.

    Andreas

    root@analog:~# cat /sys/kernel/debug/clk/clk_summary
                                     enable  prepare  protect                                duty
       clock                          count    count    count        rate   accuracy phase  cycle
    ---------------------------------------------------------------------------------------------
     ltc6952_out10                        0        0        0   500000000          0     0  50000
     ltc6952_out9                         0        0        0   100000000          0     0  50000
     ltc6952_out8                         1        1        0   500000000          0     0  50000
        tx_out_clk                        0        0        0   500000000          0     0  50000
        dac_gt_clk                        0        0        0    10000000          0     0  50000
           jesd_dac_lane_clk              0        0        0    10000000          0     0  50000
     ltc6952_out7                         0        0        0   500000000          0     0  50000
     ltc6952_out6                         0        0        0     5000000          0     0  50000
     ltc6952_out5                         0        0        0     5000000          0     0  50000
     ltc6952_out4                         0        0        0   500000000          0     0  50000
     ltc6952_out3                         0        0        0   500000000          0     0  50000
     ltc6952_out2                         0        0        0   500000000          0     0  50000
     ltc6952_out1                         0        0        0   500000000          0     0  50000
     ltc6952_out0                         2        2        0     5000000          0     0  50000
     dp_aclk                              0        0        0   100000000        100     0  50000
     aux_ref_clk                          0        0        0    27000000          0     0  50000
     gt_crx_ref_clk                       0        0        0   108000000          0     0  50000
     pss_alt_ref_clk                      0        0        0           0          0     0  50000
     video_clk                            0        0        0    27000000          0     0  50000
     pss_ref_clk                          2        2        2    33333333          0     0  50000
        vpll_post_src                     0        0        0    33333333          0     0  50000
        vpll_pre_src                      0        0        0    33333333          0     0  50000
           vpll_int                       0        0        0  2133333312          0     0  50000
              vpll_half                   0        0        0  1066666656          0     0  50000
                 vpll_int_mux             0        0        0  1066666656          0     0  50000
                    vpll                  0        0        0  1066666656          0     0  50000
                       dp_stc_ref_mux       0        0        0  1066666656          0     0  50000
                          dp_stc_ref_div1       0        0        0    21333334          0     0  50000
                             dp_stc_ref_div2       0        0        0      666667          0     0  50000
                                dp_stc_ref       0        0        0      666667          0     0  50000
                       dp_audio_ref_mux       0        0        0  1066666656          0     0  50000
                          dp_audio_ref_div1       0        0        0    30476191          0     0  50000
                             dp_audio_ref_div2       0        0        0    10158731          0     0  50000
                                dp_audio_ref       0        0        0    10158731          0     0  50000
                       vpll_to_lpd        0        0        0   533333328          0     0  50000
        dpll_post_src                     0        0        0    33333333          0     0  50000
        dpll_pre_src                      0        0        0    33333333          0     0  50000
           dpll_int                       0        0        0  2399999976          0     0  50000
              dpll_half                   0        0        0  1199999988          0     0  50000
                 dpll_int_mux             0        0        0  1199999988          0     0  50000
                    dpll                  0        0        0  1199999988          0     0  50000
                       gpu_ref_mux        0        0        0  1199999988          0     0  50000
                          gpu_ref_div1       0        0        0   239999998          0     0  50000
                             gpu_ref       0        0        0   239999998          0     0  50000
                                gpu_pp1_ref       0        0        0   239999998          0     0  50000
                                gpu_pp0_ref       0        0        0   239999998          0     0  50000
                       pcie_ref_mux       0        0        0  1199999988          0     0  50000
                          pcie_ref_div1       0        0        0    99999999          0     0  50000
                             pcie_ref       0        0        0    99999999          0     0  50000
                       sata_ref_mux       0        0        0  1199999988          0     0  50000
                          sata_ref_div1       0        0        0    99999999          0     0  50000
                             sata_ref       0        0        0    99999999          0     0  50000
                       dpdma_ref_mux       0        0        0  1199999988          0     0  50000
                          dpdma_ref_div1       0        0        0   599999994          0     0  50000
                             dpdma_ref       0        0        0   599999994          0     0  50000
                       gdma_ref_mux       0        0        0  1199999988          0     0  50000
                          gdma_ref_div1       0        0        0   599999994          0     0  50000
                             gdma_ref       0        0        0   599999994          0     0  50000
                       dp_video_ref_mux       0        0        0  1199999988          0     0  50000
                          dp_video_ref_div1       0        0        0   119999999          0     0  50000
                             dp_video_ref_div2       0        0        0   119999999          0     0  50000
                                dp_video_ref       0        0        0   119999999          0     0  50000
                       dpll_to_lpd        0        0        0   399999996          0     0  50000
        apll_post_src                     0        0        0    33333333          0     0  50000
        apll_pre_src                      0        0        0    33333333          0     0  50000
           apll_int                       0        0        0  2399999976          0     0  50000
              apll_half                   0        0        0  1199999988          0     0  50000
                 apll_int_mux             0        0        0  1199999988          0     0  50000
                    apll                  0        0        0  1199999988          0     0  50000
                       acpu_mux           0        0        0  1199999988          0     0  50000
                          acpu            0        0        0  1199999988          0     0  50000
        rpll_post_src                     0        0        0    33333333          0     0  50000
        rpll_pre_src                      1        1        1    33333333          0     0  50000
           rpll_int                       1        1        1  1999999980          0     0  50000
              rpll_half                   1        1        1   999999990          0     0  50000
                 rpll_int_mux             1        1        1   999999990          0     0  50000
                    rpll                  2        2        2   999999990          0     0  50000
                       spi1_ref_mux       0        0        0   999999990          0     0  50000
                          spi1_ref_div1       0        0        0    99999999          0     0  50000
                             spi1_ref_div2       0        0        0    99999999          0     0  50000
                                spi1_ref       0        0        0    99999999          0     0  50000
                       spi0_ref_mux       0        0        0   999999990          0     0  50000
                          spi0_ref_div1       0        0        0    99999999          0     0  50000
                             spi0_ref_div2       0        0        0    99999999          0     0  50000
                                spi0_ref       0        0        0    99999999          0     0  50000
                       sdio1_ref_mux       1        1        1   999999990          0     0  50000
                          sdio1_ref_div1       1        1        1    50000000          0     0  50000
                             sdio1_ref_div2       1        1        1    50000000          0     0  50000
                                sdio1_ref       1        1        1    50000000          0     0  50000
                       sdio0_ref_mux       1        1        1   999999990          0     0  50000
                          sdio0_ref_div1       1        1        1   199999998          0     0  50000
                             sdio0_ref_div2       1        1        1   199999998          0     0  50000
                                sdio0_ref       1        1        1   199999998          0     0  50000
                       rpll_to_fpd        0        0        0   499999995          0     0  50000
        iopll_post_src                    0        0        0    33333333          0     0  50000
        iopll_pre_src                     1        1        1    33333333          0     0  50000
           iopll_int                      1        1        1  2999999970          0     0  50000
              iopll_half                  1        1        1  1499999985          0     0  50000
                 iopll_int_mux            1        1        1  1499999985          0     0  50000
                    iopll                12       14        7  1499999985          0     0  50000
                       gem3_ref_ung_mux       0        0        0  1499999985          0     0  50000
                          gem3_ref_ung_div1       0        0        0    62500000          0     0  50000
                             gem3_ref_ung       0        0        0    62500000          0     0  50000
                                gem3_ref       0        0        0    62500000          0     0  50000
                                   gem3_tx       0        0        0    62500000          0     0  50000
                       gem2_ref_ung_mux       0        0        0  1499999985          0     0  50000
                          gem2_ref_ung_div1       0        0        0    62500000          0     0  50000
                             gem2_ref_ung       0        0        0    62500000          0     0  50000
                                gem2_ref       0        0        0    62500000          0     0  50000
                                   gem2_tx       0        0        0    62500000          0     0  50000
                       gem1_ref_ung_mux       0        0        0  1499999985          0     0  50000
                          gem1_ref_ung_div1       0        0        0    62500000          0     0  50000
                             gem1_ref_ung       0        0        0    62500000          0     0  50000
                                gem1_ref       0        0        0    62500000          0     0  50000
                                   gem1_tx       0        0        0    62500000          0     0  50000
                       gem0_ref_ung_mux       1        1        0  1499999985          0     0  50000
                          gem0_ref_ung_div1       1        1        0   124999999          0     0  50000
                             gem0_ref_ung       1        1        0   124999999          0     0  50000
                                gem0_ref       2        2        0   124999999          0     0  50000
                                   gem0_tx       1        1        0   124999999          0     0  50000
                       pl3_ref_mux        1        1        0  1499999985          0     0  50000
                          pl3_ref_div1       1        1        0    46875000          0     0  50000
                             pl3_ref_div2       1        1        0     9375000          0     0  50000
                                pl3_ref       1        1        0     9375000          0     0  50000
                       pl2_ref_mux        1        1        0  1499999985          0     0  50000
                          pl2_ref_div1       1        1        0   499999995          0     0  50000
                             pl2_ref_div2       1        1        0   499999995          0     0  50000
                                pl2_ref       1        1        0   499999995          0     0  50000
                       pl1_ref_mux        1        1        0  1499999985          0     0  50000
                          pl1_ref_div1       1        1        0   249999998          0     0  50000
                             pl1_ref_div2       1        1        0   249999998          0     0  50000
                                pl1_ref       1        1        0   249999998          0     0  50000
                       pl0_ref_mux        1        1        0  1499999985          0     0  50000
                          pl0_ref_div1       1        1        0    99999999          0     0  50000
                             pl0_ref_div2       1        1        0    99999999          0     0  50000
                                pl0_ref       3        3        0    99999999          0     0  50000
                       ams_ref_mux        1        1        1  1499999985          0     0  50000
                          ams_ref_div1       1        1        1    51724138          0     0  50000
                             ams_ref_div2       1        1        1    51724138          0     0  50000
                                ams_ref       1        1        1    51724138          0     0  50000
                       adma_ref_mux       0        0        0  1499999985          0     0  50000
                          adma_ref_div1       0        0        0   499999995          0     0  50000
                             adma_ref       0        0        0   499999995          0     0  50000
                       can1_ref_mux       0        0        0  1499999985          0     0  50000
                          can1_ref_div1       0        0        0    46875000          0     0  50000
                             can1_ref_div2       0        0        0    46875000          0     0  50000
                                can1_ref       0        0        0    46875000          0     0  50000
                                   can1       0        0        0    46875000          0     0  50000
                       can0_ref_mux       0        0        0  1499999985          0     0  50000
                          can0_ref_div1       0        0        0    46875000          0     0  50000
                             can0_ref_div2       0        0        0    46875000          0     0  50000
                                can0_ref       0        0        0    46875000          0     0  50000
                                   can0       0        0        0    46875000          0     0  50000
                       i2c1_ref_mux       0        0        0  1499999985          0     0  50000
                          i2c1_ref_div1       0        0        0   299999997          0     0  50000
                             i2c1_ref_div2       0        0        0   299999997          0     0  50000
                                i2c1_ref       0        0        0   299999997          0     0  50000
                       i2c0_ref_mux       0        1        1  1499999985          0     0  50000
                          i2c0_ref_div1       0        1        1    99999999          0     0  50000
                             i2c0_ref_div2       0        1        1    99999999          0     0  50000
                                i2c0_ref       0        1        1    99999999          0     0  50000
                       nand_ref_mux       0        0        0  1499999985          0     0  50000
                          nand_ref_div1       0        0        0    46875000          0     0  50000
                             nand_ref_div2       0        0        0     9375000          0     0  50000
                                nand_ref       0        0        0     9375000          0     0  50000
                       uart1_ref_mux       0        0        0  1499999985          0     0  50000
                          uart1_ref_div1       0        0        0    62500000          0     0  50000
                             uart1_ref_div2       0        0        0    62500000          0     0  50000
                                uart1_ref       0        0        0    62500000          0     0  50000
                       uart0_ref_mux       1        1        1  1499999985          0     0  50000
                          uart0_ref_div1       1        1        1    99999999          0     0  50000
                             uart0_ref_div2       1        1        1    99999999          0     0  50000
                                uart0_ref       1        1        1    99999999          0     0  50000
                       qspi_ref_mux       0        1        1  1499999985          0     0  50000
                          qspi_ref_div1       0        1        1    50000000          0     0  50000
                             qspi_ref_div2       0        1        1    50000000          0     0  50000
                                qspi_ref       0        1        1    50000000          0     0  50000
                       gem_tsu_ref_mux       1        1        1  1499999985          0     0  50000
                          gem_tsu_ref_div1       1        1        1   249999998          0     0  50000
                             gem_tsu_ref_div2       1        1        1   249999998          0     0  50000
                                gem_tsu_ref       1        1        1   249999998          0     0  50000
                                   gem_tsu       1        1        0   249999998          0     0  50000
                       usb3_dual_ref_mux       1        1        1  1499999985          0     0  50000
                          usb3_dual_ref_div1       1        1        1    60000000          0     0  50000
                             usb3_dual_ref_div2       1        1        1    20000000          0     0  50000
                                usb3_dual_ref       1        1        1    20000000          0     0  50000
                       usb1_bus_ref_mux       0        0        0  1499999985          0     0  50000
                          usb1_bus_ref_div1       0        0        0   124999999          0     0  50000
                             usb1_bus_ref_div2       0        0        0   124999999          0     0  50000
                                usb1_bus_ref       0        0        0   124999999          0     0  50000
                       usb0_bus_ref_mux       1        1        1  1499999985          0     0  50000
                          usb0_bus_ref_div1       1        1        1   249999998          0     0  50000
                             usb0_bus_ref_div2       1        1        1   249999998          0     0  50000
                                usb0_bus_ref       1        1        1   249999998          0     0  50000
                       lpd_lsbus_mux       1        1        0  1499999985          0     0  50000
                          lpd_lsbus_div1       1        1        0    99999999          0     0  50000
                             lpd_lsbus       7        8        0    99999999          0     0  50000
                                lpd_wdt       0        0        0    99999999          0     0  50000
                       iopll_to_fpd       1        1        0   499999995          0     0  50000
                          topsw_lsbus_mux       1        1        0   499999995          0     0  50000
                             topsw_lsbus_div1       1        1        0    99999999          0     0  50000
                                topsw_lsbus       2        2        0    99999999          0     0  50000
                                   fpd_wdt       0        0        0    99999999          0     0  50000
     can1_mio                             0        0        0           0          0     0  50000
     can0_mio                             0        0        0           0          0     0  50000
     gem3_rx                              0        0        0           0          0     0  50000
     gem2_rx                              0        0        0           0          0     0  50000
     gem1_rx                              0        0        0           0          0     0  50000
     gem0_rx                              1        1        0           0          0     0  50000
    root@analog:~#

  • What is the error (ret) your getting from:

    ret = clk_prepare_enable(st->conv.clk[CLK_DATA]);

    -Michael

  • The tx_out_clk looks too high,   it should be 250MHz.    You can do that by setting the  ltc6952_out to 250MHz or by selecting DIV2 for         adi,out-clk-select = <XCVR_REFCLK_DIV2>;

    Laszlo