ssm2518 When pa chip plays, the speaker is silent

Question 1:

We use the 3.072MHz BCLK that is 48KHz sampling rate\ ch 2 \ 32bit. When pa chip plays, the speaker is silent. 

This is our register values when pa plays, please help us double check, thanks.

# i2cdump -f -y 1 0x34
0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: 00 01 02 00 10 40 40 80 0c 98 7c 5b 57 89 8c 77 .??.?@@???|[W??w
10: 26 1c 07 00 00 00 10 00 00 00 00 00 00 00 00 00 &??...?.........
20: 00 01 02 00 10 40 40 80 0c 98 7c 5b 57 89 8c 77 .??.?@@???|[W??w
30: 26 1c 07 00 00 00 10 00 00 00 00 00 00 00 00 00 &??...?.........
40: 00 01 02 00 10 40 40 80 0c 98 7c 5b 57 89 8c 77 .??.?@@???|[W??w
50: 26 1c 07 00 00 00 10 00 00 00 00 00 00 00 00 00 &??...?.........
60: 00 01 02 00 10 40 40 80 0c 98 7c 5b 57 89 8c 77 .??.?@@???|[W??w
70: 26 1c 07 00 00 00 10 00 00 00 00 00 00 00 00 00 &??...?.........
80: 00 01 02 00 10 40 40 80 0c 98 7c 5b 57 89 8c 77 .??.?@@???|[W??w
90: 26 1c 07 00 00 00 10 00 00 00 00 00 00 00 00 00 &??...?.........
a0: 00 01 02 00 10 40 40 80 0c 98 7c 5b 57 89 8c 77 .??.?@@???|[W??w
b0: 26 1c 07 00 00 00 10 00 00 00 00 00 00 00 00 00 &??...?.........
c0: 00 01 02 00 10 40 40 80 0c 98 7c 5b 57 89 8c 77 .??.?@@???|[W??w
d0: 26 1c 07 00 00 00 10 00 00 00 00 00 00 00 00 00 &??...?.........
e0: 00 01 02 00 10 40 40 80 0c 98 7c 5b 57 89 8c 77 .??.?@@???|[W??w
f0: 26 1c 07 00 00 00 10 00 00 00 00 00 00 00 00 00 &??...?.........

Question 2:

Whether ssm2518 can support 1.536Mhz BCLK that is 16bit ,2 ch , 48kHz.

  • 0
    •  Analog Employees 
    on Nov 18, 2021 7:59 AM

    Hi Tom,

    1. Can you please post here the output of "amixer -c 0" command from Linux to debug faster the problem. Take care if the SSM is not your only card you have to get its number with command "aplay -l" and adapt -c from amixer accordingly.

    2. SSM2518 can support 16 bit, 2ch, 48kHz with 1.536MHz BCLK but you have to also provide a 3.072MHz MCLK. SSM2518 support operation with only one clock where BCLK is derived from MCLK but in that case the provided MCLK clock must be in range 2.048 MHz to 6.144 MHz according to datasheet.

  • Thank for your support.

    1、We use "tinyplay" command that same amixer. Then the speaker is silent. The registers are shown above.

    tinyplay xxxx.wav -c 2 -r 48000 -b 16

    2、Now, we don't set the MCLK value, only use the BCLK, and connect with ssm2518 BCLK pin throuch our board pin. Does it work normally? This is our schematic, if have any suggest, plesase tell me.

    3、Register  0x03 = 0x00 , 0x00 = 0x00, we think the values are normal, but the speaker is silent, please help us check the register value, thanks.

  • +1
    •  Analog Employees 
    on Nov 19, 2021 7:39 AM in reply to Tom_lei

    According to datasheet you can configure the chip to work without BCLK and generate it internal derived from MCLK but without MCLK is not possible. If you can provide only one clock I recommend you to provide a 3.072MHz MCLK. Then also according to datasheet connect BCLK pin to DVDD if you have 16 bits/channel or BCLK to GND if you have 32 bits/channel.

    After that make sure that BCLK_GEN (Bit 7 of Register 0x03) and NO_BCLK (Bit 5 of Register 0x00) are set. Please check the code in the driver. Basically you have to call ssm2518_set_sysclk with SSM2518_POWER1_NO_BCLK.

  • Hi btogorean,

    Thank for your support. You are a hero. But maybe we have some problem according your solution.

    Beacuse our target HW design, we can not change the BCLK to GND or DVDD, so we use the BCLK.

    1、If we use the MCLK(our board only support 9.6MHz\11.289MHz\12.288MHz), the BCLK connect to our board, whether is correct?

    2、We provide MCLK 12.288MHz, 3.072MHz BCLK that is 48KHz sampling rate\ ch 2 \ 32bit. And then play, but the speaker is slient. This is our register values. Please help us double check or provide the register setting in this conditon.

    register 0x00 value 0x20

    register 0x01 value 0x01

    register 0x02 value 0x02

    register 0x03 value 0x00

    register 0x04 value 0x11

    register 0x05 value 0x40

    register 0x06 value 0x40

    register 0x07 value 0x80

    register 0x08 value 0x0c

    Details:

    BRs

    Tom

  • 0
    •  Analog Employees 
    on Nov 19, 2021 12:19 PM in reply to Tom_lei

    Hi Tom,

    1. If you provide 12.288MHz MCLK you should also connect BCLK and supply a clock with frequency between 2.048 MHz and 6.144 MHz.

    2. MCLK 12.288MHz, BCLK 3.072MHz and 2 channel at 48KHz with 32bit per channel is a valid configuration. Now let's look at the registers 

    register 0x00 should be 0x00

    register 0x04 should be 0x10

    register 0x07 you can try to set it to 0x00

    register 0x09 you can try 0x80