Post Go back to editing

ADRV9361-Z7035 Stackup Concerns

Looking into spinning a board with the ADRV9361 chip - so we're using the ADRV9361-Z7035 eval board as a reference, especially with respect to PCB stackup on the controlled RF impedances.

The fab notes in the BRD file (Film: fab2) says the following:

External layers 0.5oz - overplate to 1.5oz

Internal signal layers 1oz Copper

Internal place layers 1oz Copper

After opening the .BRD file of the Ref F layout in Allegro viewer, I'm a bit stumped by the copper thickness values inserted into the stackup table

None of these copper thicknesses make very much sense. 1.79mils, 0.93mils, 1.18mils, and 0.6mils are all non-standard copper foil thicknesses.

Not to mention that the thicknesses for the Isola Tachyon 100G don't make sense either (I can't see 3.38mil or 3.33mil thick options available from Isola's spec sheets, only 3.5mils or 3.8mils)

Is there a more up to date or accurate stackup table available for this eval board? We'd love to try to replicate the stackup on our design but this doesn't seem manufacturable.