How to enable 2 RX channel of adrv9009 base on adrv9009-iiostream.c?

On the adrv9009-ZU11EG Noticing discontinuities/saturation on the data on this set up when writing to disk vs when only one channel is enabled :( I have cma = 1024M set and also using tmpfs for optimal write speeds.

See those artifacts in the time series around 0.01s?

I'm noticing that I'm configuring the frequency for both devices ( out_altvoltage0_TRX_LO_frequency file is being updated for both adrv9009-phy and adrv9009-phy-b)

Are you setting out_altvoltage0_TRX_LO_frequency with separate iio_devices? Your code snippets do not reference these calls.

-Travis

Yes frequency is configured before these code snippets.

wanted to see if I’m enabling the channels correctly.

thanks 

Child id should be 1 not 2 for secondary RX channels.

-Travis

Im trying to enable adrv9009-phy's primary RX channel and adrv9009-phy-b's primary RX channel.

I.e. the RX1 channel for each ADC, No secondary RX channels.

Then index 0 and 2 are fine.

-Travis

Hi Trav, I'm now using adrv9009zu11EG + fmcomms8. Has the adrv9009 iio streaming been tested for this hardware? CUrrently getting "Could not create RX buffer: Cannot allocate memory" ERROR.

Notice the destination bus width in the hdl is 128Bits.

This is the dts file arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-fmcomms8.dts notice it says 256 bits for destination.

Max is 128 bits for HP

Max is 128 bits for HP