Cmos 4lane not working in ADRV9002

Hi ,

we are trying to bringup ADRV9002FMCZ using linux system and IIOSCOPE using CMOS interface

profile loading  for 1lane CMOS is working fine and we are able to get a sine wave on IIOSCOPE using DDS input through RX-TX loopback in ADRV9002.

But when we are trying to load profile for 4-Lane CMOS we are getting sine wave with distortion/glitches with same loopback configuration. we teste this with other signal like ramp nibble and getting same distortion/glitches. Also while profile loading we getting "ramp nibble", "strobe error", "data error" which we then bypassed

Also we tried to bringup with baremetal no-OS driver from ADi, in this  for both 1lane and 4lane we are not getting a correct data in either of the mode and getting "data_error"

    

Kindly guide us some solution on it or are we missing any configuration.

Also can you share link for latest HDL/ linux code branch for ADRV9002 for us to cross validate.

thanks ,

Shivashankar Thatti.

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  • 0
    •  Analog Employees 
    on Oct 13, 2021 12:11 PM

    Hello Shivashankar Thatti,

    We need to try this on our end to see if we can reproduce it...

    Also while profile loading we getting "ramp nibble", "strobe error", "data error" which we then bypassed

    What do you mean by this? When loading a profile, the board will be reseted which means it is expected that the signal breaks for sometime until everything is up and running again...

    - Nuno Sá

  • Hi,

    we found & resolved the issue. basically it was due to wrong configuration of REG_RATECNtrl register (0x04c)

    it was configured to 31 for CMOS 4lane which made 4 adc_valid signal between consecutive strb signal, as a result each data got send 4 times as a result glitch after modulation-> demodulation.

    so we then changed REG_RATECNtrl value from 31->7 now it issue are resolved as only one adc_valid signal generated between two consecutive strb signal. also we checked in noOS for 1 lane REG_RATECNtrl configured value is given as->7

    and for 4lane cmos as  ->1. so i guess that is also wrong, we corrected it and things got working.

    i think there might be these bug in code.

    regards,

    shivashankar Thatti.

  • 0
    •  Analog Employees 
    on Oct 14, 2021 1:25 PM in reply to Shivashankar

    Hi , I marked your reply as answer to your question.
    However, I'd like to know what do you mean by the last line, do you think there is a bug in ADI adrv9002 drivers that misconfigures REG_RATECNtrl ?

  • Hi ,

    the linux driver does not have any line to configure REG_RATECNtrl for Cmos 4 lane, just check which gives strb error. and also noOS driver we refer writes default some wrong value , for which its not working.

    Or maybe we might have referref a wrong or undeveloped code.

    regards,

    Shivashankar T

  • 0
    •  Analog Employees 
    on Oct 14, 2021 1:39 PM in reply to Shivashankar

    Hi,

    I'm a bit puzzled by this. Which value are you writing on 0x4c? According to the wiki, for CMOS 4 lanes SDR it has to be 1 and the driver is doing that here on the 2019_R2 branch... The value 7 is for CMOS 1 lane

    - Nuno Sá

  • Hi,

    Dont Know what exactly is the case, but things get started for us when we configured 0x4c with 7 for cmos 4lane and 31 for Cmos 1 lane. by default value was giving us error as well as above issue persisted.

    But technically what we understand 0x4c register set count clock after which a valid signal should be raised. so in that point of view 0x4c with 7 for cmos 4lane and 31 for Cmos 1 lane seems correct.

    Also we are running this on intel cyclone V FPGA.

    regards,

    Shivashankar T.

  • 0
    •  Analog Employees 
    on Oct 18, 2021 10:43 AM in reply to Shivashankar
    Also we are running this on intel cyclone V FPGA

    Ok, this explains it. IIRC, intel FPGAs support came later and only exists in the master branch. Hence, if you were using a release branch , you're expected to have issues.

    - Nuno Sá

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