Hello everyone,
I'm currently using AD40xx ADCs connected to Zedboard through the AXI SPI Engine IP by ADI. I'm also using meta-adi 2020.1 and also checked this with 2019_R2. From measurements, it seems the sampling frequency is around 900,000 samples per second as shown below. I was wondering if it is possible to increase sampling rate by software?
Channel 1 (yellow) is the CNV signal while Channel 2 (blue) is the SCK. I'm thinking of reducing CNV's high pulse duration which is about 615ns seconds here to increase the sampling rate or frequency. The minimum CNV pulse length (tCNVH) from datasheet is just 10ns, so is it possible to reduce it to like 120ns? After all, some of AD40XX ADCs like AD4020 have a sampling rate of 1.8MSPS so increasing sampling rate to more than 1MSPS should be possible to demonstrate this feature.
This is very much controlled from the AXI SPI engine HDL but I'm not very knowledgable in the details of the HDL, so I am looking at this route from the software and drivers if it is possible. I've read the SPI engine has a 16-bit instruction set from this link:
https://wiki.analog.com/resources/fpga/peripherals/spi_engine/instruction_format
There is the command for the chip-select (corresponding to the CNV signal) but the spi-axi-spiengine.c driver has already set the delay parameter to 1 which I'm not sure is the minimum. This is where I hit the dead-end. Can this be adjusted further to reduce the tCNVH pulse length?
