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Change sampling rate in AXI-SPI-Engine ADCs like AD4020

Hello everyone,

I'm currently using AD40xx ADCs connected to Zedboard through the AXI SPI Engine IP by ADI.  I'm also using meta-adi 2020.1 and also checked this with 2019_R2.  From measurements, it seems the sampling frequency is around 900,000 samples per second as shown below.  I was wondering if it is possible to increase sampling rate by software?

Channel 1 (yellow) is the CNV signal while Channel 2 (blue) is the SCK.  I'm thinking of reducing CNV's high pulse duration which is about 615ns seconds here to increase the sampling rate or frequency. The minimum CNV pulse length (tCNVH) from datasheet is just 10ns, so is it possible to reduce it to like 120ns?  After all, some of AD40XX ADCs like AD4020 have a sampling rate of 1.8MSPS so increasing sampling rate to more than 1MSPS should be possible to demonstrate this feature.

This is very much controlled from the AXI SPI engine HDL but I'm not very knowledgable in the details of the HDL, so I am looking at this route from the software and drivers if it is possible.   I've read the SPI engine has a 16-bit instruction set from this link:

There is the command for the chip-select (corresponding to the CNV signal) but the spi-axi-spiengine.c driver has already set the delay parameter to 1 which I'm not sure is the minimum.  This is where I hit the dead-end.  Can this be adjusted further to reduce the tCNVH pulse length?

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  • Hello Sergiu ,

    I'm using both 2020.1 and 2019_R2 HDL versions with petalinux/meta-adi 2020.1 and 2019_R2 as well.  I haven't use the no-OS drivers yet as I'm using AD4020 Linux driver on the Zedboard Linux.

    No, I haven't altered the HDL, as I'm more of a Linux developer and not very experienced on the FPGA design so I really don't know where to dive deeper on the HDL details.

    Thanks for the waveform you shared.  As additional details, here are some of the measurements I did based on the oscilloscope waveform I shared above:

    entire conversion + spi transfer cycle = 1.130 us

    pulse high length of my CS or CNV sign = 615 ns

    SCK period = 23 ns

    But in your logic analyzer waveform,

    entire conversion + spi transfer cycle as you said is 576 ns

    pulse length of CS or CNV sign is ~300 ns

    It seems as if the timings in my Linux Zedboard setup increased by an order of 2 and hence my sampling rate got cut to half of what you are seeing...

    I'm not sure what's causing this.  Zedboard clocks?  As I've said, I neither altered the HDL for this nor made a lot of changes in the device tree scripts.

  • Hi Sergiu 

    I went back to our hardware engineer and he confirmed that there indeed are changes from AD4020 I was not aware of.  The ADC we have at our Zedboard is not AD4020, but ADAQ4003 (and so the driver is still compatible).  I looked at its specs and it's 18-bits vs 20-bits of AD4020.

    He also mentioned he re-arranged the SPI pins' constraints in the HDL to fit in the FMC connections of this board


    An amplifier pin from the AD4020 Eval board, which does not exist in the ADAQ4003 eval board, was moved somewhere in the FMC pins where it was thought harmless.

    How do we then change the reference HDL to correct the sampling speed in this ADC?  Is this HDL hard-coded for the 20-bit ADC like AD4020?

  • To anyone who will incorporate the fix,

    While the thread is located on FPGA reference section (as I thought it was  caused in FPGA), the problem cause was in fact in the Linux driver, and so the fix was done in the driver code.  The link in the verified solution shows how it is done.