Dear all,
We're creating a custom solution using the ADRV9364-Z7020 board. Due to adding several custom IPs (DMA, custom VHDL blocks, i2c, SPI...), we are building the devicetree again from the Vivado design, and then compiling Petalinux to generate the necessary files for booting from the SDCard (and later on probably from QSPI).
Using the meta-adi package, we have configured everything but we can't wrap our heads around the KERNEL_DTB step. Following the answer in this post, we understand that we need to extract the pl.dtsi from a raw petalinux-build:
/*
* CAUTION: This file is automatically generated by Xilinx.
* Version:
* Today is: Fri Sep 3 15:13:59 2021
*/
/ {
amba_pl: amba_pl {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges ;
AD9361_SDR_axi_ad9361: axi_ad9361@79020000 {
clock-names = "delay_clk", "clk", "s_axi_aclk";
clocks = <&clkc 16>, <&misc_clk_0>, <&clkc 15>;
compatible = "xlnx,axi-ad9361-1.0";
interrupt-names = "gps_pps_irq";
interrupt-parent = <&intc>;
interrupts = <0 33 4>;
reg = <0x79020000 0x10000>;
};
misc_clk_0: misc_clk_0 {
#clock-cells = <0>;
clock-frequency = <100000000>;
compatible = "fixed-clock";
};
AD9361_SDR_axi_ad9361_adc_dma: axi_dmac@7c400000 {
clock-names = "s_axi_aclk", "m_dest_axi_aclk", "fifo_wr_clk";
clocks = <&clkc 15>, <&clkc 15>, <&clkc 15>;
compatible = "xlnx,axi-dmac-1.0";
interrupt-names = "irq";
interrupt-parent = <&intc>;
interrupts = <0 31 4>;
reg = <0x7c400000 0x1000>;
};
AD9361_SDR_axi_ad9361_dac_dma: axi_dmac@7c420000 {
clock-names = "s_axi_aclk", "m_src_axi_aclk", "m_axis_aclk";
clocks = <&clkc 15>, <&clkc 15>, <&clkc 15>;
compatible = "xlnx,axi-dmac-1.0";
interrupt-names = "irq";
interrupt-parent = <&intc>;
interrupts = <0 32 4>;
reg = <0x7c420000 0x1000>;
};
CPU_axi_sysid_0: axi_sysid@45000000 {
clock-names = "s_axi_aclk";
clocks = <&clkc 15>;
compatible = "xlnx,axi-sysid-1.0";
reg = <0x45000000 0x10000>;
};
axi_dma_0: dma@40400000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_s2mm_aclk";
clocks = <&clkc 15>, <&clkc 15>, <&clkc 15>;
compatible = "xlnx,axi-dma-7.1", "xlnx,axi-dma-1.00.a";
interrupt-names = "s2mm_introut";
interrupt-parent = <&intc>;
interrupts = <0 30 4>;
reg = <0x40400000 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
xlnx,sg-include-stscntrl-strm ;
xlnx,sg-length-width = <0xe>;
dma-channel@40400030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
interrupts = <0 30 4>;
xlnx,datawidth = <0x20>;
xlnx,device-id = <0x0>;
};
};
};
};
Then create a file to delete those nodes that do not belong to Xilinx (AD9361, for example), and then include both of those files plus all the other .dts files that we obtained from Vivado, together with a base file that represents our system and is in the Analog Devices github (fmcomms-4, z7020?).
With that, we can add all these files to the build system in the unnamed file referenced in this link.
Is this correct? We are really struggling to understand this procedure, but at least it seems like the documentation is miles better than when we were trying with Buildroot.
Best regards.
