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Custom devicetree in Petalinux build for ADRV9364-Z7020

Dear all,

We're creating a custom solution using the ADRV9364-Z7020 board. Due to adding several custom IPs (DMA, custom VHDL blocks, i2c, SPI...), we are building the devicetree again from the Vivado design, and then compiling Petalinux to generate the necessary files for booting from the SDCard (and later on probably from QSPI).

Using the meta-adi package, we have configured everything but we can't wrap our heads around the KERNEL_DTB step. Following the answer in this post, we understand that we need to extract the pl.dtsi from a raw petalinux-build:

/*
 * CAUTION: This file is automatically generated by Xilinx.
 * Version:  
 * Today is: Fri Sep  3 15:13:59 2021
 */


/ {
	amba_pl: amba_pl {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges ;
		AD9361_SDR_axi_ad9361: axi_ad9361@79020000 {
			clock-names = "delay_clk", "clk", "s_axi_aclk";
			clocks = <&clkc 16>, <&misc_clk_0>, <&clkc 15>;
			compatible = "xlnx,axi-ad9361-1.0";
			interrupt-names = "gps_pps_irq";
			interrupt-parent = <&intc>;
			interrupts = <0 33 4>;
			reg = <0x79020000 0x10000>;
		};
		misc_clk_0: misc_clk_0 {
			#clock-cells = <0>;
			clock-frequency = <100000000>;
			compatible = "fixed-clock";
		};
		AD9361_SDR_axi_ad9361_adc_dma: axi_dmac@7c400000 {
			clock-names = "s_axi_aclk", "m_dest_axi_aclk", "fifo_wr_clk";
			clocks = <&clkc 15>, <&clkc 15>, <&clkc 15>;
			compatible = "xlnx,axi-dmac-1.0";
			interrupt-names = "irq";
			interrupt-parent = <&intc>;
			interrupts = <0 31 4>;
			reg = <0x7c400000 0x1000>;
		};
		AD9361_SDR_axi_ad9361_dac_dma: axi_dmac@7c420000 {
			clock-names = "s_axi_aclk", "m_src_axi_aclk", "m_axis_aclk";
			clocks = <&clkc 15>, <&clkc 15>, <&clkc 15>;
			compatible = "xlnx,axi-dmac-1.0";
			interrupt-names = "irq";
			interrupt-parent = <&intc>;
			interrupts = <0 32 4>;
			reg = <0x7c420000 0x1000>;
		};
		CPU_axi_sysid_0: axi_sysid@45000000 {
			clock-names = "s_axi_aclk";
			clocks = <&clkc 15>;
			compatible = "xlnx,axi-sysid-1.0";
			reg = <0x45000000 0x10000>;
		};
		axi_dma_0: dma@40400000 {
			#dma-cells = <1>;
			clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_s2mm_aclk";
			clocks = <&clkc 15>, <&clkc 15>, <&clkc 15>;
			compatible = "xlnx,axi-dma-7.1", "xlnx,axi-dma-1.00.a";
			interrupt-names = "s2mm_introut";
			interrupt-parent = <&intc>;
			interrupts = <0 30 4>;
			reg = <0x40400000 0x10000>;
			xlnx,addrwidth = <0x20>;
			xlnx,include-sg ;
			xlnx,sg-include-stscntrl-strm ;
			xlnx,sg-length-width = <0xe>;
			dma-channel@40400030 {
				compatible = "xlnx,axi-dma-s2mm-channel";
				dma-channels = <0x1>;
				interrupts = <0 30 4>;
				xlnx,datawidth = <0x20>;
				xlnx,device-id = <0x0>;
			};
		};
	};
};

Then create a file to delete those nodes that do not belong to Xilinx (AD9361, for example), and then include both of those files plus all the other .dts files that we obtained from Vivado, together with a base file that represents our system and is in the Analog Devices github (fmcomms-4, z7020?).

With that, we can add all these files to the build system in the unnamed file referenced in this link.

Is this correct? We are really struggling to understand this procedure, but at least it seems like the documentation is miles better than when we were trying with Buildroot.

Best regards.

Parents
  • Hi,

    Looking at your pl.dtsi you should delete everything but the axi_dma node... Though Im not sure about the dma node. Is it a xilinx IP? Or is it the ADI DMA IP or your custom one? If it's custom, then you probably have to delete it as well.

    d then include both of those files plus all the other .dts files that we obtained from Vivado, together with a base file that represents our system and is in the Analog Devices github (fmcomms-4, z7020?).

    You should only have to care about setting the KERNEL_DTB variable in your petalinuxbsp.conf file. This tells the system which devicetree you'll want to use. Then, you also need to make sure pl-delete-nodes-${KERNEL_DTB} will be in the working directory. You do that by appending SRC_URI. Now, you have two ways of introducing your changes:

    1) Your changes are not that much so that you can extend the ADI base devicetree (in this case fmcomms-4, z7020). Here, you would set KERNEL_DTB = "zynqmp-zcu102-rev10-ad9364-fmcomms4". And your .dtsi to delete the autogenerated nodes would be "pl-delete-nodes-zynqmp-zcu102-rev10-ad9364-fmcomms4.dtsi". You would also need to tell the system to use the pl-delete nodes file (because  it's not one of the supported projects) by appending the devicetree recipe with this:

    FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
    
    SRC_URI_append = " \
    	pl-delete-nodes-zynqmp-zcu102-rev10-ad9364-fmcomms4.dtsi "

    2) You have considerable changes so that you decide to define your own devicetree (probably based on the ADI one). Then you should follow adding-a-new-devicetree. Here KERNEL_DTB should be whatever name you give to your dts. The delete nodes should have the same name prepended with pl-delete-nodes-. In this case, the devicetree won't be in the ADI kernel tree so you can also set 'USE_KERNEL_SOURCES = "n"' in your devicetree.bbappend recipe as specified in the documentation.

    - Nuno Sá

  • Dear Nuno,

    I apologize for the delay. I have been trying to follow both approaches (extending and creating a new one) to no success. This has prompted me to wonder how necessary it is to actually rebuild the kernel with the modifications I've done to the Vivado project. I have moved around some MIO and EMIO, added more i2c, a custom processing block connected to a DMA, and not much more. Is this enough to warrant a kernel / rootfs rebuild? When is this necessary?

    I've been attempting to manually generate the BOOT.BIN with the new manually-compiled devicetree (from the .xsa) and the bitstream generated by Vivado (in impl_1), while keeping uImage, the rootfs, fsbl and u-boot the same, but I get stuck in Starting kernel (earlyprintk does not provide much information).

    [18928.18h.04m.07s.587] ## Booting kernel from Legacy Image at 03000000 ...
    [18928.18h.04m.07s.587]    Image Name:   Linux-4.19.0-g17f4223
    [18928.18h.04m.07s.587]    Image Type:   ARM Linux Kernel Image (uncompressed)
    [18928.18h.04m.07s.587]    Data Size:    6316656 Bytes = 6 MiB
    [18928.18h.04m.07s.587]    Load Address: 00008000
    [18928.18h.04m.07s.587]    Entry Point:  00008000
    [18928.18h.04m.07s.587]    Verifying Checksum ... OK
    [18928.18h.04m.07s.661] ## Flattened Device Tree blob at 02a00000
    [18928.18h.04m.07s.661]    Booting using the fdt blob at 0x2a00000
    [18928.18h.04m.07s.661]    Loading Kernel Image ... OK
    [18928.18h.04m.07s.693]    Loading Device Tree to 1ed1d000, end 1ed232ff ... OK
    [18928.18h.04m.07s.714] 
    [18928.18h.04m.07s.714] Starting kernel ...
    [18928.18h.04m.07s.714] 
    [18928.18h.04m.08s.178] Booting Linux on physical CPU 0x0
    [18928.18h.04m.08s.178] Linux version 4.19.0-g17f4223 (jenkins@romlxbuild1.adlk.analog.com) (gcc version 8.2.0 (GCC)) #1848 SMP PREEMPT Tue Jul 27 12:46:50 IST 2021
    [18928.18h.04m.08s.178] CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
    [18928.18h.04m.08s.178] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
    [18928.18h.04m.08s.178] OF: fdt: Machine model: xlnx,zynq-7000
    [18928.18h.04m.08s.178] earlycon: cdns0 at MMIO 0xe0000000 (options '115200n8')
    [18928.18h.04m.08s.178] bootconsole [cdns0] enabled
    [18928.18h.04m.08s.178] bootconsole [earlycon0] enabled
    [18928.18h.04m.08s.178] Memory policy: Data cache writealloc
    [18928.18h.04m.08s.194] cma: Reserved 128 MiB at 0x38000000
    [18928.18h.04m.08s.226] random: get_random_bytes called from start_kernel+0xa0/0x404 with crng_init=0
    [18928.18h.04m.08s.275] percpu: Embedded 16 pages/cpu @(ptrval) s33548 r8192 d23796 u65536
    [18928.18h.04m.08s.275] Built 1 zonelists, mobility grouping on.  Total pages: 260608
    [18928.18h.04m.08s.275] Kernel command line: console=ttyPS1,115200 root=/dev/mmcblk0p2 rw earlycon rootfstype=ext4 rootwait earlyprintk
    [18928.18h.04m.08s.275] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
    [18928.18h.04m.08s.275] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
    [18928.18h.04m.08s.371] Memory: 889484K/1048576K available (9216K kernel code, 759K rwdata, 6760K rodata, 1024K init, 167K bss, 28020K reserved, 131072K cma-reserved, 131072K highmem)
    [18928.18h.04m.08s.371] Virtual kernel memory layout:
    [18928.18h.04m.08s.371]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    [18928.18h.04m.08s.371]     fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
    [18928.18h.04m.08s.371]     vmalloc : 0xf0800000 - 0xff800000   ( 240 MB)
    [18928.18h.04m.08s.371]     lowmem  : 0xc0000000 - 0xf0000000   ( 768 MB)
    [18928.18h.04m.08s.371]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    [18928.18h.04m.08s.371]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
    [18928.18h.04m.08s.414]       .text : 0x(ptrval) - 0x(ptrval)   (10208 kB)
    [18928.18h.04m.08s.414]       .init : 0x(ptrval) - 0x(ptrval)   (1024 kB)
    [18928.18h.04m.08s.414]       .data : 0x(ptrval) - 0x(ptrval)   ( 760 kB)
    [18928.18h.04m.08s.414]        .bss : 0x(ptrval) - 0x(ptrval)   ( 168 kB)
    [18928.18h.04m.08s.414] rcu: Preemptible hierarchical RCU implementation.
    [18928.18h.04m.08s.414] rcu: 	RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
    [18928.18h.04m.08s.414] 	Tasks RCU enabled.
    [18928.18h.04m.08s.414] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
    [18928.18h.04m.08s.414] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
    [18928.18h.04m.08s.414] efuse mapped to (ptrval)
    [18928.18h.04m.08s.414] slcr mapped to (ptrval)
    [18928.18h.04m.08s.457] L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
    [18928.18h.04m.08s.457] L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
    [18928.18h.04m.08s.457] L2C-310 erratum 769419 enabled
    [18928.18h.04m.08s.457] L2C-310 enabling early BRESP for Cortex-A9
    [18928.18h.04m.08s.457] L2C-310 full line of zeros enabled for Cortex-A9
    [18928.18h.04m.08s.457] L2C-310 ID prefetch enabled, offset 1 lines
    [18928.18h.04m.08s.457] L2C-310 dynamic clock gating enabled, standby mode enabled
    [18928.18h.04m.08s.457] L2C-310 cache controller enabled, 8 ways, 512 kB
    [18928.18h.04m.08s.457] L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
    [18928.18h.04m.08s.457] zynq_clock_init: clkc starts at (ptrval)
    [18928.18h.04m.08s.502] Zynq clock init
    [18928.18h.04m.08s.502] sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 4398046511103ns
    [18928.18h.04m.08s.502] clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4ce07af025, max_idle_ns: 440795209040 ns
    [18928.18h.04m.08s.502] Switching to timer-based delay loop, resolution 3ns
    [18928.18h.04m.08s.502] clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 537538477 ns
    [18928.18h.04m.08s.502] timer #0 at (ptrval), irq=17
    [18928.18h.04m.08s.502] Console: colour dummy device 80x30
    [18928.18h.04m.08s.502] Calibrating delay loop (skipped), value calculated using timer frequency.. 666.66 BogoMIPS (lpj=3333333)
    [18928.18h.04m.08s.544] pid_max: default: 32768 minimum: 301
    [18928.18h.04m.08s.544] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
    [18928.18h.04m.08s.544] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
    [18928.18h.04m.08s.544] CPU: Testing write buffer coherency: ok
    [18928.18h.04m.08s.544] CPU0: Spectre v2: using BPIALL workaround
    [18928.18h.04m.08s.544] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
    [18928.18h.04m.08s.605] Setting up static identity map for 0x100000 - 0x100060
    [18928.18h.04m.08s.605] rcu: Hierarchical SRCU implementation.
    [18928.18h.04m.08s.637] smp: Bringing up secondary CPUs ...
    [18928.18h.04m.08s.757] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
    [18928.18h.04m.08s.757] CPU1: Spectre v2: using BPIALL workaround
    [18928.18h.04m.08s.757] smp: Brought up 1 node, 2 CPUs
    [18928.18h.04m.08s.757] SMP: Total of 2 processors activated (1333.33 BogoMIPS).
    [18928.18h.04m.08s.757] CPU: All CPU(s) started in SVC mode.
    [18928.18h.04m.08s.757] devtmpfs: initialized
    [18928.18h.04m.08s.757] VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
    [18928.18h.04m.08s.757] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
    [18928.18h.04m.08s.757] futex hash table entries: 512 (order: 3, 32768 bytes)
    [18928.18h.04m.08s.757] pinctrl core: initialized pinctrl subsystem
    [18928.18h.04m.08s.817] NET: Registered protocol family 16
    [18928.18h.04m.08s.817] DMA: preallocated 256 KiB pool for atomic coherent allocations
    [18928.18h.04m.08s.817] cpuidle: using governor ladder
    [18928.18h.04m.08s.817] hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
    [18928.18h.04m.08s.817] hw-breakpoint: maximum watchpoint size is 4 bytes.
    [18928.18h.04m.08s.817] zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0x(ptrval)
    [18928.18h.04m.08s.817] zynq-pinctrl 700.pinctrl: zynq pinctrl initialized

    Is this the correct way to proceed or should I go back to the petalinux-build?

    Best regards,

    Adrián.

Reply
  • Dear Nuno,

    I apologize for the delay. I have been trying to follow both approaches (extending and creating a new one) to no success. This has prompted me to wonder how necessary it is to actually rebuild the kernel with the modifications I've done to the Vivado project. I have moved around some MIO and EMIO, added more i2c, a custom processing block connected to a DMA, and not much more. Is this enough to warrant a kernel / rootfs rebuild? When is this necessary?

    I've been attempting to manually generate the BOOT.BIN with the new manually-compiled devicetree (from the .xsa) and the bitstream generated by Vivado (in impl_1), while keeping uImage, the rootfs, fsbl and u-boot the same, but I get stuck in Starting kernel (earlyprintk does not provide much information).

    [18928.18h.04m.07s.587] ## Booting kernel from Legacy Image at 03000000 ...
    [18928.18h.04m.07s.587]    Image Name:   Linux-4.19.0-g17f4223
    [18928.18h.04m.07s.587]    Image Type:   ARM Linux Kernel Image (uncompressed)
    [18928.18h.04m.07s.587]    Data Size:    6316656 Bytes = 6 MiB
    [18928.18h.04m.07s.587]    Load Address: 00008000
    [18928.18h.04m.07s.587]    Entry Point:  00008000
    [18928.18h.04m.07s.587]    Verifying Checksum ... OK
    [18928.18h.04m.07s.661] ## Flattened Device Tree blob at 02a00000
    [18928.18h.04m.07s.661]    Booting using the fdt blob at 0x2a00000
    [18928.18h.04m.07s.661]    Loading Kernel Image ... OK
    [18928.18h.04m.07s.693]    Loading Device Tree to 1ed1d000, end 1ed232ff ... OK
    [18928.18h.04m.07s.714] 
    [18928.18h.04m.07s.714] Starting kernel ...
    [18928.18h.04m.07s.714] 
    [18928.18h.04m.08s.178] Booting Linux on physical CPU 0x0
    [18928.18h.04m.08s.178] Linux version 4.19.0-g17f4223 (jenkins@romlxbuild1.adlk.analog.com) (gcc version 8.2.0 (GCC)) #1848 SMP PREEMPT Tue Jul 27 12:46:50 IST 2021
    [18928.18h.04m.08s.178] CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
    [18928.18h.04m.08s.178] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
    [18928.18h.04m.08s.178] OF: fdt: Machine model: xlnx,zynq-7000
    [18928.18h.04m.08s.178] earlycon: cdns0 at MMIO 0xe0000000 (options '115200n8')
    [18928.18h.04m.08s.178] bootconsole [cdns0] enabled
    [18928.18h.04m.08s.178] bootconsole [earlycon0] enabled
    [18928.18h.04m.08s.178] Memory policy: Data cache writealloc
    [18928.18h.04m.08s.194] cma: Reserved 128 MiB at 0x38000000
    [18928.18h.04m.08s.226] random: get_random_bytes called from start_kernel+0xa0/0x404 with crng_init=0
    [18928.18h.04m.08s.275] percpu: Embedded 16 pages/cpu @(ptrval) s33548 r8192 d23796 u65536
    [18928.18h.04m.08s.275] Built 1 zonelists, mobility grouping on.  Total pages: 260608
    [18928.18h.04m.08s.275] Kernel command line: console=ttyPS1,115200 root=/dev/mmcblk0p2 rw earlycon rootfstype=ext4 rootwait earlyprintk
    [18928.18h.04m.08s.275] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
    [18928.18h.04m.08s.275] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
    [18928.18h.04m.08s.371] Memory: 889484K/1048576K available (9216K kernel code, 759K rwdata, 6760K rodata, 1024K init, 167K bss, 28020K reserved, 131072K cma-reserved, 131072K highmem)
    [18928.18h.04m.08s.371] Virtual kernel memory layout:
    [18928.18h.04m.08s.371]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    [18928.18h.04m.08s.371]     fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
    [18928.18h.04m.08s.371]     vmalloc : 0xf0800000 - 0xff800000   ( 240 MB)
    [18928.18h.04m.08s.371]     lowmem  : 0xc0000000 - 0xf0000000   ( 768 MB)
    [18928.18h.04m.08s.371]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    [18928.18h.04m.08s.371]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
    [18928.18h.04m.08s.414]       .text : 0x(ptrval) - 0x(ptrval)   (10208 kB)
    [18928.18h.04m.08s.414]       .init : 0x(ptrval) - 0x(ptrval)   (1024 kB)
    [18928.18h.04m.08s.414]       .data : 0x(ptrval) - 0x(ptrval)   ( 760 kB)
    [18928.18h.04m.08s.414]        .bss : 0x(ptrval) - 0x(ptrval)   ( 168 kB)
    [18928.18h.04m.08s.414] rcu: Preemptible hierarchical RCU implementation.
    [18928.18h.04m.08s.414] rcu: 	RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
    [18928.18h.04m.08s.414] 	Tasks RCU enabled.
    [18928.18h.04m.08s.414] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
    [18928.18h.04m.08s.414] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
    [18928.18h.04m.08s.414] efuse mapped to (ptrval)
    [18928.18h.04m.08s.414] slcr mapped to (ptrval)
    [18928.18h.04m.08s.457] L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
    [18928.18h.04m.08s.457] L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
    [18928.18h.04m.08s.457] L2C-310 erratum 769419 enabled
    [18928.18h.04m.08s.457] L2C-310 enabling early BRESP for Cortex-A9
    [18928.18h.04m.08s.457] L2C-310 full line of zeros enabled for Cortex-A9
    [18928.18h.04m.08s.457] L2C-310 ID prefetch enabled, offset 1 lines
    [18928.18h.04m.08s.457] L2C-310 dynamic clock gating enabled, standby mode enabled
    [18928.18h.04m.08s.457] L2C-310 cache controller enabled, 8 ways, 512 kB
    [18928.18h.04m.08s.457] L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
    [18928.18h.04m.08s.457] zynq_clock_init: clkc starts at (ptrval)
    [18928.18h.04m.08s.502] Zynq clock init
    [18928.18h.04m.08s.502] sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 4398046511103ns
    [18928.18h.04m.08s.502] clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4ce07af025, max_idle_ns: 440795209040 ns
    [18928.18h.04m.08s.502] Switching to timer-based delay loop, resolution 3ns
    [18928.18h.04m.08s.502] clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 537538477 ns
    [18928.18h.04m.08s.502] timer #0 at (ptrval), irq=17
    [18928.18h.04m.08s.502] Console: colour dummy device 80x30
    [18928.18h.04m.08s.502] Calibrating delay loop (skipped), value calculated using timer frequency.. 666.66 BogoMIPS (lpj=3333333)
    [18928.18h.04m.08s.544] pid_max: default: 32768 minimum: 301
    [18928.18h.04m.08s.544] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
    [18928.18h.04m.08s.544] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
    [18928.18h.04m.08s.544] CPU: Testing write buffer coherency: ok
    [18928.18h.04m.08s.544] CPU0: Spectre v2: using BPIALL workaround
    [18928.18h.04m.08s.544] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
    [18928.18h.04m.08s.605] Setting up static identity map for 0x100000 - 0x100060
    [18928.18h.04m.08s.605] rcu: Hierarchical SRCU implementation.
    [18928.18h.04m.08s.637] smp: Bringing up secondary CPUs ...
    [18928.18h.04m.08s.757] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
    [18928.18h.04m.08s.757] CPU1: Spectre v2: using BPIALL workaround
    [18928.18h.04m.08s.757] smp: Brought up 1 node, 2 CPUs
    [18928.18h.04m.08s.757] SMP: Total of 2 processors activated (1333.33 BogoMIPS).
    [18928.18h.04m.08s.757] CPU: All CPU(s) started in SVC mode.
    [18928.18h.04m.08s.757] devtmpfs: initialized
    [18928.18h.04m.08s.757] VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
    [18928.18h.04m.08s.757] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
    [18928.18h.04m.08s.757] futex hash table entries: 512 (order: 3, 32768 bytes)
    [18928.18h.04m.08s.757] pinctrl core: initialized pinctrl subsystem
    [18928.18h.04m.08s.817] NET: Registered protocol family 16
    [18928.18h.04m.08s.817] DMA: preallocated 256 KiB pool for atomic coherent allocations
    [18928.18h.04m.08s.817] cpuidle: using governor ladder
    [18928.18h.04m.08s.817] hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
    [18928.18h.04m.08s.817] hw-breakpoint: maximum watchpoint size is 4 bytes.
    [18928.18h.04m.08s.817] zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0x(ptrval)
    [18928.18h.04m.08s.817] zynq-pinctrl 700.pinctrl: zynq pinctrl initialized

    Is this the correct way to proceed or should I go back to the petalinux-build?

    Best regards,

    Adrián.

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