Post Go back to editing

Access TX/RX DMA Addresses from BOOT.bin in PackRF

I used both MATLAB R2020b and Vivado 2018.3 to generate BOOT.bin from my customized transceiver for my PackRF. In Set Target Interface (Section 1.3) of the HDL Workflow Advisor in Simulink, I set the following:

* ch1_tx_dma_i as IP Data 0 IN [0:15]

ch1_tx_dma_q as IP Data 1 IN [0:15]

* ch2_tx_dma_i as IP Data 2 IN [0:15]

* ch2_tx_dma_q as IP Data 3 IN [0:15]

* ch1_rx_dma_i as IP Data 0 OUT [0:15]

* ch1_rx_dma_q as IP Data 1 OUT [0:15]

* ch2_rx_dma_i as IP Data 2 OUT [0:15]

* ch2_rx_dma_q as IP Data 3 OUT [0:15]

When I turn on PackRF with customized BOOT.bin, what will be the locations and addresses of these IQ DMAs?

  • DMA memory locations are defined in the device tree. Here is the base address for the RX DMAs: https://github.com/analogdevicesinc/linux/blob/d7c0f7cad3280fdcff25a20443ad82487f2d3921/arch/arm/boot/dts/zynq-adrv9361-z7035.dtsi#L140

    This may be different for your board based on the software version. I would decompile and check the running device tree from your system's BOOT partition. These will match the offset addresses in Vivado.

    -Travis

  • Thank you, Travis. My Linux version is Linux analog 4.19.0-ga6ef26d and the dtb file is from zynq-adrv9361-z7035-packrf. After converting to dts file, it shows as

    /dts-v1/;
    
    / {
    	#address-cells = < 0x01 >;
    	#size-cells = < 0x01 >;
    	compatible = "xlnx,zynq-7000";
    	interrupt-parent = < 0x01 >;
    	model = "Analog Devices ADRV9361-Z7035 RFSOM-BOX (Z7035/AD9361)";
    
    	cpus {
    		#address-cells = < 0x01 >;
    		#size-cells = < 0x00 >;
    
    		cpu@0 {
    			compatible = "arm,cortex-a9";
    			device_type = "cpu";
    			reg = < 0x00 >;
    			clocks = < 0x02 0x03 >;
    			clock-latency = < 0x3e8 >;
    			cpu0-supply = < 0x03 >;
    			operating-points = < 0xa2c2b 0xf4240 0x51616 0xf4240 >;
    		};
    
    		cpu@1 {
    			compatible = "arm,cortex-a9";
    			device_type = "cpu";
    			reg = < 0x01 >;
    			clocks = < 0x02 0x03 >;
    		};
    	};
    
    	fpga-full {
    		compatible = "fpga-region";
    		fpga-mgr = < 0x04 >;
    		#address-cells = < 0x01 >;
    		#size-cells = < 0x01 >;
    		ranges;
    	};
    
    	pmu@f8891000 {
    		compatible = "arm,cortex-a9-pmu";
    		interrupts = < 0x00 0x05 0x04 0x00 0x06 0x04 >;
    		interrupt-parent = < 0x01 >;
    		reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
    	};
    
    	fixedregulator {
    		compatible = "regulator-fixed";
    		regulator-name = "VCCPINT";
    		regulator-min-microvolt = < 0xf4240 >;
    		regulator-max-microvolt = < 0xf4240 >;
    		regulator-boot-on;
    		regulator-always-on;
    		phandle = < 0x03 >;
    	};
    
    	amba {
    		u-boot,dm-pre-reloc;
    		compatible = "simple-bus";
    		#address-cells = < 0x01 >;
    		#size-cells = < 0x01 >;
    		interrupt-parent = < 0x01 >;
    		ranges;
    
    		adc@f8007100 {
    			compatible = "xlnx,zynq-xadc-1.00.a";
    			reg = < 0xf8007100 0x20 >;
    			interrupts = < 0x00 0x07 0x04 >;
    			interrupt-parent = < 0x01 >;
    			clocks = < 0x02 0x0c >;
    		};
    
    		can@e0008000 {
    			compatible = "xlnx,zynq-can-1.0";
    			status = "disabled";
    			clocks = < 0x02 0x13 0x02 0x24 >;
    			clock-names = "can_clk\0pclk";
    			reg = < 0xe0008000 0x1000 >;
    			interrupts = < 0x00 0x1c 0x04 >;
    			interrupt-parent = < 0x01 >;
    			tx-fifo-depth = < 0x40 >;
    			rx-fifo-depth = < 0x40 >;
    		};
    
    		can@e0009000 {
    			compatible = "xlnx,zynq-can-1.0";
    			status = "disabled";
    			clocks = < 0x02 0x14 0x02 0x25 >;
    			clock-names = "can_clk\0pclk";
    			reg = < 0xe0009000 0x1000 >;
    			interrupts = < 0x00 0x33 0x04 >;
    			interrupt-parent = < 0x01 >;
    			tx-fifo-depth = < 0x40 >;
    			rx-fifo-depth = < 0x40 >;
    		};
    
    		gpio@e000a000 {
    			compatible = "xlnx,zynq-gpio-1.0";
    			#gpio-cells = < 0x02 >;
    			clocks = < 0x02 0x2a >;
    			gpio-controller;
    			interrupt-controller;
    			#interrupt-cells = < 0x02 >;
    			interrupt-parent = < 0x01 >;
    			interrupts = < 0x00 0x14 0x04 >;
    			reg = < 0xe000a000 0x1000 >;
    			phandle = < 0x06 >;
    
    			imu_rstn {
    				gpio-hog;
    				gpios = < 0x3f 0x00 >;
    				output-high;
    				line-name = "imu_rstn";
    			};
    
    			gps_reset0 {
    				gpio-hog;
    				gpios = < 0x3c 0x00 >;
    				output-high;
    				line-name = "gps_reset";
    			};
    
    			gps_force_on {
    				gpio-hog;
    				gpios = < 0x3b 0x00 >;
    				input;
    				line-name = "gps_force_on";
    			};
    
    			gps_standby {
    				gpio-hog;
    				gpios = < 0x3a 0x00 >;
    				input;
    				line-name = "gps_standby";
    			};
    		};
    
    		i2c@e0004000 {
    			compatible = "cdns,i2c-r1p10";
    			status = "disabled";
    			clocks = < 0x02 0x26 >;
    			interrupt-parent = < 0x01 >;
    			interrupts = < 0x00 0x19 0x04 >;
    			reg = < 0xe0004000 0x1000 >;
    			#address-cells = < 0x01 >;
    			#size-cells = < 0x00 >;
    		};
    
    		i2c@e0005000 {
    			compatible = "cdns,i2c-r1p10";
    			status = "disabled";
    			clocks = < 0x02 0x27 >;
    			interrupt-parent = < 0x01 >;
    			interrupts = < 0x00 0x30 0x04 >;
    			reg = < 0xe0005000 0x1000 >;
    			#address-cells = < 0x01 >;
    			#size-cells = < 0x00 >;
    		};
    
    		interrupt-controller@f8f01000 {
    			compatible = "arm,cortex-a9-gic";
    			#interrupt-cells = < 0x03 >;
    			interrupt-controller;
    			reg = < 0xf8f01000 0x1000 0xf8f00100 0x100 >;
    			phandle = < 0x01 >;
    		};
    
    		cache-controller@f8f02000 {
    			compatible = "arm,pl310-cache";
    			reg = < 0xf8f02000 0x1000 >;
    			interrupts = < 0x00 0x02 0x04 >;
    			arm,data-latency = < 0x03 0x02 0x02 >;
    			arm,tag-latency = < 0x02 0x02 0x02 >;
    			cache-unified;
    			cache-level = < 0x02 >;
    		};
    
    		memory-controller@f8006000 {
    			compatible = "xlnx,zynq-ddrc-a05";
    			reg = < 0xf8006000 0x1000 >;
    		};
    
    		ocmc@f800c000 {
    			compatible = "xlnx,zynq-ocmc-1.0";
    			interrupt-parent = < 0x01 >;
    			interrupts = < 0x00 0x03 0x04 >;
    			reg = < 0xf800c000 0x1000 >;
    		};
    
    		serial@e0000000 {
    			compatible = "xlnx,xuartps\0cdns,uart-r1p8";
    			status = "okay";
    			clocks = < 0x02 0x17 0x02 0x28 >;
    			clock-names = "uart_clk\0pclk";
    			reg = < 0xe0000000 0x1000 >;
    			interrupts = < 0x00 0x1b 0x04 >;
    		};
    
    		serial@e0001000 {
    			compatible = "xlnx,xuartps\0cdns,uart-r1p8";
    			status = "okay";
    			clocks = < 0x02 0x18 0x02 0x29 >;
    			clock-names = "uart_clk\0pclk";
    			reg = < 0xe0001000 0x1000 >;
    			interrupts = < 0x00 0x32 0x04 >;
    		};
    
    		spi@e0006000 {
    			compatible = "xlnx,zynq-spi-r1p6";
    			reg = < 0xe0006000 0x1000 >;
    			status = "okay";
    			interrupt-parent = < 0x01 >;
    			interrupts = < 0x00 0x1a 0x04 >;
    			clocks = < 0x02 0x19 0x02 0x22 >;
    			clock-names = "ref_clk\0pclk";
    			#address-cells = < 0x01 >;
    			#size-cells = < 0x00 >;
    
    			ad9361-phy@0 {
    				#address-cells = < 0x01 >;
    				#size-cells = < 0x00 >;
    				#clock-cells = < 0x01 >;
    				compatible = "adi,ad9361";
    				reg = < 0x00 >;
    				spi-cpha;
    				spi-max-frequency = < 0x989680 >;
    				clocks = < 0x05 0x00 >;
    				clock-names = "ad9361_ext_refclk";
    				clock-output-names = "rx_sampl_clk\0tx_sampl_clk";
    				adi,digital-interface-tune-skip-mode = < 0x00 >;
    				adi,pp-tx-swap-enable;
    				adi,pp-rx-swap-enable;
    				adi,rx-frame-pulse-mode-enable;
    				adi,lvds-mode-enable;
    				adi,lvds-bias-mV = < 0x96 >;
    				adi,lvds-rx-onchip-termination-enable;
    				adi,rx-data-delay = < 0x04 >;
    				adi,tx-fb-clock-delay = < 0x07 >;
    				adi,xo-disable-use-ext-refclk-enable;
    				adi,2rx-2tx-mode-enable;
    				adi,frequency-division-duplex-mode-enable;
    				adi,rx-rf-port-input-select = < 0x00 >;
    				adi,tx-rf-port-input-select = < 0x00 >;
    				adi,tx-attenuation-mdB = < 0x2710 >;
    				adi,tx-lo-powerdown-managed-enable;
    				adi,rf-rx-bandwidth-hz = < 0x112a880 >;
    				adi,rf-tx-bandwidth-hz = < 0x112a880 >;
    				adi,rx-synthesizer-frequency-hz = < 0x00 0x8f0d1800 >;
    				adi,tx-synthesizer-frequency-hz = < 0x00 0x92080880 >;
    				adi,rx-path-clock-frequencies = < 0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000 >;
    				adi,tx-path-clock-frequencies = < 0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000 >;
    				adi,gc-rx1-mode = < 0x02 >;
    				adi,gc-rx2-mode = < 0x02 >;
    				adi,gc-adc-ovr-sample-size = < 0x04 >;
    				adi,gc-adc-small-overload-thresh = < 0x2f >;
    				adi,gc-adc-large-overload-thresh = < 0x3a >;
    				adi,gc-lmt-overload-high-thresh = < 0x320 >;
    				adi,gc-lmt-overload-low-thresh = < 0x2c0 >;
    				adi,gc-dec-pow-measurement-duration = < 0x2000 >;
    				adi,gc-low-power-thresh = < 0x18 >;
    				adi,mgc-inc-gain-step = < 0x02 >;
    				adi,mgc-dec-gain-step = < 0x02 >;
    				adi,mgc-split-table-ctrl-inp-gain-mode = < 0x00 >;
    				adi,agc-attack-delay-extra-margin-us = < 0x01 >;
    				adi,agc-outer-thresh-high = < 0x05 >;
    				adi,agc-outer-thresh-high-dec-steps = < 0x02 >;
    				adi,agc-inner-thresh-high = < 0x0a >;
    				adi,agc-inner-thresh-high-dec-steps = < 0x01 >;
    				adi,agc-inner-thresh-low = < 0x0c >;
    				adi,agc-inner-thresh-low-inc-steps = < 0x01 >;
    				adi,agc-outer-thresh-low = < 0x12 >;
    				adi,agc-outer-thresh-low-inc-steps = < 0x02 >;
    				adi,agc-adc-small-overload-exceed-counter = < 0x0a >;
    				adi,agc-adc-large-overload-exceed-counter = < 0x0a >;
    				adi,agc-adc-large-overload-inc-steps = < 0x02 >;
    				adi,agc-lmt-overload-large-exceed-counter = < 0x0a >;
    				adi,agc-lmt-overload-small-exceed-counter = < 0x0a >;
    				adi,agc-lmt-overload-large-inc-steps = < 0x02 >;
    				adi,agc-gain-update-interval-us = < 0x3e8 >;
    				adi,fagc-dec-pow-measurement-duration = < 0x40 >;
    				adi,fagc-lp-thresh-increment-steps = < 0x01 >;
    				adi,fagc-lp-thresh-increment-time = < 0x05 >;
    				adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = < 0x08 >;
    				adi,fagc-final-overrange-count = < 0x03 >;
    				adi,fagc-gain-index-type-after-exit-rx-mode = < 0x00 >;
    				adi,fagc-lmt-final-settling-steps = < 0x01 >;
    				adi,fagc-lock-level = < 0x0a >;
    				adi,fagc-lock-level-gain-increase-upper-limit = < 0x05 >;
    				adi,fagc-lock-level-lmt-gain-increase-enable;
    				adi,fagc-lpf-final-settling-steps = < 0x01 >;
    				adi,fagc-optimized-gain-offset = < 0x05 >;
    				adi,fagc-power-measurement-duration-in-state5 = < 0x40 >;
    				adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
    				adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = < 0x0a >;
    				adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable;
    				adi,fagc-rst-gla-if-en-agc-pulled-high-mode = < 0x00 >;
    				adi,fagc-rst-gla-large-adc-overload-enable;
    				adi,fagc-rst-gla-large-lmt-overload-enable;
    				adi,fagc-rst-gla-stronger-sig-thresh-above-ll = < 0x0a >;
    				adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable;
    				adi,fagc-state-wait-time-ns = < 0x104 >;
    				adi,fagc-use-last-lock-level-for-set-gain-enable;
    				adi,rssi-restart-mode = < 0x03 >;
    				adi,rssi-delay = < 0x01 >;
    				adi,rssi-wait = < 0x01 >;
    				adi,rssi-duration = < 0x3e8 >;
    				adi,ctrl-outs-index = < 0x00 >;
    				adi,ctrl-outs-enable-mask = < 0xff >;
    				adi,temp-sense-measurement-interval-ms = < 0x3e8 >;
    				adi,temp-sense-offset-signed = < 0xce >;
    				adi,temp-sense-periodic-measurement-enable;
    				adi,aux-dac-manual-mode-enable;
    				adi,aux-dac1-default-value-mV = < 0x00 >;
    				adi,aux-dac1-rx-delay-us = < 0x00 >;
    				adi,aux-dac1-tx-delay-us = < 0x00 >;
    				adi,aux-dac2-default-value-mV = < 0x00 >;
    				adi,aux-dac2-rx-delay-us = < 0x00 >;
    				adi,aux-dac2-tx-delay-us = < 0x00 >;
    				en_agc-gpios = < 0x06 0x62 0x00 >;
    				sync-gpios = < 0x06 0x63 0x00 >;
    				reset-gpios = < 0x06 0x64 0x00 >;
    				enable-gpios = < 0x06 0x65 0x00 >;
    				txnrx-gpios = < 0x06 0x66 0x00 >;
    				phandle = < 0x0d >;
    			};
    
    			nhd@0 {
    				compatible = "syncoam,seps525";
    				reg = < 0x01 >;
    				status = "ok";
    				spi-max-frequency = < 0x989680 >;
    				spi-cpol;
    				spi-cpha;
    				rotate = < 0x00 >;
    				fps = < 0x32 >;
    				buswidth = < 0x08 >;
    				txbuflen = < 0xfa00 >;
    				reset-gpios = < 0x06 0x40 0x00 >;
    				dc-gpios = < 0x06 0x41 0x00 >;
    				debug = < 0x00 >;
    			};
    		};
    
    		spi@e0007000 {
    			compatible = "xlnx,zynq-spi-r1p6";
    			reg = < 0xe0007000 0x1000 >;
    			status = "okay";
    			interrupt-parent = < 0x01 >;
    			interrupts = < 0x00 0x31 0x04 >;
    			clocks = < 0x02 0x1a 0x02 0x23 >;
    			clock-names = "ref_clk\0pclk";
    			#address-cells = < 0x01 >;
    			#size-cells = < 0x00 >;
    			num-cs = < 0x04 >;
    			is-decoded-cs = < 0x00 >;
    
    			adis16460@0 {
    				compatible = "adi,adis16460";
    				reg = < 0x00 >;
    				spi-max-frequency = < 0xf4240 >;
    				spi-cpol;
    				spi-cpha;
    				interrupt-parent = < 0x06 >;
    				interrupts = < 0x52 0x01 >;
    			};
    		};
    
    		spi@e000d000 {
    			clock-names = "ref_clk\0pclk";
    			clocks = < 0x02 0x0a 0x02 0x2b >;
    			compatible = "xlnx,zynq-qspi-1.0";
    			status = "okay";
    			interrupt-parent = < 0x01 >;
    			interrupts = < 0x00 0x13 0x04 >;
    			reg = < 0xe000d000 0x1000 >;
    			#address-cells = < 0x01 >;
    			#size-cells = < 0x00 >;
    			is-dual = < 0x00 >;
    			num-cs = < 0x01 >;
    
    			ps7-qspi@0 {
    				#address-cells = < 0x01 >;
    				#size-cells = < 0x01 >;
    				spi-tx-bus-width = < 0x01 >;
    				spi-rx-bus-width = < 0x04 >;
    				compatible = "n25q256a\0jedec,spi-nor";
    				reg = < 0x00 >;
    				spi-max-frequency = < 0x2faf080 >;
    
    				partition@qspi-fsbl-uboot {
    					label = "qspi-fsbl-uboot";
    					reg = < 0x00 0xe0000 >;
    				};
    
    				partition@qspi-uboot-env {
    					label = "qspi-uboot-env";
    					reg = < 0xe0000 0x20000 >;
    				};
    
    				partition@qspi-linux {
    					label = "qspi-linux";
    					reg = < 0x100000 0x500000 >;
    				};
    
    				partition@qspi-device-tree {
    					label = "qspi-device-tree";
    					reg = < 0x600000 0x20000 >;
    				};
    
    				partition@qspi-rootfs {
    					label = "qspi-rootfs";
    					reg = < 0x620000 0xce0000 >;
    				};
    
    				partition@qspi-bitstream {
    					label = "qspi-bitstream";
    					reg = < 0x1300000 0xd00000 >;
    				};
    			};
    		};
    
    		memory-controller@e000e000 {
    			#address-cells = < 0x01 >;
    			#size-cells = < 0x01 >;
    			status = "disabled";
    			clock-names = "memclk\0apb_pclk";
    			clocks = < 0x02 0x0b 0x02 0x2c >;
    			compatible = "arm,pl353-smc-r2p1\0arm,primecell";
    			interrupt-parent = < 0x01 >;
    			interrupts = < 0x00 0x12 0x04 >;
    			ranges;
    			reg = < 0xe000e000 0x1000 >;
    
    			flash@e1000000 {
    				status = "disabled";
    				compatible = "arm,pl353-nand-r2p1";
    				reg = < 0xe1000000 0x1000000 >;
    				#address-cells = < 0x01 >;
    				#size-cells = < 0x01 >;
    			};
    
    			flash@e2000000 {
    				status = "disabled";
    				compatible = "cfi-flash";
    				reg = < 0xe2000000 0x2000000 >;
    				#address-cells = < 0x01 >;
    				#size-cells = < 0x01 >;
    			};
    		};
    
    		ethernet@e000b000 {
    			compatible = "cdns,zynq-gem\0cdns,gem";
    			reg = < 0xe000b000 0x1000 >;
    			status = "okay";
    			interrupts = < 0x00 0x16 0x04 >;
    			clocks = < 0x02 0x1e 0x02 0x1e 0x02 0x0d >;
    			clock-names = "pclk\0hclk\0tx_clk";
    			#address-cells = < 0x01 >;
    			#size-cells = < 0x00 >;
    			phy-handle = < 0x07 >;
    			phy-mode = "rgmii-id";
    
    			phy@0 {
    				device_type = "ethernet-phy";
    				reg = < 0x00 >;
    				marvell,reg-init = < 0x03 0x10 0xff00 0x1e 0x03 0x11 0xfff0 0x00 >;
    				phandle = < 0x07 >;
    			};
    		};
    
    		ethernet@e000c000 {
    			compatible = "cdns,zynq-gem\0cdns,gem";
    			reg = < 0xe000c000 0x1000 >;
    			status = "disabled";
    			interrupts = < 0x00 0x2d 0x04 >;
    			clocks = < 0x02 0x1f 0x02 0x1f 0x02 0x0e >;
    			clock-names = "pclk\0hclk\0tx_clk";
    			#address-cells = < 0x01 >;
    			#size-cells = < 0x00 >;
    		};
    
    		mmc@e0100000 {
    			compatible = "arasan,sdhci-8.9a";
    			status = "okay";
    			clock-names = "clk_xin\0clk_ahb";
    			clocks = < 0x02 0x15 0x02 0x20 >;
    			interrupt-parent = < 0x01 >;
    			interrupts = < 0x00 0x18 0x04 >;
    			reg = < 0xe0100000 0x1000 >;
    			disable-wp;
    		};
    
    		mmc@e0101000 {
    			compatible = "arasan,sdhci-8.9a";
    			status = "disabled";
    			clock-names = "clk_xin\0clk_ahb";
    			clocks = < 0x02 0x16 0x02 0x21 >;
    			interrupt-parent = < 0x01 >;
    			interrupts = < 0x00 0x2f 0x04 >;
    			reg = < 0xe0101000 0x1000 >;
    		};
    
    		slcr@f8000000 {
    			u-boot,dm-pre-reloc;
    			#address-cells = < 0x01 >;
    			#size-cells = < 0x01 >;
    			compatible = "xlnx,zynq-slcr\0syscon\0simple-mfd";
    			reg = < 0xf8000000 0x1000 >;
    			ranges;
    			phandle = < 0x08 >;
    
    			clkc@100 {
    				u-boot,dm-pre-reloc;
    				#clock-cells = < 0x01 >;
    				compatible = "xlnx,ps7-clkc";
    				fclk-enable = < 0x0f >;
    				clock-output-names = "armpll\0ddrpll\0iopll\0cpu_6or4x\0cpu_3or2x\0cpu_2x\0cpu_1x\0ddr2x\0ddr3x\0dci\0lqspi\0smc\0pcap\0gem0\0gem1\0fclk0\0fclk1\0fclk2\0fclk3\0can0\0can1\0sdio0\0sdio1\0uart0\0uart1\0spi0\0spi1\0dma\0usb0_aper\0usb1_aper\0gem0_aper\0gem1_aper\0sdio0_aper\0sdio1_aper\0spi0_aper\0spi1_aper\0can0_aper\0can1_aper\0i2c0_aper\0i2c1_aper\0uart0_aper\0uart1_aper\0gpio_aper\0lqspi_aper\0smc_aper\0swdt\0dbg_trc\0dbg_apb";
    				reg = < 0x100 0x100 >;
    				ps-clk-frequency = < 0x1fca055 >;
    				phandle = < 0x02 >;
    			};
    
    			rstc@200 {
    				compatible = "xlnx,zynq-reset";
    				reg = < 0x200 0x48 >;
    				#reset-cells = < 0x01 >;
    				syscon = < 0x08 >;
    			};
    
    			pinctrl@700 {
    				compatible = "xlnx,pinctrl-zynq";
    				reg = < 0x700 0x200 >;
    				syscon = < 0x08 >;
    			};
    		};
    
    		dmac@f8003000 {
    			compatible = "arm,pl330\0arm,primecell";
    			reg = < 0xf8003000 0x1000 >;
    			interrupt-parent = < 0x01 >;
    			interrupt-names = "abort\0dma0\0dma1\0dma2\0dma3\0dma4\0dma5\0dma6\0dma7";
    			interrupts = < 0x00 0x0d 0x04 0x00 0x0e 0x04 0x00 0x0f 0x04 0x00 0x10 0x04 0x00 0x11 0x04 0x00 0x28 0x04 0x00 0x29 0x04 0x00 0x2a 0x04 0x00 0x2b 0x04 >;
    			#dma-cells = < 0x01 >;
    			#dma-channels = < 0x08 >;
    			#dma-requests = < 0x04 >;
    			clocks = < 0x02 0x1b >;
    			clock-names = "apb_pclk";
    			phandle = < 0x0f >;
    		};
    
    		devcfg@f8007000 {
    			compatible = "xlnx,zynq-devcfg-1.0";
    			interrupt-parent = < 0x01 >;
    			interrupts = < 0x00 0x08 0x04 >;
    			reg = < 0xf8007000 0x100 >;
    			clocks = < 0x02 0x0c 0x02 0x0f 0x02 0x10 0x02 0x11 0x02 0x12 >;
    			clock-names = "ref_clk\0fclk0\0fclk1\0fclk2\0fclk3";
    			syscon = < 0x08 >;
    			phandle = < 0x04 >;
    		};
    
    		efuse@f800d000 {
    			compatible = "xlnx,zynq-efuse";
    			reg = < 0xf800d000 0x20 >;
    		};
    
    		timer@f8f00200 {
    			compatible = "arm,cortex-a9-global-timer";
    			reg = < 0xf8f00200 0x20 >;
    			interrupts = < 0x01 0x0b 0x301 >;
    			interrupt-parent = < 0x01 >;
    			clocks = < 0x02 0x04 >;
    		};
    
    		timer@f8001000 {
    			interrupt-parent = < 0x01 >;
    			interrupts = < 0x00 0x0a 0x04 0x00 0x0b 0x04 0x00 0x0c 0x04 >;
    			compatible = "cdns,ttc";
    			clocks = < 0x02 0x06 >;
    			reg = < 0xf8001000 0x1000 >;
    		};
    
    		timer@f8002000 {
    			interrupt-parent = < 0x01 >;
    			interrupts = < 0x00 0x25 0x04 0x00 0x26 0x04 0x00 0x27 0x04 >;
    			compatible = "cdns,ttc";
    			clocks = < 0x02 0x06 >;
    			reg = < 0xf8002000 0x1000 >;
    		};
    
    		timer@f8f00600 {
    			interrupt-parent = < 0x01 >;
    			interrupts = < 0x01 0x0d 0x301 >;
    			compatible = "arm,cortex-a9-twd-timer";
    			reg = < 0xf8f00600 0x20 >;
    			clocks = < 0x02 0x04 >;
    		};
    
    		usb@e0002000 {
    			compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2";
    			status = "okay";
    			clocks = < 0x02 0x1c >;
    			interrupt-parent = < 0x01 >;
    			interrupts = < 0x00 0x15 0x04 >;
    			reg = < 0xe0002000 0x1000 >;
    			phy_type = "ulpi";
    			dr_mode = "otg";
    			xlnx,phy-reset-gpio = < 0x06 0x07 0x00 >;
    		};
    
    		usb@e0003000 {
    			compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2";
    			status = "disabled";
    			clocks = < 0x02 0x1d >;
    			interrupt-parent = < 0x01 >;
    			interrupts = < 0x00 0x2c 0x04 >;
    			reg = < 0xe0003000 0x1000 >;
    			phy_type = "ulpi";
    		};
    
    		watchdog@f8005000 {
    			clocks = < 0x02 0x2d >;
    			compatible = "cdns,wdt-r1p2";
    			interrupt-parent = < 0x01 >;
    			interrupts = < 0x00 0x09 0x01 >;
    			reg = < 0xf8005000 0x1000 >;
    			timeout-sec = < 0x0a >;
    		};
    	};
    
    	aliases {
    		ethernet0 = "/amba/ethernet@e000b000";
    		serial0 = "/amba/serial@e0001000";
    		serial1 = "/amba/serial@e0000000";
    	};
    
    	memory {
    		device_type = "memory";
    		reg = < 0x00 0x40000000 >;
    	};
    
    	chosen {
    		stdout-path = "/amba@0/uart@E0001000";
    	};
    
    	clocks {
    
    		clock@0 {
    			#clock-cells = < 0x00 >;
    			compatible = "adjustable-clock";
    			clock-frequency = < 0x2625a00 >;
    			clock-accuracy = < 0x30d40 >;
    			clock-output-names = "XO_40MHz";
    			phandle = < 0x09 >;
    		};
    
    		clock@2 {
    			#clock-cells = < 0x00 >;
    			compatible = "fixed-clock";
    			clock-frequency = < 0x16e3600 >;
    			clock-output-names = "24MHz";
    			phandle = < 0x0a >;
    		};
    	};
    
    	ad9361-refclk-gpio-gate@0 {
    		#clock-cells = < 0x00 >;
    		compatible = "gpio-gate-clock";
    		clocks = < 0x09 >;
    		enable-gpios = < 0x06 0x69 0x00 >;
    		clock-output-names = "ad9361_ext_refclk";
    		phandle = < 0x05 >;
    	};
    
    	usb-ulpe-gpio-gate@0 {
    		#clock-cells = < 0x00 >;
    		compatible = "gpio-gate-clock";
    		clocks = < 0x0a >;
    		enable-gpios = < 0x06 0x09 0x01 >;
    	};
    
    	fpga-axi@0 {
    		compatible = "simple-bus";
    		#address-cells = < 0x01 >;
    		#size-cells = < 0x01 >;
    		ranges;
    
    		i2c@41600000 {
    			compatible = "xlnx,axi-iic-1.02.a\0xlnx,xps-iic-2.00.a";
    			reg = < 0x41600000 0x10000 >;
    			interrupt-parent = < 0x01 >;
    			interrupts = < 0x00 0x3a 0x04 >;
    			clocks = < 0x02 0x0f >;
    			clock-names = "pclk";
    			#address-cells = < 0x01 >;
    			#size-cells = < 0x00 >;
    
    			adm1166@68 {
    				compatible = "adi,adm1166";
    				reg = < 0x6a >;
    			};
    
    			ad7291-ccbox@2f {
    				compatible = "adi,ad7291";
    				reg = < 0x2f >;
    			};
    
    			eeprom@50 {
    				compatible = "at24,24c32";
    				reg = < 0x50 >;
    			};
    
    			adau1761@3a {
    				compatible = "adi,adau1761";
    				reg = < 0x3a >;
    				clocks = < 0x0b >;
    				clock-names = "mclk";
    				#sound-dai-cells = < 0x00 >;
    				phandle = < 0x11 >;
    			};
    
    			ts3a227e@3b {
    				compatible = "ti,ts3a227e";
    				reg = < 0x3b >;
    				interrupt-parent = < 0x06 >;
    				interrupts = < 0x4b 0x08 >;
    				ti,micbias = < 0x01 >;
    				ti,insertion-debounce-time = < 0x06 >;
    			};
    
    			rtc@68 {
    				compatible = "dallas,ds3232";
    				reg = < 0x69 >;
    				interrupt-parent = < 0x06 >;
    				interrupts = < 0x50 0x08 >;
    			};
    
    			ltc2942@64 {
    				compatible = "lltc,ltc2942";
    				reg = < 0x64 >;
    				lltc,resistor-sense = < 0x14 >;
    				lltc,prescaler-exponent = < 0x05 >;
    			};
    
    			adp5061@14 {
    				compatible = "adi,adp5061";
    				reg = < 0x14 >;
    			};
    		};
    
    		dma@7c400000 {
    			compatible = "adi,axi-dmac-1.00.a";
    			reg = < 0x7c400000 0x10000 >;
    			#dma-cells = < 0x01 >;
    			interrupts = < 0x00 0x39 0x04 >;
    			clocks = < 0x02 0x10 >;
    			phandle = < 0x0c >;
    
    			adi,channels {
    				#size-cells = < 0x00 >;
    				#address-cells = < 0x01 >;
    
    				dma-channel@0 {
    					reg = < 0x00 >;
    					adi,source-bus-width = < 0x40 >;
    					adi,source-bus-type = < 0x02 >;
    					adi,destination-bus-width = < 0x40 >;
    					adi,destination-bus-type = < 0x00 >;
    				};
    			};
    		};
    
    		dma@7c420000 {
    			compatible = "adi,axi-dmac-1.00.a";
    			reg = < 0x7c420000 0x10000 >;
    			#dma-cells = < 0x01 >;
    			interrupts = < 0x00 0x38 0x04 >;
    			clocks = < 0x02 0x10 >;
    			phandle = < 0x0e >;
    
    			adi,channels {
    				#size-cells = < 0x00 >;
    				#address-cells = < 0x01 >;
    
    				dma-channel@0 {
    					reg = < 0x00 >;
    					adi,source-bus-width = < 0x40 >;
    					adi,source-bus-type = < 0x00 >;
    					adi,destination-bus-width = < 0x40 >;
    					adi,destination-bus-type = < 0x02 >;
    				};
    			};
    		};
    
    		cf-ad9361-lpc@79020000 {
    			compatible = "adi,axi-ad9361-6.00.a";
    			reg = < 0x79020000 0x6000 >;
    			dmas = < 0x0c 0x00 >;
    			dma-names = "rx";
    			spibus-connected = < 0x0d >;
    		};
    
    		cf-ad9361-dds-core-lpc@79024000 {
    			compatible = "adi,axi-ad9361-dds-6.00.a";
    			reg = < 0x79024000 0x1000 >;
    			clocks = < 0x0d 0x0d >;
    			clock-names = "sampl_clk";
    			dmas = < 0x0e 0x00 >;
    			dma-names = "tx";
    		};
    
    		mwipcore@43c00000 {
    			compatible = "mathworks,mwipcore-axi4lite-v1.00";
    			reg = < 0x43c00000 0xffff >;
    		};
    
    		axi-sysid-0@45000000 {
    			compatible = "adi,axi-sysid-1.00.a";
    			reg = < 0x45000000 0x10000 >;
    		};
    
    		axi-i2s@77600000 {
    			compatible = "adi,axi-i2s-1.00.a";
    			reg = < 0x77600000 0x1000 >;
    			dmas = < 0x0f 0x00 0x0f 0x01 >;
    			dma-names = "tx\0rx";
    			clocks = < 0x02 0x0f 0x0b >;
    			clock-names = "axi\0ref";
    			#sound-dai-cells = < 0x00 >;
    			phandle = < 0x10 >;
    		};
    	};
    
    	leds {
    		compatible = "gpio-leds";
    
    		led0 {
    			label = "led0:red";
    			gpios = < 0x06 0x38 0x00 >;
    			linux,default-trigger = "heartbeat";
    		};
    
    		led1 {
    			label = "led1:green";
    			gpios = < 0x06 0x37 0x00 >;
    			linux,default-trigger = "heartbeat";
    		};
    
    		led2 {
    			label = "led2:blue";
    			gpios = < 0x06 0x36 0x00 >;
    			linux,default-trigger = "heartbeat";
    		};
    	};
    
    	gpio-keys-power {
    		#address-cells = < 0x01 >;
    		#size-cells = < 0x00 >;
    		compatible = "gpio-keys";
    
    		power {
    			interrupt-parent = < 0x06 >;
    			interrupts = < 0x4c 0x02 >;
    			label = "Power";
    			linux,code = < 0x74 >;
    			gpio-key,wakeup;
    		};
    	};
    
    	gpio-keys-nav-switch {
    		compatible = "gpio-keys";
    		#address-cells = < 0x01 >;
    		#size-cells = < 0x00 >;
    		interrupt-parent = < 0x06 >;
    
    		s5 {
    			label = "Right";
    			linux,code = < 0x6a >;
    			interrupts = < 0x65 0x01 >;
    			debounce-interval = < 0x0a >;
    		};
    
    		s3 {
    			label = "Left";
    			linux,code = < 0x69 >;
    			interrupts = < 0x67 0x01 >;
    			debounce-interval = < 0x0a >;
    		};
    
    		s4 {
    			label = "Down";
    			linux,code = < 0x6c >;
    			interrupts = < 0x66 0x01 >;
    			debounce-interval = < 0x0a >;
    		};
    
    		s2 {
    			label = "Up";
    			linux,code = < 0x67 >;
    			interrupts = < 0x68 0x01 >;
    			debounce-interval = < 0x0a >;
    		};
    
    		s1 {
    			label = "Enter";
    			linux,code = < 0x1c >;
    			interrupts = < 0x6f 0x01 >;
    			debounce-interval = < 0x0a >;
    		};
    	};
    
    	rotary {
    		compatible = "rotary-encoder";
    		gpios = < 0x06 0x70 0x01 0x06 0x71 0x01 >;
    		linux,axis = < 0x08 >;
    		rotary-encoder,steps = < 0x18 >;
    		rotary-encoder,steps-per-period = < 0x02 >;
    		rotary-encoder,rollover;
    		rotary-encoder,relative-axis;
    	};
    
    	poweroff {
    		compatible = "gpio-poweroff";
    		gpios = < 0x06 0x4d 0x01 >;
    	};
    
    	audio_clock {
    		compatible = "fixed-clock";
    		#clock-cells = < 0x00 >;
    		clock-frequency = < 0xbb8000 >;
    		phandle = < 0x0b >;
    	};
    
    	pzsdr_sound {
    		compatible = "simple-audio-card-adrv936x-box";
    		simple-audio-card,name = "ADRV9361-Z7035 ADAU1761";
    		simple-audio-card,widgets = "Microphone\0Mic In\0Headphone\0Headphone Out";
    		simple-audio-card,routing = "Headphone Out\0LHP\0Headphone Out\0RHP\0Mic In\0MICBIAS\0LINN\0Mic In";
    
    		simple-audio-card,dai-link@0 {
    			format = "i2s";
    
    			cpu {
    				sound-dai = < 0x10 >;
    				frame-master;
    				bitclock-master;
    			};
    
    			codec {
    				sound-dai = < 0x11 >;
    			};
    		};
    	};
    };
    

  • From the dts file, it seems that Line 751 is for the RX while Line 773 is for the TX. Both specify Channel 0. What are the address offsets for Channel 1 Q, Channel 2 I and Channel 2 Q?

  • They all go to the same DMA as interleaved samples. DMA width is 64 -> 4x 16-bit samples

    -Travis

  • So if the first sample address for RX DMA is 0x7C400000, is the next sample address 0x7C400008?

  • This depends on what channels are enabled. Samples are 2 bytes each and interleaved. They follow the channel ordering as well. 0x7C400008 could be the next channel's sample or a sample from the same channel.

    The easiest way to pull data from the buffers is to use the libiio interface which will tell you the stride between samples based on the driver itself. An example is here: https://github.com/analogdevicesinc/libiio/blob/master/examples/ad9361-iiostream.c

    -Travis

  • I have another question. I set a variable in Simulink called TriggerCapture defined as boolean and set its interface as AXI4 with its interface mapping at x"104". If I want to read this variable from my PackRF hardware, what is the register address to read?

  • It will be whatever address the AXI interface to the IP is mapped to, plus that offset. This is shown in the vivado address table.

    -Travis

  • I checked the Vivado address table and the AXI4 offset address is 0x43C00000. As above, I use TiggerCapture (x"104") to test register writing. I use the follow code to do the register read/write.

    volatile int *addr = (volatile int *)0x43C00104;
    *addr = 0x1;  // write the register

    Instead I got segmentation fault. What is the right way to read/write registers?

  • You cannot arbitrary access memory like that. You must go through devmem or the proper method is to use a driver.

    -Travis